Download Tutorial 1 - Solution

TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
1.
Describe briefly the following terms as applied to an ideal operational amplifier:
i)
iii)
v)
vii)
Virtual ground;
Input dc offset voltage;
Input bias current;
Slew rate.
ii)
iv)
vi)
Virtual short;
Output dc offset voltage;
Input offset current;
SOLUTION
1.
i)
In the inverting amplifier shown in the following figure, since the open-loop gain is
very large, the two inputs v1 and v2 must be nearly equal. And since v2 is connected to
ground, v1 must be at zero potential. The fact that v1 is at zero potential does mean
that the terminal is connected to ground. Rather, the terminal is said to be at virtual
ground.
RF
R1
vI
v1
v2 = 0
ii)
vO
+
In the non-inverting amplifier shown in the following figure, the negative feedback
forces v1 to track v2. Thus v1 and v2 are essentially equal. Such condition is referred to
as virtual short.
RF
R1
v1
v2
~
Jan 2011
-
+
vO
vI
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
iii)
The input dc offset voltage (VOS) is defined as the input differential voltage that must
be applied to the open-loop op-amp to produce zero output voltage.
iv)
The output dc offset voltage is defined as the measured output voltage when the input
voltage is zero
v)
If the input stage is symmetrical with all corresponding elements matched the input
bias currents IB1 and IB2 are equal i.e. I B1  I B 2 . However, in a practical op-amp, due
to component (input transistors) mismatched, I B1  I B 2 . In such a case, the input
bias current IB is the average of the two i.e.
IB 
vi)
I B1  I B 2
2
The input offset current IOS is the net difference between the input currents IB1 and IB2
i.e.
I OS  I B1 - I B 2
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
vii)
The slew rate is defined as the maximum rate of change in the output voltage per unit
of time
Slew rate 
Vout
t
V
t
0
Vout  Vmax - - Vmax 
V in
t  t 2 - t1
+V max
V
0
t1
t2
t
-V max
V out
QUESTION
2.
List down five parameters of an op-amp and give comparisons between an ideal and a
practical op-amp with regards to these parameters and hence draw the equivalent circuit of
an ideal op-amp a simplified equivalent circuit of a practical op-amp.
SOLUTION
Jan 2011
PARAMETERS
IDEAL OP-AMP
PRACTICAL OP-AMP
Input resistance
Infinite
500 k – 2 M
Output resistanced
Zero
20  – 100 
Open-loop voltage gain
Infinite
20k – 200k
Bandwidth
Infinite
Few kHz
Output dc voltage
zero
1 mV – 2 mV
Input bias current
zero
pA – 10 A
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
The equivalent circuit representation of an ideal op-amp
A simplified equivalent circuit representation
of a practical op-amp
Jan 2011
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
3.
With the aid of suitable diagrams, give brief description of the terms DIFFERENTIAL
MODE INPUT and COMMON-MODE INPUT as applied to an op-amp and hence give the
mathematical definition for the term COMMON-MODE REJECTION RATIO (CMRR).
SOLUTION
In the differential mode input, the input signal is applied across the inverting and noninverting terminals of an op-amp as shown in Figure 3(a). Since an op-amp responses to the
difference between the two input signals at its input terminals, differential mode input may
also be represented as shown Figure 3(b) but we must ensure that vi1  vi2.
vd
+
~
-
vO
Figure 3(a) : Differential mode input
+
vi1
~
vi2
vO
~
Figure 3(b) : Differential mode input when vi1  vi2
From Figure 3(a), the differential gain Ad is;
vO
vd
From Figure 3(b); vd  vi1 - vi 2 . Hence;
Ad 
Ad 
Jan 2011
vO
vi1 - vi 2
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
Since, in both Figures 3(a) and (b), the op-amp is under open loop condition, the differential
gain Ad is also known as the open-loop gain AOL. Thus.
AOL 
vO
vi1 - vi 2
which is normally extremely large.
In Figure 3(b), if we make vi1 = vi2, it is known as common mode input i.e. both input
terminals receive identical input signal. Another way to illustrate this condition is shown in
Figure 3(c).
+
v CM
-
~
vO
Figure 3(c) : Common mode input
The common-mode gain ACM is defined as;
ACM 
vO
vCM
which is normally very small.
The common-mode rejection ratio CMRR is defined as the ratio of differential gain Ad to
common-mode gain ACM namely;
CMRR 
Ad
ACM
CMRR is normally expressed in dB, thus;
 A 
CMRR dB  20 log  d 
 ACM 
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
4.
Consider an operational amplifier with ideal parameters except that the open-loop gain is
finite and is equal to Ao. The op-amp is operated as an inverting amplifier with the input
signal voltage vi applied through R1 and the output signal vo is fed back to the input through
RF.
a)
b)
Draw the circuit diagram.
Derive an expression for the close-loop gain, ACL.
c)
Show that if AOL   , then the close-loop gain is;
ACL  -
RF
R1
SOLUTION
a)
The circuit diagram
RF
R1
vi
Ao
vo
+
b)
Expression for closed-loop gain
i2
vi
0
R1
i1
v1
RF
Ao
vo
+
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
 1
vi
1  vo
  v1  
R1
 R1 RF  RF
vi - v1 v1 - vo

R1
RF
vo  Ao v1
v1 
(A)
vo
Ao
Substituting for v1 in (A);
 1
vi
1
1 

 vo 

R1
 Ao R1 Ao RF RF 
 R  R1 - Ao R1 
vi

 vo  F
R1
A
R
R
o 1 F


ACL 
c)
vo
Ao RF
RF


vi RF  R1 - Ao R1 RF R1

- R1
Ao Ao
From the expression for ACL above, as Ao   ;
RF
0
Ao
and
R1
0
Ao
Therefore;
ACL  -
RF
R1
QUESTION
5.
The parameters of the op-amp in Figure 1 are ideal except that the open-loop gain Ao is
finite. Derive an expression for the close-loop gain ACL and hence show that when the openloop gain Ao is infinite, the close-loop gain ACL can be expressed as;
ACL  1 
Jan 2011
RF
R1
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
RF
R1
vo
+
vi
~
Figure 1
SOLUTION
RF
0
R1
v1
i1
-
Ao
v2
vi
i2
vo
+
~
 R1  RF

 R1 RF
v1 v1 - vo

R1
RF
vo  Ao v1 - v2   Ao v1 - vi 

v
v1  o
RF

v1 
vo
 vi
Ao
Substituting for v1;
 R1  RF

 R1 RF
 v
 vo

 vi   o
 Ao
 RF
Rearranging;
vo  R1  RF
-
RF  R1 RF
Jan 2011
 vo  R1  RF

 
 Ao  R1 RF

vi

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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
ACL 
When Ao   ; the term
vo

vi
R1  RF
R  RF
R1 - 1
Ao
R1  RF
 0 and the closed-loop voltage gain becomes;
Ao
ACL 
R1  RF
R
 1 F
R1
R1
QUESTION
6.
Analyze the circuit in Figure 2 to obtain the dc values VE, VC1, VC2, IC1 and IC2, under
quiescent condition (i.e. when the input signal voltages vs1 = vs2 = 0). Assume Q1 and Q2 are
perfectly matched pair where  = 150 and VBE(on) = 0.7 V.
V CC = 15 V
RC
5 k
VC1
IC1
RC
5 k
VC2
IC2
Q2
Q1
vs2
vs1
VE
RE
3.3 k
V EE = -15 V
Figure 2
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
SOLUTION
When the input signal is zero i.e. vs1 = vs2 = 0, the circuit may be redrawn as follows;
V CC = 15 V
RC
5 k
VC1
IC2
IC1
VE
V BE 1
IE1
RC
5 k
VC2
V BE 2
IE2
IE
RE
3.3 k
V EE = -15 V
VE  0 - VBE  -0.7 V
VRE  VBE - VEE  -0.7 - - 15  14.3 V
IE 
VRE 14.3

 4.333 mA
RE 3.3k
I E1  I E 2 
I C1  I C 2 
I E 4.333

2
2
I E1  I E 2  2.167 mA
I E1 150  2.167mA

 2.152 mA
1 
151
I C1  I C 2  2.152 mA
VC1  VC 2  VCC - I C1 RC  15 - 2.152mA  5k
VC1  VC 2  4.238 V
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
7.
Perform an ac analysis on the circuit in Figure 3 to obtain an expression for the voltage gain
Av where;
.
v
Av  O
vI
V CC
RC
RC
.
vO
Q2
Q1
vI
~
RE
.
V EE
Figure 3
SOLUTION
Using the hybrid- model for both Q1 and Q2, the small-signal equivalent circuit becomes as
follows;
~
vO
iB1
vI
 1i B 1
r1
RC
iB2
RC
iC1
r2
iC2
iE2
iE1
i RE
Jan 2011
 2i B 2
RE
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
Assuming perfectly matched transistors;
iB1  iB 2  iB ;
iE1  iE 2  iE ;
1   2   ;
r 1  r 2  r
iE  1   iB
and
iC1  iC 2  iC
Considering that;
iC  i B
The equivalent circuit may be labeled as follows;
~
vO
iB
vI
iB
r
RC
iB
iB
RC
iB
r
iB
(1+ )i B
(1+ )i B
2(1+ )i B
RE
Referring to the equivalent circuit above;
iB 
v I - 21   iB RE
r
vO  -i B RC  -
The common-mode voltage gain;
Jan 2011
iB 
vI
r  21   iB RE
RC
vI
r  21   i B RE
Av 
vO
RC
vI
r  21   i B RE
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
Perform an ac analysis on the circuit in Figure 4 to to show that as RE   , the singleended differential voltage gain Ad is given by the expression;
8.
Ad 
vO
R
- C
vi1 - vi 2
2r
.
V CC
RC
RC
.
vo
Q2
Q1
vi1
~
~
Figure 4
vi2
RE
.
V EE
SOLUTION
vI1
~
vO
iB1
iB1
r
RC
iB1
(1+ )i B 1
RC
iB2
r
~
vI2
iB2
(1+ )i B 2
vE
(1+ )i B 1
+(1+ )i B 2
1   iB1  1   iB 2 
Jan 2011
iB2
RE
vE
RE
(1)
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
iB1 
vI 1 - vE
r
iB 2 
(2)
vI 2 - vE
r
(3)
Substituting (2) and (3) into (1)
1    v
r
I1
 v I 2 - 2v E  
vE
RE
Rearranging the terms;
1   vI 1  v I 2 
r
 1 21   


v E
r 
 RE
Therefore;
vI 1  vI 2 
vE 
r
1   RE
(4)
2
The output voltage is;
vO  - iB1 RC
Substituting for iB1 as in equation (2)
vO  - RC
v I 1 - v E RC
- vI 1  vE 

r
r
Substituting for vE as in (4);




RC 

vI 1  vI 2  
vO 
- vI 1 

r
r 
 2

1   RE 

As RE  
vO 
RC 
r
Or;
vO  -
 - vI 1 

RC
2r
vI 1  vI 2    RC  - v
2


r


I1

vI 1 vI 2 


2
2 
vI 1 - vI 2 
The single-ended differential voltage gain is therefore;
Ad 
Jan 2011
vO
R
- C
vi1 - vi 2
2r
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
QUESTION
9.
The inverting amplifier in Figure 5 receives an input signal for the source vs. The source is
capable of delivering a maximum current of 4 A at a peak voltage of 0.2 V. Design the
amplifier for a gain |Av| of 20. Assume that the op-amp is ideal.
R2
R1
~
-
Figure 5
vo
vs
+
SOLUTION
9.
To limit the current drawn from vs at 4 A at a peak voltage of of 0.2 V, the amplifier must
have an input resistance Ri;
Ri 
0.2
 50 k
4  10 -6
R1  Ri  50 k
Av 
Jan 2011
R2
 20
R1
R2  20R1  1 M
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TUTORIAL 1 - SOLUTION
EKT214 : ANALOG ELECTRONICS CIRCUIT II; SEMESTER 2; 2010/2011
Jan 2011
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