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Design-Manufacturing Interface Formulations and Algorithms Andrew B. Kahng, CSE 291 Spring 2001 [email protected], http://vlsicad.ucsd.edu Subwavelength Optical Lithography Subwavelength Gap since .35 m EUV, X-rays, E-beams all > 10 years out huge investment in > 30 years of optical litho infrastructure knobs: direction, phase, aperture, pattern context Mask Types Bright Field Dark Field – opaque features – transparent features – transparent background – opaque background Clear areas Opaque (chrome) areas Phase Shifting Masks conventional mask phase shifting mask glass Chrome Phase shifter 0 E at mask 0 0 E at wafer 0 0 I at wafer 0 Impact of PSM PSM enables smaller transistor gate lengths Leff – “critical” polysilicon features only (gate Leff) – faster device switching faster circuits – better critical dimension (CD) control improved parametric yield – all features on polysilicon layer, local interconnect layers – smaller die area more $/wafer (“full-chip PSM” == BIG win) Alternative: build a $10B fab with equipment that won’t exist for 5+ years Data points – exponential increase in price of CAD technology for PSM – 25 nm gates (!!!) manufactured with 248nm DUV steppers (NTI + MIT Lincoln Labs, announced June 2000); 90nm gates in production at Motorola, Lucent (since late 1999) Double-Exposure Bright-Field PSM 0 18 180 0 + = The Phase Assignment Problem Assign 0, 180 phase regions such that critical features with width (separation) < B are induced by adjacent phase regions with opposite phases Bright Field (Dark Field) 180 0 180 0 Key: Global 2-Colorability If there is an odd cycle of “phase implications” layout cannot be manufactured – layout verification becomes a global, not local, issue 180 0 ? 180 180 0 180 Critical features: F1,F2,F3,F4 F2 F1 F4 F3 F2 F1 OppositePhase Shifters (0,180) F4 F3 S3 F2 S4 S1 F1 S8 F4 S7 S2 S5 F3 S6 Shifters: S1-S8 PROPER Phase Assignment: – Opposite phases for opposite shifters – Same phase for overlapping shifters S3 F2 S4 S1 F1 S8 F4 S7 S2 S5 F3 S6 Phase Conflict Proper Phase Assignment is IMPOSSIBLE Phase Conflict Resolution S3 F2 S4 S1 F1 S8 F4 S7 S2 Phase Conflict S5 F3 S6 feature shifting to remove overlap Phase Conflict Resolution S3 F2 S4 S1 F1 S8 F4 S7 S2 F3 Phase Conflict feature widening to turn conflict into non-conflict How will VLSI CAD deal with PSM ? UCLA: first comprehensive methodology for PSM-aware layout design Approach: partition responsibility for phaseassignability – Type 1 : good layout practices (local geometry) – (open) problem: is there a set of “design rules” that guarantees phase-assignability of layout ? (no T’s, no doglegs, even fingers...) – Type 2 : automatic phase conflict resolution / bipartization (global colorability) – Type 3 : enabling reuse of layout (free composability) – problem: how can we guarantee reusability of phase-assigned layouts, such that no odd cycles can occur when the layouts are composed together in a larger layout ? Type 1 Rules: Local Geometry Rules Local Geometry Rules Features classified as critical or noncritical – according to dimension and inter-layer interactions – e.g., poly geometry critical if width less than 180nm, OR if width less than 220nm but over active region Spacing rules depend on feature criticality – e.g., minimum spacing between parallel critical is different from minimum spacing between parallel noncritical Particular feature shapes can be prohibited – “no critical-width T's” rule is required – “no critical-width doglegs” rule is discretionary Local Geometry Rules: Example Cases Type 2 Rules: Automatic Conflict Resolution Compaction-Oriented Approach Analyze input layout Find min-cost set of perturbations needed to eliminate all “odd cycles” Induce constraints for output layout – i.e., PSM-induced (shape, spacing) constraints Compact to get phase-assignable layout Key: Minimize the set of new constraints, i.e., break all odd cycles in conflict graph by deleting a minimum number of edges. Conflict Graph Dark Field: build graph over feature regions – edge between two features whose separation is < B Bright Field: build graph over shifter regions – shifters for features whose width is < B – two edge types – adjacency edge between overlapping phase regions : endpoints must have same phase – conflict edge between shifters on opposite side of critical feature: endpoints must have opposite phase Conflict Graph G Dark Field: green = feature; pink = conflict Bright Field: conflict edge adjacency edge conflict graph G conflict graph G Optimal Odd Cycle Elimination dark green = feature; pink = conflict T-join of odd-degree nodes in D conflict graph G dual graph D Optimal Odd Cycle Elimination dark green = feature; pink = conflict T-join of odd-degree nodes in D - assign phases: dark green and purple - remaining pink conflicts correctly handled corresponds to broken edges in original conflict graph The T-join Problem How to delete minimum-cost set of edges from conflict graph G to eliminate odd cycles? Construct geometric dual graph D = dual(G) Find odd-degree vertices T in D Solve the T-join problem in D: –find min-weight edge set J in D such that –all T-vertices have odd degree –all other vertices have even degree Solution J corresponds to desired min-cost edge set in conflict graph G Solving T-join in Sparse Graphs Reduction to matching – construct a complete graph T(G) – vertices = T-vertices – edge costs = shortest-path cost – find minimum-cost perfect matching Typical example = sparse (not always planar) graph – note that conflict graphs are sparse – #vertices = 1,000,000 – #edges 5 #vertices – # T-vertices 10% of #vertices = 100,000 Drawback: finding APSP too slow, memory-consuming – #vertices = 100,000 #edges in T(G) = 5,000,000,000 Solving T-join: Reduction to Matching Desirable properties of reduction to matching: –exact (i.e., optimal) –not much memory (say, 2-3X more) –leads to very fast solution Solution: gadgets! –replace each edge/vertex with gadgets s.t. matching all vertices in gadgeted graph T-join in original graph T-join Problem: Reduction to Matching replace each vertex with a chain of triangles one more edge for T-vertices in graph D: m = #edges, n = #vertices, t = #T in gadgeted graph: 4m-2n-t vertices, 7m-5n-t edges cost of red edges = original dual edge costs cost of (black) edges in triangles = 0 vertex T vertex T Example of Gadgeted Graph Gadgeted graph Dual Graph black + red edges == min-cost perfect matching Results Layout1 Testcase polygons edges 3769 12442 Algorithm edges runtime Greedy 2650 0.56 GW 1612 3.33 Exact 1468 19.88 New Gadgets 1468 3.62 Layout2 polygons edges 9775 26520 edges runtime 2722 3.66 1488 5.77 1346 16.67 1346 5.17 Layout3 polygons edges 18249 51402 edges runtime 6180 5.38 3280 14.47 2958 74.33 2958 17.9 • Runtimes in CPU seconds on Sun Ultra-10 • Greedy = breadth-first-search bicoloring • GW = Goemans/Williamson95 heuristic • Cook/Rohe98 for perfect matching • Integration w/compactor: saves 9+% layout area vs. GW S3 F2 S4 S1 F1 S8 F4 S7 S2 S5 F3 S6 Can distinguish between use of shifting, widening DOFs Black points - features Blue - shifter overlap Red - extra nodes to distinguish opposite shifters Bipartization Problem: delete min # of nodes (or edges) to make graph bipartite - blue nodes: shifting - red nodes: widening Bipartization by node deletion is NP-hard (GW98: 9/4-approx) Recap New fast, optimal algorithms for edge-deletion bipartization – Fast T-join using gadgets – applicable to any AltPSM phase conflict graphs Approximate solution for node-deletion bipartization – Goemans-Williamson98 9/4-approximation – If node-deletion cost < 1.5 edge deletion, GW is better than edge deletion UCLA code at IBM Burlington, NTI, ... Type 3 Rules: Standard-Cell Composability for P&R Flows Conflict Graph for Cell-Based Layouts Coarse view: at level of connected components of conflict graphs within each cell master – each component independently phase-assignable (2k versions) – treated as a single “vertex” in coarse-grain conflict graph cell master A cell master B connected component edge in coarse-grain conflict graph Guidelines PSM must be “transparent” to auto-P&R – “free composability” is the cornerstone of the cell-based methodology! – focus on poly layer we are concerned with placer, not router – polygon layout information currently not in placement vocabulary – available abstractions: pin EEQs/LEQs, overlap layer geometries Competitive context for placer – extremely competitive runtime regimes – nontrivial cost of checking placement phase-assignability is unacceptable Iteration between placer and separate tool is unacceptable P&R tool MUST deliver guaranteed phase-assignable poly layer Types of Composability Same-row composability – any cell can be placed immediately adjacent (in the same row) to any other cell Adj-row composability – any cell can be placed in an adjacent cell row to any other cell, with the two cells having intersecting x-spans Four cases of cell libraries (G = guaranteed; NG = not guaranteed) – Case 1: adj-G, same-G – most-constrained cell layout; most transparent to placer – Case 2: adj-G, same-NG – Case 3: adj-NG, same-G – Case 4: adj-NG, same-NG – least-constrained cell layout; least transparent to placer Case 2: Adj-G, Same-NG Blue vertices, edges = graph of phase assignment “dependencies” Case 3: Adj-NG, Same-G Blue vertices, edges = graph of phase assignment “dependencies” Case 1: Adj-G, Same-G Solution 1: “no restrictions on the cell layout” – create cell abstractions such that placer runs in “normal” mode – e.g., pre-bloat (by 1 site) cells that have critical poly near left/right boundary – e.g., create overlap layer obstacles corresponding to critical poly near top/bottom boundary Solution 2: smart rules to restrict cell layout – e.g., every pair of boundary-CP features from the same cell must be non-interfering – definition: two features are non-interfering if they are in different connected components of the cell’s phase conflict graph – no boundary-CP feature is “near” two different sides of its cell – these two restrictions composability guaranteed (no odd cycles possible) Solution 3: dumb rules to restrict cell layout – all cells have 250nm-wide 0-phase boundary (IBM style) Cases 2,4: Same-NG Each (sub)row checked separately, post-placement Basic tool: cell compatibility table – library is precharacterized by M2 two-dimensional arrays Aij, one array for each possible pairing of cells with Ci to the left of Cj – Aij<p,q> = minimum site separation at which Cip can be placed adjacent to Cjq (p = 1, …, Vi and q = 1, …, Vj) – example: M = 500 with 16 versions of each master cell < 30 MB storage Goals: – (1) if phase assignment possible, return set of versions for each of the cell instances – (2) if not possible, return set of versions plus set of inserted feedthroughs (extra sites) such that minimum perturbation is achieved Conclusions Broad PSM effects: DSM P&R, Custom IC, PV, … Three-part comprehensive EDA methodology for BFPSM Partitions responsibility for phase-assignability among three “rule” types – layout creation, automatic conflict resolution, and composability Support for key subflows – interactive full-custom, automated full-custom, automatic cellbased P&R, layout migration Density Control for CMP Chemical-mechanical polishing (CMP) – applied to interlayer dielectrics (ILD) and inlaid metals – polishing pad wear, slurry composition, pad elasticity make this a very difficult process step Cause of CMP variability – pad deforms over metal feature – greater ILD thickness over dense regions of layout – “dishing” in sparse regions of layout – huge part of chip variability budget used up (e.g., 4000Å ILD variation across-die) Min-Variation Objective Relationship between oxide thickness and local feature density oxide thickness filling min min’ max density Minimizing variation in window density over layout preferable to satisfying lower and upper density bounds Density Control for CMP Layout density control – density rules minimize yield impact – uniform density achieved by post-processing, insertion of dummy features Performance verification (PV) flow implications – accurate estimation of filling is needed in PD, PV tools (else broken performance analysis flow) – filling geometries affect capacitance extraction by > 50% – is a multilayer problem (coupling to critical nets, contacting restrictions, active layers, other interlayer dependencies) Density Rules Modern foundry rules specify layout density bounds to minimize impact of CMP on yield Density rules control local feature density for w w windows – e.g., for metal layer every 2000um 2000um window must be between 35% and 70% filled Filling = insertion of "dummy" features to improve layout density – typically via layout post-processing in PV / TCAD tools – affects vital design characteristics (e.g., RC extraction) – accurate knowledge of filling is required during physical design and verification Need for Density Awareness in Layout Performance verification flow: RCX ROM Delay Calc Timing/Noise Analysis Filling/slotting geometries affect RC extraction -15 VICTIM LAYER TOTAL CAPACITANCE (10 Same layer-i neighbors? N N Y Y Fill layers i-1, i+1? N Y N Y = 3.9 2.43 3.73 4.47 5.29 (1.0) (1.54) (1.84) (2.18) F) = 2.7 1.68 2.58 3.09 3.66 (1.0) (1.54) (1.84) (2.18) Up to 1% error in extracted capacitance Reliability also affected (e.g. slotting of power stripes) Need for Density Awareness in Layout Performance verification flow: RCX ROM Delay Calc Timing/Noise Analysis Can be considered as ``single-layer’’ problem -15 Middle Victim Conductor Total Capacitance (10 F) Fill layer offset N N Y Y Fill geometry 10 1 11 10 1 11 = 3.9 3.776 3.750 3.777 3.745 (1.0) (0.99) (1.00) (0.99) = 2.7 2.614 2.596 2.615 2.593 (1.0) (0.99) (1.00) (0.99) • Caveat: contacting, active layers, other interlayer dependencies Limitations of Current Techniques Current techniques for density control have three key weaknesses: (1) only the average overall feature density is constrained, while local variation in feature density is ignored (2) density analysis does not find true extremal window densities - instead, it finds extremal window densities only over fixed set of window positions (3) fill insertion into layout does not minimize the maximum variation in window density Layout Density Control Flow Density Analysis • find total feature area in each window • find maximum/minimum total feature area over all w w windows • find slack (available area for filling) in each window Fill synthesis • compute amounts, locations of dummy fill • generate fill geometries Exact Max-Density Window Analysis For each pivot rectangle R do – find density of ww window W that abuts R on top and right – while W intersects R do – slide W right till intersection with other rectangle edge – record changes in density R W Fixed r-Dissection Regime Feature area density bounds enforced only for fixed set of w w windows Layout partitioned by r2 distinct fixed dissections Each w w window is partitioned in r2 tiles tile fixed r-dissection with r = 4 overlapping windows Drawbacks of Fixed r-Dissection Analysis If all w w windows of fixed r-dissection have density U, there may be floating w w window with density min{1, U + 1/r -1/(4r2)} Fixed-dissection algorithm is inaccurate Exact algorithm is slow = O(k2) Shrunk and Bloated Windows Standard window = fixed r-dissection w w window Floating window = arbitrary w w window Bloated window = standard window bloated by one tile Shrunk window = standard window shrunk by one tile Any floating window is contained in one bloated window and contains one shrunk window standard window bloated window shrunk window floating window Multilevel Approach Estimation: – max floating window density max bloated window density – min floating window density min shrunk window density Zooming: – remove standard windows in underfilled bloated windows – subdivide remaining tiles and find area of new bloated windows Terminate subdivision when either: – # of rectangles is small (run exact density analysis), or – (max bloated density)/(max standard density) (say, =1%) Multilevel Algorithm Tiles = list of all windows (r =1) Accuracy = While Accuracy > 1+ find are in each bloated and standard window MAX = max area of standard window BMAX = max area of bloated window refine Tiles = list of tiles from bloated windows of area MAX subdivide each tile in Tiles into 4 subtiles Accuracy = BMAX / MAX Output max standard window density = MAX/ w2 Runtime of Multilevel Algorithm Each iteration decreases difference in area between bloated and standard window by half Original difference is 3w2 Main loop terminates after t iterations: 3w2/2t 2 Maximum t is O(log(w/ ) Runtime is O((n/w * log(w/ ))2) Filling Problem Given design rule-correct layout of k disjoint rectilinear features in nn region Find design rule-correct filled layout –no fill geometry is added within distance B of any layout feature –no fill is added into any window that has density U –minimum window density in the filled layout is maximized (or has density lower bound L) Filling Problem in Fixed-Dissection Regime Given – fixed r-dissection of layout – feature area[T] in each tile T – slack[T] = area available for filling in T – maximum window density U Find total fill area p[T] to add in each T s.t. any w w window W has density U and minW T W (area[T] + p[T]) is maximized Fixed-Dissection LP Formulation Maximize M (lower bound on window density) subject to: –For any tile T: 0 p[T] pattern slack[T] –For any window W: T W p[T] U w2 M T W (p[T] + area[T]) (pattern = max achievable pattern area density) Fixed-Dissection LP Formulation one variable and two constraints per tile two constraints per window Multilevel LP Formulation Use multilevel density analysis in LP Tiles[r] = list of fixed r-dissection tiles from bloated windows of area MAX Saved tiles = subdivided Tiles[r] minus Tiles[r+1] Saved windows = all standard windows W for which area is found Multilevel LP uses only constraints for saved tiles and saved windows Multilevel LP Formulation Saved tiles have different sizes: tiles with more feature area are more subdivided ML LP has one variable and two constraints per tile and two constraints per window Floating Deviation LP Formulation Floating deviation = the difference between max and min floating window density Floating deviation max bloated window density - min shrunk window density Floating deviation LP: – For any bloated window W: T W p[T] U w2 – For any shrunk window W: M T W (p[T] + area[T]) Floating Deviation LP Formulation one variable and two constraints per tile one constraint per shrunk window one constraint per bloated window Hierarchical Density Control Hierarchical filling = master cell filling Tile T Subcells Cell C Slack[C] Buffer C1 Features C2 Hierarchical LP Formulation For any cell instance C of master cell C and tile T, [C,T] is portion of slack[C] in intersection of C with T: [C,T] = slack(C T)/slack[C] New variable d[C] per each master cell C: d[C] = filling per master cell C New constraints: – For total amount of filling added into tile T: p[T] = C T d[C] [C,T] – For amount of filling added into each master cell C: 0 d[C] pattern slack[C] Synthesis of Filling Patterns Given area of filling pattern p[i,j], insert filling pattern into tile T[i,j] uniformly over available area Desirable properties of filling pattern –uniform coupling to long conductors –either grounded or floating Basket-Weave Pattern Each vertical/horizontal crossover line has same overlap capacitance to fill Grounded Pattern Fill with horizontal stripes, then span with vertical lines Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Hierarchical Dummy Fill for Process Uniformity Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UCSD, UVA and GSU) http://vlsicad.cs.ucla.edu Outline Chemical Mechanical Planarization & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research CMP and Interlevel Dielectric Thickness Chemical-Mechanical Planarization (CMP) = wafer surface planarization Uneven features cause polishing pad to deform ILD thickness Features Interlevel-dielectric (ILD) thickness feature density Insert dummy features to decrease variation Dummy features ILD thickness Objectives of Density Control Objective for Manufacture = Min-Var minimize “window” density variation subject to upper bound on window layout density Objective for Design = Min-Fill minimize total amount of filling subject to bound on window layout density variation Filling Problem Statement Given – rule-correct layout in n n region – window size = w w – window density upper bound U, buffer distance B Add dummy fill to the layout with Min-Var and/or Min-Fill objective such that no fill is added – within given buffer distance B of any layout feature – into any overfilled window that already has density U Fixed-Dissection Regime Monitor only fixed set of w w windows – “offset” = w/r (example shown: w = 4, r = 4) Partition n x n layout into overlapping fixed dissections Each w w window is partitioned into r2 tiles w w/r tile Overlapping windows n Layout Density Models Spatial Density Model window density sum of tiles feature area Effective Density Model (more accurate) window density weighted sum of tiles' feature area – weights decrease from window center to boundaries tile Feature Area Slack Area Requirements for Dummy Filling Estimation of RC parasitics, gate/interconnect delays and device reliability in PD & verification Compatibility of master cell, macro characterizations with later insertion of dummy fill Consistent with design hierarchy to avoid data explosion and maintain verifiability Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research Linear Programming Approaches Min-Var Objective (Kahng et al.) – Maximize: M – Subject to: for any tile 0 p[T] slack[T] for any window TW (p[T]+area[T]) U M TW (p[T] + area[T]) p[T] = fill area of tile – spatial density model Min-Fill Objective (Wong et al.) – Minimize: fill amount – Subject to: for any tile 0 p[T] slack[T] LowerB 0(T) UpperB MAX 0(T) - MIN 0(T) 0(T) = effective density of tile T – effective density model Monte-Carlo Approach Min-Var objective – pick the tile for next filling geometry randomly – higher priority (based on max covering window density) of tile higher probability to be filled – lock tile if any containing window is overfilled – update window priorities Min-Fill objective – Fill-Deletion problem – delete as much fill as possible while maintaining min window density L. – Min-Fill Monte-Carlo algorithm – – – – if (min covering-window density < L) lock the tile randomly select unlocked tile by its priority delete a filling geometry from tile update priorities of tiles Iterated Monte-Carlo Approach Repeat forever – run Min-Var Monte-Carlo with max window density U – exit if no change in minimum window density – run Min-Fill Monte-Carlo with min window density M No Improvement LP vs. Monte-Carlo for Flat Filling LP impractical runtime for large layouts r-dissection solution may be suboptimal for 2r dissections essential rounding error for small tiles Monte-Carlo very efficient: O((nr/w)log(nr/w)) time scalability: handle large values of r accuracy: reasonably high comparing with LP Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research Hierarchical Filling Problem Dummy fill are added only to master cells Each cell of the filled layout is a filled version of the corresponding original master cell Two instances of a master cell features Flat fill solution Original layout Hierarchical fill solution Why Hierarchical Filling? Hierarchical characteristics of design flows Enables and faster verification of the filled layout Decreases data volume for Challenges of Hierarchical Filling Density constraints apply to all instances of the master Interactions / interferences at master cell boundaries Always gives worse results than flat solutions Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research Why Not LP? Complexity caused by constraints – need a huge number of variables and constraints for each window, cell instance, and feasible fill position Overlaps between cell instances – ownership of overlapping regions – unavailable regions for fill Monte-Carlo Hierarchical Filling 1 1 1 1 1 1 1 1 density analysis 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Original layout Computing Slack Hierarchically Overlaps between master and features the same 2 instances of different master masters Exclude the overlapping regions buffer Master cell slack slack Drawbacks of Hierarchical Filling Sparse or unfilled region in the solution – the overlaps – bloat regions Cause high layout density variation features ! ! ! ! three instances of a master cell Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research k-way Master Cell Splitting Create k copies of master cell Ci Link contained master cells C` with new copies Randomly replace Ci in master cells with new copies C1 C2 C2 C1 Ci C 1` C 2` Ci C 1` C 2` C1 C2 Ci,1 Ci,2 C 1` C2` C 1` C 2` C1 C 1` C 2` Ci,2 k : hierarchical layout flat layout C2 C 1` C 2` Ci,1 Hybrid Hierarchical / Flat Filling features Purely hierarchical fill phase Split-hierarchical phase Flat fill `cleanup` phase three instances of a master cell Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research Computational Experience Testbed Implementation features – grid slack computation – GDSII input – hierarchical polygon database – C++ under Solaris – doughnut area computation – wraparound density analysis and synthesis – different pattern types Test cases: Artificial hierarchical layouts based on single cell, different magnification factors Test Case layout size #rectangles Case 1 260,000 216 Case 2 288,000 432 Case 3 504,000 540 Computational Experience DenModel data OrgLayout Hier H+F H+S H+S+F Flat 645 1562 2321 2834 5219 OrgLayout Hier H+F H+S H+S+F Flat 2081 2451 4368 4374 13974 OrgLayout Hier H+F H+S H+S+F Flat 4995 7472 9690 12212 17695 Effective Density Spatial Density MinDen #fill data MinDen #fill Testcase 1 0.291 0.07 0.369 2608 1054 0.11 5136 0.655 4312 2758 0.335 6053 0.525 4166 1552 0.17 7601 0.676 5522 2908 0.339 8114 0.735 5732 5732 0.403 5219 Testcase 2 0.145 0.167 0.248 16972 2142 0.272 16060 0.32 17460 5630 0.393 16430 0.365 18126 4531 0.41 17494 0.383 20829 7234 0.421 17500 0.443 23415 23415 0.527 13974 Testcase 3 0.091 0 0.157 20320 4449 0.071 22566 0.371 25332 9461 0.532 25043 0.159 22990 8575 0.102 23622 0.394 25700 13285 0.54 26144 0.483 31204 31204 0.547 17695 Comparison among hierarchical, flat and hybrid filling approaches Outline Chemical-Mechanical Polishing & Filling Problem Previous Works – Linear programming approaches – Monte-Carlo (MC) approaches Our Contributions: – Hierarchical filling problem – Hierarchical filling algorithm – Hybrid hierarchical / flat filling approach Computational Experience Summary and Future Research Summary and Future Research Hierarchical filling problem for CMP uniformity Practical pure hierarchical filling algorithm Practical hybrid hierarchical filling approach – trade off runtime, solution quality and data volume Ongoing research – Alternate pure hierarchical filling heuristics – Reusable solutions – Fill compression – Layer interactions (filling/cheesing, dual-material, …)