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CMOS Digital Integrated Circuits Analysis and Design Chapter 5 MOS Inverters: Static Characteristics 1 Introduction • Positive logic convention – “1” represents high voltage of VDD – “0” represents low voltage of 0 • The inverter threshold voltage, Vth – The input voltage, 0<Vin<VthBoutput VDD – The input voltage, Vth<Vin<VDDBoutput 0 2 General circuit structure of an nMOS inverter • The driver transistor – The input voltage Vin=VGS – The output voltage Vout=VDS – The source and the substrate are ground, VSB=0 • The load device – Terminal current IL, terminal voltage VL 3 Voltage transfer characteristic (VTC) • The VTC describing Vout as a function of Vin under DC condition • Very low voltage level – Vout=VOH – nMOS off, no conducting current, voltage drop across the load is very small, the output voltage is high • As Vin increases – The driver transistor starts conducting, the output voltage starts to decrease – The critical voltage point, dVout/dVin=-1 • The input low voltage VIL • The input high voltage VIH • Determining the noise margins • Further increase Vin – Output low voltage VOL, when the input voltage is equal to VOH – The inverter threshold voltage Vth • Define as the point where Vin=Vout 4 Noise immunity and noise margin • NML=VIL-VOL • NMH=VOH-VIH • The transition region, uncertain region 5 Power and area consideration • The DC power dissipation – The product of its power supply voltage and the amount of current down from the power supply during steady state or in standby mode – PDC=VDDIDC=(VDD/2)[IDC(Vin=low)+IDC(Vin=high)] – In deep submicron technologies • Subthreshold current Bmore power consumption • The chip area – To reduce the area of the MOS transistor • The gate area of the MOS transistor • The product of W and L 6 Resistive-load inverter • Operation mode – Vin<VT0, cut off • No current, no voltage drop across the load resistor • Vout=VDD – VT0≤Vin<Vout+VT0, saturation • Initially, VDS>Vin-VT0 • I = k n ⋅ (V − V )2 R in T0 2 • With Vin↑B Vout↓ – Vin≥Vout+VT0, linear • The output voltage continues to decrease 2 • I R = k n ⋅ 2 ⋅ (Vin − VT 0 ) ⋅Vout − Vout 2 [ ] 7 Calculation of VOH, VOL • Calculation of VOH – Vout=VDD-RLIR – When Vin is low ⇒ID=IR=0 ⇒VOH=VDD • Calculation of VOL – Assume the input voltage is equal to VOH – Vin-VT0≥Vout ⇒ linear region – VDD − Vout IR = RL Using KCL for the output node, i.e. I R = I D [ VDD − VOL k n = ⋅ 2 ⋅ (VDD − VT 0 ) ⋅V0 L − V02L RL 2 ] 1 2 ⋅ V0 L + ⋅ VDD = 0 V02L − 2 ⋅ VDD − VT 0 + k R k R n L n L 2 1 1 2VDD − − VDD − VT 0 + V0 L = VDD − VT 0 + k n RL k R k n RL n L 8 Calculation of VIL, and VIH By definition, VIL is the smaller of the two input voltage at which the slope of the VTC becomes equal to - 1. i.e. dVout /dVin = -1 Vout > Vin - VT0 , saturation region VDD - Vout k n 2 = ⋅ (Vin − VT 0 ) RL 2 − 1 dVout 1 ⋅ = k n ⋅ (Vin − VT 0 ) ⇒ − ⋅ (− 1) = k n ⋅ (Vin − VT 0 ) RL dVin RL VIL = VT 0 + 1 k n RL k R Vout (Vin = VIL ) = VDD − n L 2 2 1 1 ⋅ VT 0 + − VT 0 = VDD − 2k n RL k n RL VIH is the larger of the two voltage points on the VTC at which the slope is equal to - 1 Vout < Vin - VTO , linear region [ VDD -Vout k n 2 = ⋅ 2 ⋅ (Vin − VT 0 ) ⋅Vout − Vout RL 2 ] 1 dVout k n dV dV ⋅ = ⋅ 2 ⋅ (Vin − VT 0 ) ⋅ out − 2Vout ⋅ out 2 RL dVin dVin dVin 1 − ⋅ (− 1) = k n ⋅ (Vin − VT 0 ) ⋅ (− 1) + 2Vout RL − [ VIH = VT 0 + 2Vout − ] 1 k n RL To determine the unknown variables VDD - Vout k n 1 2 = ⋅ 2 ⋅ VT 0 + 2Vout − − VT 0 ⋅ Vout − Vout k n RL RL 2 Vout (Vin = VIH ) = VIH 2 VDD ⋅ 3 k n RL 8 VDD 1 = VT 0 + ⋅ − 3 k n RL k n RL 9 VTC for different knRL • The term knRL plays an important role in determining the shape of the voltage transfer characteristic • knRL appears as a critical parameter in expressions for VOL, VIL, and VIH • knRL can be adjusted by circuit designer • VOH is determine primarily by the power supply voltage, VDD • The adjustment of VOL receives primarily attention than VIL, VIH • Larger knRL ⇒VOL becomes smaller, larger transition slope 10 Example 5.1 11 Power consumption • The average power consumption – When input low, VOL • The driver cut-off, no steady-state current flow, DC power consumption is zero – When input high, VOH • Both driver MOSFET and the load resistor conduct a nonzero current • The output voltage VOL, so the current ID=IR=(VDDVOL)/RL VDD VDD − VOL – P ⋅ DC ( average ) = 2 RL 12 Chip area • The chip area depend on two parameters – The W/L ratio of the driver transistor • Gate area WxL – The value of the resistor RL • Diffused resistor – Sheet resistance 20 to 100Ω/□ – Very large length-to-width rations to achieve resistor values on the order if tens to hundreds of kΩ • Ploysilicon resistor – Doped polysilicon (for gate of the transistor), Rs~20 to 40 Ω/□ – Undoped polysilicon, Rs Rs~10M Ω/□ – The resistance value can not be controlled very accurately B large variation of the VTC – Low power static random access memory (SRAM) 13 Example 5.2 14 Inverters with n-type MOSFET load • The resistive-load inverter – The large area occupied by the load resistor • The main advantage of using a MOSFET as the load device – Smaller silicon area occupied by the transistor – Better overall performance • Enhancement-load nMOS inverter – The saturated enhancement-load inverter • A single voltage supply • A relative simple fabrication process • VOH=VDD-VT,load – The linear enhancement-type load • VOH=VDD • Higher noise margins • Two separate power supply voltage (drawback) – Both type suffer from relatively high stand-by (DC) power dissipation • Not used in any large-scale digital applications 15 Depletion-load nMOS inverter • Slightly more complicated – Channel implant to adjust the threshold voltage • Advantages – Sharp VTC transition better noise margins – Single power supply – Smaller overall layout area – Reduce standby (leakage) current • The circuit diagram – Consisting • A nonlinear load resistor, depletion MOSFET, VT0,load<0 • A nonideal switch (driver) , enhancement MOSFET, VT0,load>0 – The load transistor • VGS=0, always on – VT ,load = VT 0,load + r ( 2φ F + Vout − 2φ F ) When the output voltage is small, Vout < VDD + VT,load The load transistor is in saturation region I D ,load = k n ,load [ ] ⋅ − VT ,load (Vout ) = 2 k n ,load ⋅ VT ,load (Vout ) 2 2 2 For larger output voltage level, Vout > VDD + VT,load The load transistor operates in the linear region I D ,load = k n ,load 2 [ ⋅ 2 VT ,load (Vout ) ⋅ (VDD − Vout ) − (VDD − Vout ) 2 ] 16 Calculation of VOH, VOL, VIL, ViH When Vin is smaller than VT 0 ⇒ driver → off, load → linear region zero drain current, VOH = VDD I D ,load = k n ,load [ ] ⋅ 2 VT ,load (VOH ) ⋅ (VDD − VOH ) − (VDD − VOH ) = 0 2 2 To calculate the output low VOL assume, Vin = VOH = VDD ⇒ driver → linear region, load → saturation region [ [ ] ] k driver k 2 2 ⋅ 2 ⋅ (VOH − VT 0 ) ⋅ VOL − VOL = load ⋅ − VT ,load (VOL ) 2 2 VOL = VOH − VT 0 − (VOH − VT 0 )2 − kload k driver 2 ⋅ VT ,load (VOL ) 17 Calculation of VOH, VOL, VIL, VIH Calculation of VIL The driver ⇒ saturation region, the load ⇒ linear region k driver k 2 2 ⋅ (Vin − VT 0 ) = load ⋅ 2 VT ,load (Vout ) ⋅ (VDD − Vout ) − (VDD − Vout ) 2 2 Differential both sides with respect to Vin [ ] dVT ,load dV + 2(VDD − Vout ) − T ,load 2 VT ,load (Vout ) − k dVout dVout k driver ⋅ (Vin − VT 0 ) = load ⋅ 2 dV − 2(VDD − Vout ) − T ,load dVout sbustitute dVout /dVin = -1 k VIL = VT 0 + load k driver [ ⋅ Vout − VDD + VT ,load (Vout ) ] Calculation of VIH The driver ⇒ linear region, the load ⇒ saturation region [ ] k driver k 2 2 ⋅ 2 ⋅ (Vin − VT 0 ) ⋅Vout − Vout = load ⋅ [− VT ,load (Vout )] 2 2 Differential both sides with respect to Vin dV k driver ⋅ Vout + (Vin + VT 0 ) out dVin sbustitute dVout /dVin = -1 k VIH = VT 0 + 2Vout + load k driver dVT ,load γ = dVout 2 2φF + Vout dV − Vout out dVin dV = kload ⋅ [− VT ,load (Vout )]⋅ T ,load dVout dV ⋅ [− VT ,load (Vout )]⋅ T ,load dVout dVout ⋅ dVin 18 VTC of depletion load inverters • The general shape of the inverter VTC, and ultimately, the noise margins, are determined by – The threshold voltage of the driver and the load • Set by the fabrication process – The driver-to-load ratio kR=(kdriver/kload) • Determined by the (W/L) ratios of the driver and the load transistor • One important observation – A sharp VTC transition and larger noise margins can be obtained with relative small driver-to-load ratios • Much small area occupation 19 Design of depletion-load inverters • The designable parameters in the inverter circuit are – The power supply voltage VDD • Being determined by other external constrains • Determining the output level high VOH=VDD – The threshold voltages of the driver and the load • Being determined by the fabrication process – The (W/L) ratios of the driver and the load transistor • VT ,load (VOL ) k driver = 2 2(VOH − VT 0 )VOL − VOL kload 2 kR = W k n′ ,driver ⋅ L , kR = W k n′ ,load ⋅ L W driver L driver , kR = W load L load • Since the channel doping densities are not equal – The channel electron mobilities are not equal – K’n,load≠k’n,driver • The actual sizes of the driver and the load transistor are usually determined by other constrains – The current-drive capability – The steady state power dissipation – The transient switching speed 20 Power consideration • The steady-state DC power consumption – Input voltage low • The driver off, Vout=VOH=VDD • No DC power dissipation – Input voltage high, Vin≈VDD and Vout=VOL • K 2 I DC (Vin = VDD ) = load ⋅ [− VT ,load (VOL )] 2 K driver 2 = ⋅ 2 ⋅ (VOH − VT 0 ) ⋅ VOL − VOL 2 Assume the input voltage level low 50% operation [ ] time and high during the other 50% V k 2 PDC = DD ⋅ load ⋅ [− VT ,load (VOL )] 2 2 21 Area consideration • Figure (a) – Sharing a common n+ diffusion region • Saving silicon area – Depletion mode • Threshold voltage adjusted by a donor implant into the channel – (W/L)driver>(W/L)load, ratio about 4 • Figure (b) – Buried contact • Reducing area • For connecting the gate and the source of the load transistor – The polysilicon gate of the depletion mode transistor makes a direct ohmic with the n+ source diffusion – The contact window on the intermediate diffusion area can be omitted 22 Example 5.3 (1) 23 Example 5.3 (2) 24 Example 5.3 (3) 25 CMOS inverter • Complementary push-pull – – • Two important advantages – – • High input BnMOS driver, pMOS load Low input BpMOS driver, nMOS load Virtually negligible steady state power dissipation VTC exhibits a full output voltage swing between 0V and VDD, transition is very sharp Latch up problem – – Formation of two parasitic bipolar transistors Preventing • Guard rings 26 Circuit operation • Region A: Vin<VT0,n – nMOS off, pMOS on B ID,n=ID,p=0, Vout=VOH=VDD • Region B: Vin>VT0,n – nMOS saturation, the output voltagedecreases – The critical voltage VIL, (dVout/dVin)=-1 is located within this region – As the output further decreases BpMOS enter saturation, boundary of region C • Region C: – If nMOS saturation B VDS,n≥VGS,nVT0,n ⇔ Vout ≥Vin-VT0,n – If pMOS saturation B VDS,n≤VGS,pVT0,p ⇔ Vout ≤Vin-VT0,p – Both of these conditions for device saturation are illustrated graphically as shaded areas • Region D: Vout<Vin-VT0,p – The criical point VIH • Region E: Vin>VDD+VT0,p – Vout=VOL=0 27 Circuit operation • The nMOS and the pMOS transistors an be seen as nearly ideal switches – The current drawn from the power supply in both these steady state points region A and region E • Nearly equal to zero • The only current Breverse biased S, D leakage current – The CMOS inverter can drive any load • Interconnect capacitance • Fan-out logic gates • Either by supplying current to the load, or by sinking current from the load 28 The steady-state input-out voltage characteristics 29 Calculation of VIL, VIH nMOS saturation, pMOS linear [ ] k kn 2 2 ⋅ (VGS ,n − VT 0,n ) = p ⋅ 2 ⋅ (VGS , p − VT 0, p )⋅ VDS , P − VDS ,p 2 2 k kn 2 2 ⋅ (Vin − VT 0,n ) = p ⋅ 2 ⋅ (Vin − VDD − VT 0, p )⋅ (Vout − VDD ) − (Vout − VDD ) 2 2 dV dV k n ⋅ (Vin − VT 0,n ) = k p ⋅ (Vin − VDD − VT 0, p )⋅ out + (Vout − VDD ) − (Vout − VDD ) ⋅ out dVin dVin substituting Vin = VIL and (dVout /dVin ) = -1 [ ] k n ⋅ (VIL − VT 0.n ) = k p ⋅ (2Vout − VIL + VT 0, p − VDD ) VIL = 2Vout + VT 0, p − VDD + k RVT 0,n where k R = 1 + kR kn kp nMOS linear, pMOS saturation [ ] kp kn 2 2 ⋅ 2 ⋅ (VGS ,n − VT 0,n )⋅ VDS ,n − VDS ⋅ (VGS , p − VT 0, p ) ,n = 2 2 k kn 2 2 ⋅ 2 ⋅ (Vin − VT 0,n )⋅Vout − Vout = p ⋅ (Vin − VDD − VT 0, p ) 2 2 dV dV k n ⋅ (Vin − VT 0,n )⋅ out + Vout − Vout ⋅ out = k p ⋅ (Vin − VDD − VT 0, p ) dVin dVin substiting Vin = VIH and (dVout /dVin ) = -1 [ ] k n ⋅ (− VIH + VT 0,n + 2Vout ) = k p ⋅ (VIH − VDD − VT 0, p ) VIH = VDD + VT 0, p + k R ⋅ (2Vout + VT 0,n ) 1 + kR 30 Calculation of Vth The inveter th reshold voltage is defined as Vth = Vin = Vout Since the CMOS inverter exhibits large noise margins and very sharp VTC transitio n the inverter t hreshold voltage emerges as an imporant parameter characteri zing the DC performanc e of the inverter For Vin = Vout , both trans istor are in saturation mode kp kn 2 2 ⋅ (VGS , n − VT 0 , n ) = ⋅ (VGS , p − VT 0 , p ) 2 2 kp kn 2 2 ⋅ (Vin − VT 0 , n ) = ⋅ (Vin − V DD − VT 0 , p ) 2 2 kp kp =V Vin ⋅ 1 + + ⋅ (V DD + VT 0 , p ) T 0,n k k n n 1 ⋅ (V DD + VT 0 , p ) kR Vth = 1 1 + k R If Vin = Vth , the output vol tage can actually attain any VT 0 , n + value between (Vth -VT 0 ,n ) and (Vth -VT 0 ,p ) 31 Threshold voltage • The Region C of VTC – Completely vertical • If the channel length modulation effect is neglected, i.e. if λ=0 – Exhibits a finite slope • If λ>0 • Fig 5.22 shows the variation of the inversion (switching) threshold voltage Vth as function of the transconductance ratio kR 32 VTC and power supply current • If input voltage is either smaller than VT0,n, or larger than VDD+VT0,p – Does not draw any significant current from the power supply – Except for small leakage current and subthreshold currents • During low-to-high and high-to-low transitions – Regions B, C, and D – The current being drawn from the power source – Reaching its peak value when Vin=Vth (both saturation mode) 33 Design of CMOS inverters VDD + VT 0, p + Vth Vth − VT 0, n k 1 = ⇒ k R = n = k p Vth − VT 0,n k R VDD + VT 0, p − Vth 2 The switching threshold voltage of an ideal inverter is defined as Vth ,ideal = k 0.5VDD + VT 0, p = substituting 5.74 in 5.73 ⇒ n k V V + 0 . 5 DD T 0, n p ideal 1 ⋅VDD s 2 2 k =1 we can achieve complely symmetric input - output characteristics by setting VT 0 = VT 0 ,n = VT 0 ,p ⇒ n k symmertric p inverter W kn L = kp W µ p C OX ⋅ L µ n C OX ⋅ W µn ⋅ L n = W µp ⋅ L p n p assume tox , Cox have the same value for nMOS and pMOS W 2 W L n µ p 230cm / V ⋅ s W ≈ ⇒ = ≈ 2 . 5 µ n 580cm 2 / V ⋅ s L p W L n L p For a symmetric CMOS inverter with VT 0 ,n = VT 0 ,p and k R = 1 1 1 VIL = ⋅ (3VDD + 2VT 0,n ),VIH = ⋅ (5VDD − 2VT 0,n ) 8 8 VIL + VIH = VDD , NM L = VIL − VOL = VIL , NM H = VOH − VIH = VDD − VIH NM L = N MH = VIL 34 Example 5.4 35 Supply voltage scaling in CMOS inverters • • The static characteristics of the CMOS inverter allow significant variation of supply voltage without affecting the functionality of the basic inverter The CMOS inverter will continue to operate correctly with a supply voltage limit value – min VDD = VT 0,n + VT 0, p – Correct inverter operation will be sustained if at least one of the transistors remains in conduction, for any given voltage – The exact shape of the VTC near e limit value is essentially determined by subthreshold conduction properties • If the power supply voltage is reduced below the sum of the two threshold – The VTC will contain a region in which none of the transistors is conducting – The output voltage level is determine by the previous state of the output – The VTC exhibits a hysteresis behavior 36 Power and area consideration • Power consideration – DC power dissipation of the circuit is almost negligible – The drain current • Source and drain pn junction reverse leakage current • In short channel leakage current • Subthreshold current – However, that the CMOS inverter does conduct a significant amount of current during a switching event • Area consideration 37