Download Sensors

Analog Mixed Signal
Low-Power Microcontrollers
CANDE Workshop
September 11-13, 2003
Taos, New Mexico
Richard B. Brown
Michael S. McCorquodale
brown, [email protected]
1
Richard B. Brown
Fundamental Changes in Microprocessor Market
•
1975 to 2000
–
•
Performance drove demand
Desktop Processors
–
–
US market is saturating
Performance is now adequate
Less motivation to upgrade
–
–
•
Servers and Video Processors
–
•
Battery operation calls for lower power
Where are the new markets?
–
2
Performance is limited by power dissipation
Portable Computers
–
•
Performance is limited by power dissipation
Cost is comparatively more important
Communications, Networking, and Microsystems
Richard B. Brown
Generalized Microsystem
Technologies
MEMS
Analog
Mixed-Signal
Sensor
RFIC/RFMEMS
Antenna
ADC
Sensor/Actuator
Interface
Components
Digital/VLSI
Actuator
Microprocessor
Baseband
Modem
Wireless
Interface
DAC
Clock
Design Tools
FE
Tools
AHDL
Custom
IC Tools
MS-HDL
Custom
IC Tools
VHDL
Synthesis
Tools
AHDL
Custom
RFIC Tools
Electrical, Magnetic, Mechanical, Chemical, Optical, Biological
3
Richard B. Brown
MS-8 Mixed-Signal Microcontroller
TWM Timers
Voltage
MFT Timers
Capacitive
Interface
USART
12-bit
DS
ADC
LPF
PGA
16-bit
Slope
ADC
Amperometric
Interface
Processor
Core
Temp.
Sensor
Control
Analog Interface
Bandgap
Reference
Parallel I/O
Parallel I/O
MAC
CLK
Manager
Prog. Mem.
Data Mem.
K. Kraver, et al., Hilton Head Sensors and Actuators Conf., June 2000.
4
Richard B. Brown
Programmable Gain Amplifier (PGA)
Vinp
Vout •
R3
R1
•
R2
•
•
R2
R3
Vinm
Vout  (Vinp  Vinm )(1 
5
R3
Large input impedance, small
output impedance
Differential to single-ended
conversion
DC Level shifting
Gain controlled by R1: 1, 11,
21, 31, 41, 51, 61 V/ V
R3
Vref
2 R2
)  Vref
R1
Richard B. Brown
Potentiostat
R2
1
Counter
R1
Vref
Vref
Reference
Working
Amperometric
Cell
4
2
Rf
to mux
3
Ramp Generator
Vref
6
Richard B. Brown
Capacitive Sensor Readout
•
•
Programmable internal
reference capacitor
Four input sensor mux
reset
Cf
V(Cs)
Cs
Cref
f
f
reset
7
Vref
f
VA
V Cs   VA
Cs  Cref
Cf
 Vref
Richard B. Brown
Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction
andand
Backannotation
Backannotation
(IC Tool)
Tapeout
Synthesis/APR/Timing
(Synthesizer)
Digital
Library
Analog Macro
Mechanical Macro
Analog Physical Design
(IC Tool)
Digital Design
(HDL)
Custom Analog Design
(SPICE)
Custom
CustomMechanical
MechanicalDesign
Design
(FE)
Digital Specification
Analog Specification
Mechanical Specification
System Specification and Design Partition
8
Mechanical Domain
Digital Macro
Analog Domain
Digital Domain
Macro Automatic Place and Route
(APR and IC Tool)
Richard B. Brown
Process
Library
Bottom-Up Design Methodology Problems
• Time-consuming design iteration
• Cross-domain verification at top level only
• Time-consuming system level simulation, if it
is possible at all
• No opportunity for architectural studies
9
Richard B. Brown
Mixed-Signal Microcontrollers
MS-8
•
Die size:
–
–
•
•
•
10
3.8 x 4.1 mm2 (total)
3.0 x 2.6 mm2 (core)
0.35 mm CMOS
303K transistors
103 I/O, 12 power
Richard B. Brown
Solid-State Sensor Advantages
•
•
•
Sensor Arrays
Convenience
Accuracy
•
•
•
•
Speed
Shelf Life
Cost
Size
Sensicore
Potentiometric
Conductometric
Temperature
Amperometric
3.5 x 4.8 mm
11
ORP
Richard B. Brown
Potable Water Testing
Test
Selective Ligand / Exchanger
Potassium
K+
PU- Valinomycin
10-5 --10-1
Sodium
Na+
PU- Calixarene
10-4 –10-1
Hydronium
pH
Tri-n-dodecylamine
5-9
Calcium
Ca++
PU- ETH 1001
10-5–10-2
Chloride
Cl -
Quaternary Ammonium Poly
10-4 –10-1
Alkalinity
HCO3-
Differential Membrane pH
3x10-3 –10-1
Oxygen
pO2
Silicone/Nafion®
0-300 mmHg
Ammonia
NH3
Silicone- diff. pH or Ammonium ion
10-5 --10-1
Chlorine
Cl2
Cellulose- HOCl reduction
1-10 ppm
Oxidation Reduction
ORP
Potential
0-1000 mV
RTD
5--50 oC
Ti/Pt
0--2000 mS/cm
Temperature
Conductivity
12
Range – (Molar
units)
Water Parameters
Salinity
Richard B. Brown
Sensors
•
Amperometric
–
–
–
–
Three terminal sensors
Voltage applied across
reference and working
electrodes
Current measured at the
auxiliary node
Measured using cyclic
voltammetry
Analyte peaks at varying
voltages
Current depends on
concentration
Dopamine
Serontonin
Cyclic Voltamagrams
13
Richard B. Brown
Neurological Sensor Array
14
Richard B. Brown
Lead Detection by Pulse Voltammetry
-2.00E-07
0 ppb
25 ppb
-1.80E-07
98 ppb
-1.60E-07
195 ppb
390 ppb
-1.40E-07
i, A
-1.20E-07
-1.00E-07
-8.00E-08
-6.00E-08
-4.00E-08
-2.00E-08
0.00E+00
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
E, V
E, V
15
Richard B. Brown
1
Arsenic Detection by Pulse Voltammetry
-1.10E-06
0 ppb
5 ppb
10 ppb
-9.00E-07
15 ppb
20 ppb
Current, A
-7.00E-07
-5.00E-07
-3.00E-07
-1.00E-07
-1.00E-07
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Voltage, V
16
Richard B. Brown
0
Test Setup
LabView
program
data
reset
GND
3V
+12 V
-12 V
2.80 V
0.20 V
3V
CLK
MS-8 Test Board
17
RS-232 buffer
Richard B. Brown
Potentiometric Sensor Demo
18
Richard B. Brown
Potentiometric Sensor Results
1.8
Molarity
1.7
10-6
1.6
10-5
10-4
10-3
10-2
1
10-1
Time Response:
each step represents
a decade jump in
potassium
concentration
PGA gain = 1
1.5
0
200
400
600
800
1000
Time (s)
1.9
Calibration
Curve for
Potassium
V = 0.0525Log(C) + 1.8211
R2 = 0.9998
Output Voltage (V)
Output Voltage (V)
Potassium
1.9
1.8
1.7
1.6
1.5
-7
-6
-5
-4
-3
-2
x
Concentration 10 (M)
19
Richard B. Brown
-1
0
Wireless Integrated MicroSystems (WIMS) ERC
Environmental Sensors
Biomedical Implants
Cochlear
Implant
electroplated
channel
column via
preconcentrator
bistable
polymer
valve
gas
detector
pump
via
Deep
Brain
Implants
stacked
deep-RIE
m-coiled
column
5 mm
distributed
vacuum
pump
1-2 cm
polar / nonpolar
columns
Medtronics
20
Richard B. Brown
Micropower Circuit Goals
Acceptable Performance
–
–
•
Very Low Power
–
–
•
Sensor Interfaces
Wireless/Network Interfaces
Software - C
Power Management
I/O
mC
Baseband RF
ADC
Sensor
Temp
Interface Sensor
Flexibility – Efficiency Trade-off
–
21
Implantable
Single Battery Cell
Compatibility
–
–
–
•
ADC Speed and Accuracy
Digital Processing Speed
Memory
•
Circuit Reusability
Richard B. Brown
WIMS Architecture
•
16-bit Instruction Encoding
– Most Instructions are two bytes
– Power-Efficient ISA
•
16-bit Datapath
– 12-bit sensor data
•
•
•
Loop Cache
Static Logic
Clocks
–
–
–
•
Gated
Frequency Control
Idle/Wake-Up
Minimize Dynamic Power
– Switching Activity
– Memory Accesses
•
Advanced Process
–
–
•
22
Low Voltage
Low Capacitance
C Code Power Efficiency
Richard B. Brown
Design Framework Requirements
• System level simulation support (HDL)
• Cross-domain verification
– Analog and digital electronics, and MEMS
•
•
•
•
•
•
•
23
Finite element simulation
Active device and HDL simulation
Parasitic extraction
Co-simulation of primitives and HDL
Timing verification
HDL synthesis
Automatic place and route
Richard B. Brown
Design Tools Employed
•
Cadence AMS
System modeling, primitive/HDL
co-simulation, and MEMS modeling
•
Cadence Spectre
Analog device level simulation
•
Coventorware
Finite element analysis
•
Artisan
Logic and Memory Libraries
•
Synopsys
Digital synthesis
•
Cadence Silicon Ensemble
Automatic place and route
•
Mentor Graphics Calibre
DRC, ERC, and LVS
24
Richard B. Brown
Top-Down Design Methodology
Behavioral Verification
(Verilog)
Analog Model
(Verilog-A)
Mechanical Model
(Verilog-A)
Custom Analog Design
(SPICE)
Mechanical Design
(Finite Element)
Mechanical Domain
Digital Model
(Verilog)
Analog Domain
Digital Domain
Abstract System Model
(Verilog-AMS: Verilog and Verilog- A)
Cross - Domain Verification
(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)
Digital
Library
Synthesis/APR/Timing
(Synthesis Tool)
Physical Design/Verif.
(IC Tool)
Physical Design/Verif.
(IC Tool)
Extraction, Timing
(Timing Tool)
Parasitic Extraction
(IC Tool)
Parasitic Extraction
(IC Tool)
Process
Library
Cross - Domain Verification
(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog -A with Primitives)
Digital Macro
Analog Macro
Mechanical Macro
Macro Place and Route, Layout Verification: DRC, LVS
(APR and IC Tool)
Layout Parasitic Extraction (LPE) and Backannotation
(IC Tool)
Tapeout
Cross -Domain Verification
(Verilog with updated Verilog - A with interconnect parasitics )
25
M. McCorquodale, DATE, March 2003.
Richard B. Brown
Low-Voltage Analog to Digital Converter
• 0.18 mm TSMC CMOS
• 0.9 – 1.8V Power Supply
• Components
–
–
–
–
Input Buffers
Programmable Gain Amplifier
Second-Order SD Converter
Third-Order Comb Filter
• Features
–
–
–
–
–
26
Subthreshold Operation
Switched-Capacitor Circuits
Clock Doubling
Switched OpAmps
Body Biasing
Richard B. Brown
WIMS Microcontroller
• TSMC 0.18 micron mixed-mode
• 16-bit 3-stage pipeline core
• Analog front end (AFE)
8KB
C
8KB
• MEMS-based clock generator
RAM
O
RAM
• 32 KB on-chip SRAM
• Timer and serial interfaces
R
E
8KB
RAM
• 1.5 million transistors
• 10.24mm2
I
AFE
CLK
O
8KB
RAM
• Estimated Power 24 mW @ 100 MHz
WIMS Microcontroller Fabricated
in TSMC 0.18mm CMOS
R. Senger, et al., DAC, June 2003.
27
Richard B. Brown
Gaps and Solutions
28
Gaps in the Tool Suite
Solutions & Future Direction
MEMS and analog simulation results
not automatically extracted to
behavioral model
Custom and manual extraction:
Requires design automation
Lack of physical verification
for MEMS components
Custom mod. of DRC/LVS decks:
Requires support
No synthesis capabilities for MEMS
from topological or behavioral models
No current solution:
Requires design automation
Inability to port designs
between process technologies
No current solution:
Requires design automation
Richard B. Brown
Synthesis of MEMS Blocks
•
Specific Devices Supported
–
–
–
•
User Interface
–
–
•
29
Calls to MatLab and/or Mathematica
Output
–
–
–
•
•
•
Enter Process Characteristics
Enter Operational Specifications
Proprietary Algorithms Generate Dimensions
–
•
Free-Free Beam Resonators
Clamped-Clamped Beam Resonators
Varactors, several configurations
Plots
Electrical Model
Physical Design Parameters
User Input for further Customization
Generation of Physical Layout
Output of Physical and Electrical Models
Richard B. Brown
IP Repository
30
M. McCorquodale, et al., IFIP VLSI SoC 2003, Darmstadt, Dec. 2003.
Richard B. Brown
Low-Power Microprocessor Status
•
•
Top-Down Design Flow
Low Dynamic and Static Power Dissipation
–
–
–
•
Processor Architecture
–
–
–
–
•
Subthreshold Operation
Bag of Tricks
Power-Aware Software
–
–
31
Transistor Sizing
Datapaths
Low-Power Analog
–
–
•
Efficient Instruction Set
Minimized Memory Accesses
Matched to Tasks
Dynamic Clock Scaling
Power-Efficient Physical Design
–
–
•
Reduced Switching
Scaled Processes, SOI
Subthreshold and Gate Leakage
C Compiler
Loop Cache
Richard B. Brown
Conclusions
•
•
•
Microsystem design methodologies are in their infancy
Current methodologies reflect disparate nature of the technologies
Top-down methodology leverages advances in mixed-signal design
automation
–
•
Gaps in tool suites must be addressed for microsystems design
–
–
–
32
Far superior verification
MEMS synthesis
Better analog synthesis
Automatic model extraction to AMS
Richard B. Brown
Acknowledgements
•
Ph.D. Students
–
•
CAD Vendors
–
33
Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger,
Matthew Guthaus
Cadence, Synopsys, Coventor, Mentor, Artisan
•
National Semiconductor
•
MOSIS
•
IBM
Richard B. Brown