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Hewlett-Packard Company
Ken Boorom, M.S. 382
P.O. Box 15
Boise, Idaho 83707-0015
Phone: 208-396-7905
Fax: 208-396-5433
Joan Lynch
Managing Editor, EDN
275 Washington St
Newton, MA 02458
October 15, 1998
Dear Ms. Lynch:
Thank you for the information regarding my submission of an article to EDN.
I have enclosed an article entitled, “SPICE Simulations can Help Engineers Understand
Signal Integrity Issues in High-Speed Digital Designs.”
The article provides useful information to the majority of engineers in the field who do
not understand signal integrity in high-speed digital systems.
Feel free to contact me with questions or concerns.
Best Regards,
Ken Boorom
M.S.E.E./B.S.E.E. Stanford University
SPICE Simulations Can Help Engineers
Understand Signal Integrity Issues in HighSpeed Digital Systems
As consumers demand higher speed computing systems, engineers
must raise clock rates to squeeze more performance from their designs.
Higher clock rates mean faster slew rates, and shorter setup and hold.
This, coupled with the trend toward 3.3 Volt logic, makes it essential to
understand transient switching behavior on digital busses.
Engineers sometimes take a trial-and-error approach to fixing transmission line problems that come up
in high speed digital circuits. They experiment with serial termination, parallel termination, or both on the
same interconnecting trace.
There is a better way. SPICE tools allow an engineer to perform simple simulations with various
termination and bus topologies. The simulations work equally well at 10 Mhz or 10 Ghz. They don’t need
exotic high frequency fixturing. They can provide the engineer with a “seat-of-the-pants” understanding
of the behavior of a high speed digital bus. More complex (and expensive) signal integrity tools are
available for exotic and critical applications, where the training and purchase costs are justified.
One such SPICE tool is OrCad’s Pspice. The tool supports the functionality of the original SPICE, and
lets you build circuits with a Graphical User Interface, so you don’t have to memorize SPICE syntax. It
also has a built in graphing waveform function. An evaluation version is available from OrCad’s web site
at: http://www.orcad.com
The interface allows an engineer to perform "what if" scenarios, varying circuit parameters to
understand the effect on the circuit's behavior. The ability to vary a parameter can provide an important
qualitative understanding of a circuit's behavior.
A high-speed digital bus can be modeled with the tool by drawing its equivalent circuit, as shown in
Figure 1.
Figure 1
Any one of the digital interconnects on the left can be modeled as the circuit on the right. The
circuit includes the driver voltage and rise time (Vsrc), the source impedance (Rsrc), any series
impedance added by the designer to match the driver’s impedance to the transmission line
(Rseries), the transmission line, and any terminating capacitance/resistance added by the
designer to terminate the line. By varying the values of the components, different experiments can
be performed. Performing the experiments prior to board layout using a tool like SPICE can
reduce project costs and lead times.
@ A Glance
Easy-to-use PC-based SPICE tools, like PSpice,
can provide useful insights into the behavior of
termination
schemes
in
high-speed
digital
interconnects. As signal rise times are reduced to
allow for faster clock speeds, it becomes more
important for engineers to understand these effects.
Figure 2 shows the parameters you will need to
know to model the circuit.
Figure 2
Parameter
Name
Driver Output
Impedance
Driver Rise
Time
Input
Impedance of
Driven
Device
Transmission
Line
Impedance
Transit Time
Source
Value
Manufacturer data
or experiments
Function of driver
strength and
capacitance seen
at driver
Mfg Data or
experiments
24 Ohms
PCB Manufacturer.
Varies with trace
width. Typical
values for 4-layer
board are 70 Ohms
for 5 mil trace, 58
Ohms for 8-mil
trace.
Divide trace length
by speed of wave
in transmission
line, which
depends on the
board’s dielectric
coefficient.
24 Ohms
0.259
nsec
is more realistic, because control signals in digital
circuits are typically active high due to the improved
noise margins.
Several different termination schemes can be
compared by varying the values of Rseries, Cterm
and Rterm. If your SPICE tool does not accept 0 or
infinite as a component value, a suitably large or
small number may be substituted:
Termination
None
Series
Parallel AC
Series + Parallel
Rseries
0
46 Ohms
0
46 Ohms
Cterm
0
0
10 pF
10 pF
Rterm
Infinite
Infinite
70 Ohms
70 Ohms
Once the values are entered, a simulation canbe
performed with a single mouse click. Figure 4 shows
the voltage that would be seen at a device close to
the driver. Series termination is the winner here,
producing the fastest rise-time with the least
overshoot.
Figure 3
Infinite
0.83ns
Once the circuit model is complete, values
must be provided for the components in the
model. These values reflect the physical
characteristics of the PC board, and the
components that are mounted on it. A fast
rise time of 0.259 nsec was used to illustrate
the differences between the termination
schemes.
For simplicity, the case where signal goes from
LOW to HIGH is examined. The HIGH to LOW case
This graph compares the voltages seen by a
device close to the driver for the different
termination schemes. The serially terminated
transmission line shows the fastest setting
characteristics, while the unterminated line
shows the most overshoot. Both lines using
parallel termination require a long setting line for
the series capacitor to charge.
At high speeds, the location of a device on a
transmission line can influence both the timing and
the shape of the transient switching waveform seen
at its inputs.
Figure 4 shows the voltages that
appear at the end of the transmission line. In these
cases, note that the range of the voltages exceeds
those seen in Figure 2.
Figure 4
Figure 5
Devices farther from the driver will see different
signal waveforms. This graph shows the impact
of various termination schemes on the waveform
seen at the end of a transmission line. Note that
the overshoot for the unterminated transmission
line is more severe at the end of the transmission
line.
Modeling Ground Bounce
Driver current can also be measured during the
simulation. Driver current is important because rapid
changes in the current cause ground bounce.
Ground bounce happens when a high frequency
current must be sunk to ground through a finite
inductance, such as a bond wire, or packaging lead.
Ground-bounce is most pronounced on falling
transitions, since the digital circuit must sink current
into the ground to discharge the interconnecting tract
and its loads. On rising edges, the voltage source
sees most of the noise. Ground-bounce is more
serious than power supply bounce because logic
circuits reference ground, so changes in the ground
can change the perceived value of a logic signal.
This can lead high logic levels to be perceived as low
logic, which can cause spurious clocking and other
problems.
Figure 4 shows the driver current for the various
termination schemes – a positive value in the graph
represents a current that would flow into the ground
plane. Note that the currents shown are for one
driver only – consider the effects of driving 8 or 32
signals simultaneously.
PSpice allows you to display the driver current
required to perform the switching, which can give
you an idea of the impact of the termination
scheme on ground-bounce. Note that while a
serial termination improves switching speed and
reduces ground-bounce, parallel terminations
reduce ground-bounce at the expense of speed.
The unterminated line will alternately dump
current onto the ground, and require positive Vcc
current during switching.
It is the high frequency components of the driver
current that are of the greatest concern, because the
inductive impedance of the ground path increases
linearly with frequency. SPICE includes a Fourier
Analysis feature which can be used to show the
frequency components of the signals listed above.
Figure 6 shows such a graph.
Note that it is not the highest value that is relevant
here, but the weighted product of the magnitude and
the frequency.
Serial termination comes out a clear winner here.
In comparing the parallel termination to the no
termination, the parallel termination shifts the spectra
to a lower frequency, but does not diminish its
magnitude.
It is interesting to note that the addition of parallel
termination to a system with series termination will
result in greater ground bounce. This shows why it’s
important to have an understanding of how
termination schemes work – it’s possible to have too
much of a good thing.
Figure 6
A Fourier Analysis of the switching current can
be a guide in evaluating ground-bounce. Since
all current must reach ground through an
inductive impedance, termination schemes that
produce switching currents with strong high
frequency components can be expected to
exacerbate ground-bounce. In this comparison,
serial termination comes out the clear winner –
the series resistor at the driving source limits the
source’s drive current and reduces groundbounce.
References:
1996 Altera Databook, Altera Corporation. San
Jose, CA, 408-894-7000
Johnson, Howard. High Speed Circuit Design: A
Handbook of Black Magic. Prentice Hall Inc.,
1993. ISBN 0-13-395724-1
Author’s Biography
Ken Boorom works for Hewlett-Packard’s
Laserjet Solutions Group in Boise, ID, where he
is responsible for ASIC and circuit board
qualification. He holds Bachelor’s and Master’s
Degrees from Stanford University.