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Chapter 5 • • • • • • • • Structure and Physical Operation I -V characteristics MOSFET DC circuits MOSFET amplifiers Biasing MOSFETS CMOS Inverter High Frequency MOS model SPICE MOSFET model parameters C. Hutchens Chap 5 ECEN 3313 Handouts 1 MOS Structure Drain and Source are defined by the voltage polarity, NMOS D to S (+ to -) PMOS D to S (- to +). Drain, Source, Body (Well ) regions are defined by masking and Doping (NA p type or ND - n type). Gate is formed by the growing of SiO2 over a silicon region and depositing polysilicon over the gate oxide. Gate oxides are 30 to 500Ao thick. Contact to the B, G, D and S regions is made by Al and most reciently Cu. “FET Transistor action” takes place under the gate or channel oxide. C. Hutchens Chap 5 ECEN 3313 Handouts 2 MOS Transistor Operation-OFF Off or non-conduction - Accumulation Note depletion region. Qp = Cox VGS where both body and source are tied together and to gnd. where Cox = ox 0 /tox and Cgs = W L Cox Now the drain to source circuit is two back to back diodes and on the order of 1012 + ohms. Circuit model: ----o o----- VGS < VTN C. Hutchens Chap 5 ECEN 3313 Handouts Veff = VGS - VTN = V “effective gate voltage” where VTN is the start of channel formation. Qn Cox V is the charge in the channel and on the gate and where Cox = ox 0 /tox and Cgs = W L Cox. Now at low VDS I. e. < 50mV ID = n Qn W/L VDS = n Cox W/L V VDS n = 0.06m2/V-S 3 Triode or Linear Region Qr viewed as a resistor----------VDS/ID = RCH =L/( W n Cox V) = (L /W) Rsheet For small VDS linear voltage controlled resistor. Resistance controlled by L/W ratio. Circuit designer can control L/W and Veff. An Inc. in Veff increases the channel thickness or dec. resistance which allows more current to flow for a fixed VDS. Alternatively ID can be set by L/W and V. C. Hutchens Chap 5 ECEN 3313 Handouts 4 Increasing VDS VDS effects on the channel - Note Veff = VGS - VTN is constant Inc VDS reduces the channel thickness which in turn limits the current. This is refered to as saturation For every value of VGS > VTN there is a cooresponding value of VDSsat = VGS - VTN and an IDsat . Where IDsat = n Cox W/L (VGS - VTN)2/2 C. Hutchens Chap 5 ECEN 3313 Handouts 5 Derivation of iD vs vDS dq(x) = - Cox W dx[vGS - v(x) -VT] where Cox = ox/tox (SPICE TOX) Note: VG is constant everywhere due to poly conductance Rearranging and integrating x= 0 to x=L and v(0) = 0 to v(L) - vDS L i D 0 vDS produces an E-field E(x) = -dv(x)/dx neg. electrons drift dx/dt = n dv(x)/dx dx v DS n CoxW vGS VT v x dv( x ) 0 1 W 2 iD n Cox vGS VT v DS v DS L 2 i = (dq) (driftvel) = {- Cox W dx[vGS - v(x) -VT]} n dv(x)/dx (The negative of the source current.) iD = Cox W dx[vGS - v(x) -VT]} n dv(x)/dx C. Hutchens Chap 5 ECEN 3313 Handouts 6 Transition of iD vs vDS Triode to Sat. Region 1- Linear Depence on VDS. Region 2 from 1 to 3a Quadratic depencence on VDS 1 W iD n Cox vGS VT v DS v DS 2 L 2 At vDSsat iDsat is reached and can be found by substituiting vDS = vGS-VT. 1 W 2 iD n Cox vGS VT 2 L C. Hutchens Chap 5 ECEN 3313 Handouts 7 Process Parameter Constants Electron mobility UO n = 580cm2/Vs gate oxide thickness TOX tox = 0.04m to 0.004m L=2m and 0.1m permittivity ox = 3.907o = 3.5x10-13 F/cm = 3.5x10-17 F/m Sheet Cap Cox = ox/tox = 0.875fFd/m2, 8.75fFd/m2 tox = 0.04m and 0.004m Capacitance per unit W Process Transconductance KP C. Hutchens Chap 5 ECEN 3313 Handouts Cox L = 1.65fd/m or 0.875fFd/m Often for purposes of estimation we can use 1fFd/m kn’ = n Cox = 50A/V2 for NMOS and 18A/V2 for PMOS 8 SPICE MODEL parameters *N38L SPICE LEVEL 2 PARAMETERS (2 micron orbit n-well) .MODEL nfet NMOS LEVEL=2 PHI=0.600000 TOX=4.1900E-08 XJ=0.200000U TPG=1 + VTO=0.8123 DELTA=5.5710E+00 LD=3.0410E-07 KP=4.6869E-05 + UO=568.7 UEXP=1.4610E-01 UCRIT=8.6360E+04 RSH=2.1170E+01 + GAMMA=0.4675 NSUB=4.4720E+15 NFS=1.9800E+11 VMAX=5.9890E+04 + LAMBDA=3.3370E-02 CGDO=3.7593E-10 CGSO=3.7593E-10 + CGBO=3.9487E-10 CJ=9.2516E-05 MJ=0.7551 CJSW=4.8928E-10 + MJSW=0.336658 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is -3.0840E-07 .MODEL pfet PMOS LEVEL=2 PHI=0.600000 TOX=4.1900E-08 XJ=0.200000U TPG=-1 + VTO=-0.9901 DELTA=5.2390E+00 LD=3.8900E-07 KP=1.6549E-05 + UO=200.8 UEXP=2.9100E-01 UCRIT=8.4920E+04 RSH=4.8190E+01 + GAMMA=0.6810 NSUB=9.4900E+15 NFS=3.270E+11 VMAX=9.9990E+05 + LAMBDA=4.5130E-02 CGDO=4.8089E-10 CGSO=4.8089E-10 + CGBO=3.7299E-10 CJ=3.2306E-04 MJ=0.5717 CJSW=3.0368E-10 + MJSW=0.259043 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is -1.7220E-07 C. Hutchens Chap 5 ECEN 3313 Handouts 9 MOSFET SPICE parameters ********** .MODEL NMOS1_2 NMOS LEVEL=2 LD=0.181362U TOX=402.000000E-10 + NSUB=6.567000E+15 VTO=0.805287 KP=4.757000E-05 GAMMA=0.5435 + PHI=0.6 UO=553.83 UEXP=0.151038 UCRIT=48309.6 + DELTA=0.823727 VMAX=50459.8 XJ=0.250000U LAMBDA=3.437039E-02 + NFS=4.094390E+12 NEFF=1 NSS=1.000000E+12 TPG=1.000000 + RSH=19.340000 CGDO=2.336825E-10 CGSO=2.336825E-10 CGBO=7.582249E-10 + CJ=1.011600E-04 MJ=0.633000 CJSW=5.320000E-10 MJSW=0.266000 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is 0.40 um *********** .MODEL PMOS1_2 PMOS LEVEL=2 LD=0.250000U TOX=402.000000E-10 + NSUB=6.786000E+15 VTO=-0.758994 KP=1.843000E-05 GAMMA=0.5525 + PHI=0.6 UO=214.5 UEXP=0.253978 UCRIT=40136.1 + DELTA=0.135535 VMAX=78961.6 XJ=0.050000U LAMBDA=4.876526E-02 + NFS=4.352678E+11 NEFF=1.001 NSS=1.000000E+12 TPG=-1.000000 + RSH=107.700000 CGDO=3.221216E-10 CGSO=3.221216E-10 CGBO=6.309201E-10 + CJ=2.474000E-04 MJ=0.548900 CJSW=3.155000E-10 MJSW=0.327000 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is -0.12 um C. Hutchens Chap 5 ECEN 3313 Handouts 10 MOSFET parameters Ex -graphical Use the Large signal model equations to find a) the value of rDS for small values of vDS if vGS = 5V, VTO = 1V and b) the value of ID if vDS = 5V and vGS = 3V. Assume that kn’ = n Cox = 50A/V2 and W/L = 100m/10m. C. Hutchens Chap 5 ECEN 3313 Handouts 11 PMOS Enhancement C. Hutchens Chap 5 ECEN 3313 Handouts 12 SPICE MOSFET parameters VT0 U0 TOX LD GAMMA NSUB PHI PB CJ CJSW LAMBDA RX MJ MJSW CGD0 VTX X tox LD NX |2F| 0 Cj0 Cj-sw0 1/ RE mj mj-sw sidewall Cgd/W C. Hutchens Chap 5 ECEN 3313 Handouts threshold where X = N or P mobility where X = n or p gate oxide thickness gate drain (source) overlap body threshold modulation paramater substate doping X = A or D for N or P MOS surface strong inversion potential built in contact potential junction to bulk zero bias bottom cap. for D-Bdy and S- Bdy zero bias side wall cap. for D-Bdy and S- Bdy recipocal forward early voltage 1/= VA Series S and D contact resistance X = S o D Grading coiefficent exponent junction bot. Grading coiefficent exponent junction per unit width G-D and G-S overlap cap. 13 Complimentry CMOS & Symbols 1 W 2 iDn kn vGS VT 1 N v DS 2 L 1 W 2 iDp k p vGS VT 1 P v DS 2 L C. Hutchens Chap 5 ECEN 3313 Handouts 14 Large Signal Equivalent Ckt Regions of Operation Triode or Linear or ohmic - vDS < vGS - VT = V iD n Cox 1 W vGS VT v DS 2 L Saturation vDS > vGS - VT = V 1 W 2 iD n Cox vGS VT 1 v DS 2 L Off vGS < VTN Note change of > sign for PMOS i.e. Off vGS > VTP C. Hutchens Chap 5 ECEN 3313 Handouts 15 Modeling rout Effective Output Resistance 1/ = VA is refered to as the early voltage in Bipolar ckts and “LAMBDA” the parameter that accounts for the “tilt” of the output charcteristics. VA L If is very very important when attempting to match transistors that L be equal for all transistors which are being matched. 1 1 i W 1 V ru D N kn' A V 2 2L N iD iD vGS vGS cons tan t C. Hutchens Chap 5 ECEN 3313 Handouts 16 vSB effect on VT VSB modulates (depletes) the body increasing the required gate voltage to develop a channel. Typically all or most transistors share the same body. To avoid the possibility of forward biasing one or more D/S to bdy diodes the body of NMOS (PMOS) device are tied to VSS (VDD). C. Hutchens Chap 5 ECEN 3313 Handouts VT VT 0 2 f vSB 2 f where 2qN X Si Cox and VT 0 VT v SB 0 X = A for NMOS and D for PMOS 17 Misc. Effects Temperature VT decreases 2mV/Co rise k’ decreases faster with the result beening less I and slower speed. Breakdown- (gate oxide and D-B diode avalanching), punch through (Source-Drain depletion). Assume “LAMBDA” and ”GAMMA” effects can be ignored. Discuss the errors associated with ignoring and . 1 W 2 iD nCox vGS VT 1 vDS 2 L C. Hutchens Chap 5 ECEN 3313 Handouts RS = (VS - VSS)/id RD = (VDD - VD)/id 18 Current Mirror EX Given the following transistor data kn = 50uA/V2, kp = 20uA/V2 , VTN = 1V, VTP = 1V, N = 2P = 0.02 V-1 and VDD and VSS are 5 and -5V respectively. For circuit 1 if both transistors have a W/L of 10 and RD = 50K find the required RB to set ID 250uA ignoring . What is the value of VDS? What is the effect of ignoring ? For circuit 2 if V of the NMOS device (W/L = 100um/5um) is to be 1V (VGS = 1 + VT = 2V) and the PMOS mirrors are to have an identical V of 1 V. a) Find the value of RB, b) the geometries of the PMOS devices, and c) estimate the VDS of the NMOS transistor. How many different PMOS mirror geometry arrangements will satisfy the circuit requirement? C. Hutchens Chap 5 ECEN 3313 Handouts 19 MOSFET DC BIAS Given the following transistor data kn = 50uA/V2,, VTN = 1V, N = 0.01 V-1 and VDD and VSS are 10 and 0 volts respectively. MOSFET BIAS Gate Eq. VGG = VGS + ID RS Drain Eq. VDD = IDRD + VDSQ + IDRS QPT is VDSQ, ID “Designer selects the desired QPT” Now selecting VDSQ = 4V, ID =1mA VGG = VGS + ID RS = 3 V + 1mA 2K = 5V RD = (VDD - VDSQ - IDRS )/ ID = (10V - 4V)/1mA - 2K = 4 K C. Hutchens Chap 5 ECEN 3313 Handouts 20 Shifting the Qpt for Gain A iDn kn 1 W 2 vGS VT 1 v DS 2 L go = gds = ID/vDS for constant vGS C. Hutchens Chap 5 ECEN 3313 Handouts 21 Distorting the Signal C. Hutchens Chap 5 ECEN 3313 Handouts 22 Shifting the Qpt con’t iDn kn 1 W 2 vGS VT 1 v DS 2 L Forward transconductance is a critical concept. gm = ID/vGS for constant vDS C. Hutchens Chap 5 ECEN 3313 Handouts 23 MOSFET DC BIAS MOSFET BIAS (Con’t) VGG = R1/(R1 + R2) and RG = rin = R1||R2 rin at the gate For input signals/nodes rin should be >> Rgen For output signals/nodes ro should be >> RLoad when possible EX rin = R1||R2 >> Rgen i.e. 50 ohms r0 RD >> RL 100K ohms gate input drain output Note it can be shown that for max. Vpp swing at VDS ID = VDD /(Rac + RDC) ; VDSQ = Rac IDQ where Rac RD||RL , RDC = RD + RS and for RL = ID = VDD /(2RD + RS) ; VDSQ = RD IDQ C. Hutchens Chap 5 ECEN 3313 Handouts 24 MOSFET DC BIAS-CS,CD,CG C. Hutchens Chap 5 ECEN 3313 Handouts 25 Bias Stabilization C. Hutchens Chap 5 ECEN 3313 Handouts 26 MOSFET Small Signal Equivalent Ckt C. Hutchens Chap 5 ECEN 3313 Handouts 27 CS small signal eqivalent Ckt Given the following transistor data kn = 50uA/V2,, VTN = 1V, N = 0.01 V-1 and VDD and VSS are 10 and 0 respectively. Observations for CS for all Capacitors are Large or neglectable rin R1||R2 = RG Cap CS ro of circuit - ac impedance at the drain (output for CS ) exclusive of RL remove RL apply an ac test current at vo with vin open ckt. vo (GD + gds) + gm vgs + iin = 0 r0 = RD||rds RD Av small signal voltage gain vo (GD + gds) + gm vgs = 0; vgs = vin Solving for vo/ vin = Av = -gm (RD||rds||RL) -gmRD C. Hutchens Chap 5 ECEN 3313 Handouts 28 CS small signal eqivalent Ckt Given the following transistor data k n = 50uA/V2,, VTN = 1V, N = 0.01 V-1 and VDD and VSS are 10 and 0 respectively. W/L = 200um/5um EX If the CS circuit above has an RD = 10K ohm, RS = 4K ohm, RL = 400k ohm, and VGG = 2.5V determine AV. From VGG = VGS + ID RS = (2ID/)1/2 + VT + ID RS = 2.5V ID = 250uA From VDSQ = VDD - ID (RS + RD) = 10 - 14k 0.25mA = 6.5V Transistor is in the Sat region and will be amplifing. gm = (2ID )1/2 =(2( 0.25mA )(40) 50/V2)1/2 = 1mS gds = 1/ rds = ID = 0.01/V .25mA = 2.5uS or 400K AV = - gm (RD || RL ||rds) -1mS 10K = -10. What is the max input allowed before major distortion and what is Vpp? C. Hutchens Chap 5 ECEN 3313 Handouts 29 CS small signal eqivalent Ckt Given the following transistor data k n = 50uA/V2,, VTN = 1V, N = 0.01 V-1 and VDD and VSS are 10 and 0 respectively. W/L = 200um/5um EX If the CS circuit above has an RD = 10K ohm, RS = 4K ohm, RL = 400k ohm, and VGG = 2.5V determine AV. From VGG = VGS + ID RS = (2ID/)1/2 + VT + ID RS = 2.5V ID = 250uA From VDSQ = VDD - ID (RS + RD) = 10 - 14k 0.25mA = 6.5V Transistor is in the Sat region and will be amplifing. gm = (2ID )1/2 =(2( 0.25mA )(40) 50/V2)1/2 = 1mS gds = 1/ rds = ID = 0.01/V .25mA = 2.5uS or 400K AV = - gm (RD || RL ||rds) -1mS 10K = -10. What is the max input allowed before major distortion and what is Vpp? C. Hutchens Chap 5 ECEN 3313 Handouts 30 Modeling the Body effect Body Effect VT VT 0 2 f vSB 2 f gm = (VGS - VT) Observations gm dec. with inc. VT VT inc. with inc vSB EX For an NMOS transistor with 2f 0.6 , = 0.5V1/2, and VSB = 4 find . Designs and analysis must consider this as approiate. Digital Logic i.e. NOR gate Analog distortion gmbc = gm gmb C. Hutchens Chap 5 ECEN 3313 Handouts iD vsb v GS v DS VT VSB 2 2 f VSB 31 Biasing in Integrated MOS Amps Basic Current mirroring/steering or routing 1 W 2 iDp k p vGS VT 1 N v DS 2 L 1 W 2 iDn kn vGS VT 1 P v DS 2 L ID1 = IREF = (VDD- VGS)/R 1 W 2 v GS VT 1 v DS ; 2 L 1 W 2 i2 k n v GS VT 1 v DS 2 L iD1 k n iO I REF 1 W 2 W v GS VT 1 v DS 2 L 2 1 v DS 2 W2 2 L 2 1 W 2 W 1 v GS 1 W1 k n v GS VT 1 v GS 1 L 1 2 L 1 kn Note in IC designs L1 = L2 “always” C. Hutchens Chap 5 ECEN 3313 Handouts 32 Current Steering I2 = I1 W 2/W 1 ; I3 = I4 = I1 W 3/W 1; I5 = I4 W 5/W 4; I5 =I1 {W 3/W 1}{ W 5/W 4}; VGS4 = VGS5 = (2 ID/ ) - |VTP| Note All VDS > VGS - |VT| = V Error Sources - matching of geometry, voltages and Vts. iO I REF W L 2 1 v DS 2 W2 W 1 v DS 2 1 v GS 1 2 ( v DS 2 v GS 1 W1 W 1 v GS 1 W1 L 1 C. Hutchens Chap 5 ECEN 3313 Handouts 33 IC Biasing of the Basic MOS amps C. Hutchens Chap 5 ECEN 3313 Handouts 34 Common Source amp in ICs To remain a “linear” amp stage M1 and M2 must remain in stauration. Then AVDC = gm2 /(gds1 + gds2) where gds1 = P ID = ID/VAP; gds2 = N ID = ID/VAN gm = { 2kn’(W/L) ID} = 2 V AVDC = ( 2 V)/( P ID+ N ID) Noting that ID = ( 2 V) V/2 AVDC = 2/{ V( P + N)} AV depends on V, but ID on V Exercise: What is the effect of CL on AV? C. Hutchens Chap 5 ECEN 3313 Handouts 35 Common Gate in ICs A CMOS CG amp is fabed in 0.8um technology has W/L = 100um/1.6um geometries for all transistors, kn’ = 90uA/V2, kp’ = 30uA/V2, ID = IREF = 100uA, VAN = 14, VAP = 20, and = .15. Find ro, rin, and Av. C. Hutchens Chap 5 ECEN 3313 Handouts 36 Common Drain in ICs Voltage Follower vo = gm1 (rds1||rds2||1/gmbvs)vgs1 = gm1 RSvgs1 vin = vgs1 + vo = vgs1(1 + RS) AV = gm1 RSvgs1/{ vgs1(1 + RS)} AV gm1/(gm1 + gmbs1) = 1/(1+) To operate in the amplifier region- both transistors saturated vo vI > V2 and vI < VDD - VTN1. EX if V2 =V1 = 250mV, W/L = 100um/1.6um geometries for all transistors, kn’ = 90uA/V2, ID = IREF = 100uA, VAN = 14, VAP = 20, and = .15. Find Vopp if VDD -VSS = 3.3V, AV, and go. C. Hutchens Chap 5 ECEN 3313 Handouts 37 INVERTER POWER 0 to 1 charge CL to VDD 1/2 CLVDD2 Stored 1 to 0 charge CL to discharged Total energy dissapated per cycle - CLVDD2 Three sources of power dissapation 1. Offstate leakage currents(subthreshold ) 2. Shunt currents (During transiotion both Device are on). 3. CLVDD2 CMOS Power Diss Cleff VDD2 C. Hutchens Chap 5 ECEN 3313 Handouts 38 Inverter Q pts. C. Hutchens Chap 5 ECEN 3313 Handouts 39 CMOS INVERTER Reg A B C* D E VIN <VTN VIL Vtrip VIH > VDD- VTP VO NMOS PMOS VOH “ 1” Vtrip “ 0” VOH cutoff Sat. Sat. lin. lin. lin. lin. Sat. Sat. cutoff * Note at C, VIN = VO = Vtrip. This will equal (VDD- VSS )/2 if NMOS and PMOS are “Beta” matched and VTN + VTP = 0. In addition NMH will equal NML. Solving for VIL in Region B IDN (sat) = IDP (tri) dVO/dVI = -1 Solving for Vtrip in Region C IDN (sat) = IDP (sat) VO = V I Solving for VIH in Region D IDN (tri) = IDP (sat) dVO/dVI = -1 C. Hutchens Chap 5 ECEN 3313 Handouts 40 CMOS INVERTER Solving for VIL in Region B - IDN (sat) = IDP (tri) VIL = {2 V0 + VTP - VDD + kR VTN}/(1 + kR) where kR = n (W/L)n /p (W/L)p Note typically Ln = Lp = Lmin then kR = (n W n )/(p (W p) Solving for VIH in Region D - IDN (tri) = IDP (sat) VIH = { VDD + VTP +kR (2 V0 + VTN}/(1 + kR) where kR = (n W n )/(p (W p) Solving for Vth in Region C - IDN (sat) = IDP (sat) Vth = VTN + 1/( kR){ VDD + VTP}/(1 +( 1/kR) C. Hutchens Chap 5 ECEN 3313 Handouts 41 The Digital CMOS inverter Roneff (VDD-VSS)/{ID(VGS=VDD) - ID(VGS=VSS)} = VDD/ID R oneff VDD 1 L 2 1 W 1 W 2 W k nVDD k n v DD VT k n VDD 2 L 2 L R oneff L Ronsheet W Note |VT| VDD/5 t fall = 2.2R oneff C for a 10 to 90 per cent signal (0.1 VDD to 0.9VDD) t fall = 2.2R oneff C 2.2 L 4.4C Ronsheet C W (W / L )k nVDD Note simplier than text but 2.5X larger time. Therefore somewhat conservative. C. Hutchens Chap 5 ECEN 3313 Handouts EX If W/L = 1.6um/0.8um, kn = 100uA/V2 and VDD =VDD-VTN = 2.5V and C = 20fFd find tfall = tHL for a CMOS inverter. If it is clocked at 100MHz estimate the power dissipation. 42 The Digital CMOS inverter EX If W/L = 1.6um/0.8um, kn = 100uA/V2 and VDD =VDD-VTN = 2.5V and C = 20fFd find tfall = tHL for a CMOS inverter. If it is clocked at 100MHz estimate the power dissipation. C. Hutchens Chap 5 ECEN 3313 Handouts 43 The CMOS switch VIN Positive PMOS: V = VSS + VT, VDS Sat to Triode “Just like inverter rise” NMOS: V = VDD - VT to 0, VDS Sat, Source can not rise above VTN VIN Negative NMOS: V = VDD - VT, VDS Sat to Triode “Just like inverter fall” PMOS: V = VDD - VT to 0, VDS Sat Source can not drop below |VTP| C. Hutchens Chap 5 ECEN 3313 Handouts 44 High Frequency MOSFET model Sat Region “Most Analog amplifiers” Cgd = W LD Cox = W CGDO << Cgs Cox = ox/TOX Assume =0 Yes 0! Cgs = 2/3 W L Cox Triode Region “Most Digital Logic and T-gate switches” Cgs = Cgd = 1/2 W L Cox Junction or Depletion Caps. “est.” Cdb = Csb ={ Area Drain (Source)} CJ0/2 + {Perimeter Drain (Source) } CJSW C. Hutchens Chap 5 ECEN 3313 Handouts 45 MOSFET fT fT is defined as the unity current gain bandwidth. Specifically the frequency at which the input current magnitude is equal the output current bandwidth. Find the unity bandwith for an NMOS transistor biased under ideal conditions and it compare to its’ unity voltage gain bandwidth if it is loaded with an identical NMOS transistor. Assume both are in saturation. Finally find the fall time of an inverter loaded by an identical inverter and compare the results symbolically. How close are the results? C. Hutchens Chap 5 ECEN 3313 Handouts 46 MOSFET fT id = gm vgs + (0- vgs) sCgd (1) (vgs - vin )Rg + vgs (s Cgs + sCgd ) = 0 (2) Or iin = vgs (sCgs +sCgd ) Note Rg has no effect. (3) Ai = Id/Ig = { gm vgs + (0- vgs) sCgd }/{ vgs (sCgs +sCgd )} Ai = {gm – sCgd }/ { (sCgs +sCgd )} Ai (s) = [gm]{1 – sCgd/ gm }/ { (sCgs +sCgd )} THIS IS VERY IMPORTANT the LINK BETWEEN ANALYSIS- THE SIMULATOR and OUR MODEL. SPICE MODELS ARE 98% REALITY AND TRANSFERABLE. We now have a pole at the origin and a a zero Infinite current gain at “DC” zero @ gm/( Cgs +Cgd) In SPICE gm = KP (W/L)Veff , Cgs = 2/3WLCox , C = WCgdo C. Hutchens Chap 5 ECEN 3313 Handouts 47 Small Signal Model Cuttoff f 0 dB This slide presents a very key concept. In practice in broad band amplifier design one CANNOT expect to apply a transistor beyond T…. .MODEL nfet NMOS LEVEL=2 PHI=0.600000 TOX=4.1900E-08 XJ=0.200000U TPG=1 + VTO=0.8123 DELTA=5.5710E+00 LD=3.0410E-07 KP=4.6869E-05 + UO=568.7 UEXP=1.4610E-01 UCRIT=8.6360E+04 RSH=2.1170E+01 + GAMMA=0.4675 NSUB=4.4720E+15 NFS=1.9800E+11 VMAX=5.9890E+04 + LAMBDA=3.3370E-02 CGDO=3.7593E-10 CGSO=3.7593E-10 + CGBO=3.9487E-10 CJ=9.2516E-05 MJ=0.7551 CJSW=4.8928E-10 + MJSW=0.336658 PB=0.800000 C. Hutchens Chap 5 ECEN 3313 Handouts 48 The Junction FET C. Hutchens Chap 5 ECEN 3313 Handouts 49 JFET I-V Characteristics Cuttoff vGS VP iD 0 Triode VP vGS 0, vDS vGS -VP v v v 2 iD I DSS 21 GS DS DS VP VP VP Saturation v 2 iD I DSS 1 GS 1 v DS VP C. Hutchens Chap 5 ECEN 3313 Handouts 50 SPICE para Review Know SPICE parameters VT0 U0 TOX KP LAMBDA GAMMA CJ CJSW AD, AS PD, PS Others W,L si ox gm gds = go C. Hutchens Chap 5 ECEN 3313 Handouts small signal model cs cg cd How to find the gain, ro, and rin from SPICE data and Qpt. CJ0 AD,AS CJSW PD, PS Others Basic Digital Inverter Analog/t-gate switch I-V properties JFET MOSFET 51