Download Local disorder effects on electron transport in silicon nanostructures

Hitachi-Cambridge collaboration on nanoelectronics and
recent progress of Coulomb blockade devices
Hiroshi Mizuta
Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Madingley Road, Cambridge, CB3 0HE, UK
Hitachi Cambridge Laboratory (HCL) was established in 1989 as an “embedded laboratory” in the
Microelectronics Research Centre (MRC), University of Cambridge. In close collaboration with more than
20 university members, HCL is a truly international team of researchers from three continents, and its
openness for research has resulted in this profitable collaboration lasting over a decade. HCL has been
aiming at creating new concepts of advanced electronic and optoelectronic devices and has produced
scientific breakthroughs such as single-electron memory and logic [1][2], coherent optical-switching [3] and
PLEDM (Phase-state Low Electron-number Drive Memory) [4][5]. This paper first describes the HCL-MRC
collaborative research highlights briefly and then presents recent progress of our research into silicon-based
Coulomb Blockade (CB) devices.
In our CB memory and logic devices heavily-doped crystalline silicon (c-Si) and polycrystalline silicon
(poly-Si) nanowire (NW) structures have been used as a key building block. In these NW structures local
disorder plays a significant role to produce nanometre-scale electron islands naturally. In the c-Si NW
structures, electrostatic potential disorder caused by randomly distributed ionized donors is responsible for
natural formation of electron islands. By using a numerical simulation that deals with random dopants
explicitly, we first show how geometrically uniform silicon NWs can break up into a series of nanoscale
electron islands that exhibit CB [6]. The offset charge effects on the distribution of threshold voltage of the
NW devices are also discussed by presenting a statistical analysis performed using a Monte Carlo transport
simulation combined with these random dopant potential calculations. We then demonstrate a high-speed CB
memory with the c-Si NW [7][8] that operates at a temperature up to about 60K. On the other hand, in the
poly-Si NW structures, individual silicon grains and grain boundaries (GBs) formed in the thin poly-Si film
act as an electron island and a tunnel junction, respectively. However, the properties of the GBs as a tunnel
barrier have not been made clear, and there is no guideline to optimise the GBs in terms of high temperature
CB operation. To clarify these we adopt poly-Si point contact transistors (PC-Trs) where both length and
width of the poly-Si NW channel are as short as the grain size [9]. The PC-Trs contain either zero or only
few GBs at most in the channel and enable to study electron transport via few GBs. By comparing the
experimental results for PC-Trs fabricated with various process conditions, a possibility of optimizing the
tunnelling properties of GBs is investigated to achieve room-temperature CB device operation.
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[5] H. Mizuta, M. Wagner and K. Nakazato, IEEE Trans. Electron Devices, 48, 1103, 2001.
[6] G. Evans, H. Mizuta and H. Ahmed, Jpn. J. Appl. Phys. 40, 5837, 2001
[7] H.-O. Müller and H. Mizuta, IEEE Trans. Electron Devices, 47, 1826, 2000.
[8] Z. Durrani, A. Irvine and H. Ahmed, IEEE Trans. Electron Devices, 47, 2334, 2000.
[9] Y. Furuta, H. Mizuta, K. Nakazato, Y. T. Tan, T. Kamiya, Z. A. K. Durrani, H. Ahmed and K. Taniguchi, Jpn. J. Appl.
Phys, 40, L615-L617, 2001.