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Transcript
Laboratory Exercise 8 – Basic Digital (Logic Gates)
This experiment introduces the use of digital logic in electronics. Logic circuits are useful in
control and automation applications in instruments and are the building blocks (a step up from
transistors) of computers. This topic is reminiscent of the relationship between transistors and op
amps; we (or more properly, electronic engineers) used a bunch of transistors to make an op amp
that did a much better job than the individual transistors. Those same EEs put together billions of
the logic devices (called gates) to get a computer. We’ll introduce two new topics in this
Exercise – the integrated circuit chips that do the logical operations and a way of thinking about
the operations themselves. I’m hoping that the logic concepts aren’t completely new to you.
The gates: There are many digital integrated devices available that are based on transistortransistor logic (TTL), including the low power Shottky (LS) devices that we use most often in
this lab. These chips operate from a single 5 V supply (plus ground). Only two input/output
voltage levels are allowed: logic “0” must be a signal between 0 and 0.8 V and logic “1” must be
a signal between 2.2 and 5 V. The state of the output is not defined if an input is between 0.8 and
2.2 V (a.k.a. no-man’s land). The output state of a device for all possible (allowable) input
voltage combinations is characterized by a truth table.
In this class (and in computers) all mathematical operations are conducted in binary, but
decoding can provide outputs in octal, hexadecimal, binary coded decimal (BCD), or decimal
number bases. In fact, we will find that the 1’s and 0’s are very versatile and can be used to
encode a large number of different things, depending on the application.
In some cases we will use the CMOS variants of these devices, but this won’t be difficult
because they are usually interchangeable for their LS TTL cousins (same pinout). These chips
can be identified by the “C” that will be buried somewhere in their name (74HC00), the 74 prefix
means that they conform to the standard setup, the HC means it is a CMOS type, and the 00
means it is a NAND gate. More on all of these distinctions during the lecture… Another
difference you will see with the CMOS devices is that their outputs are much nearer to 5 V and 0
V. This allows their “no-man’s land” to be a bit more symmetrical and larger, making them more
immune to noise than TTL devices. They also demand much less current at their inputs.
Logic Primer: There are four basic logic operations that we will make use of in this class. (Three
are truly unique and one is a special case of another.) They are NOT (or inverse), AND, OR, and
XOR (exclusive OR). All but XOR are probably familiar to you in a general sense. For instance
when we search for a journal article and want to add more terms, we use OR to indicate that
either NMR or Protein would be a good keyword. Conversely if we want to narrow a big search
we ask for papers that have both NMR and Protein, expecting that this will eliminate some of the
“bad hits” for each of the terms alone. XOR means either keyword 1 or keyword 2 would be ok,
but for some reason we don’t want papers with both terms.
We will use various symbols to represent the operations (and the gates), but some of the more
common types are:
NOT is indicated by a bar over a logical variable or a star superscript next to one; e.g., A* means
the inverse of A. (We saw the bar notation in the last lab with the Q and Q bar outputs of the
74123.) The schematic symbol for the gate is an arrow (like an amp) with a circle (or “bubble”)
at the output. Any other input or output on the other types of gates can be NOTed (a.k.a., negated
or inverted) by putting a bubble on the connection. A NOT gate with a hysteresis loop symbol
indicates that the input is a Schmitt trigger, making it a special type of “decisive” gate.
AND is indicated by the multiplication sign between two logical variables (A * B means A AND
B or A ∩ B, if you remember the math version). As with normal multiplication, if two variables
are grouped (like AB or (AB)) we interpret this to mean that they are ANDed. The schematic
symbol for the gate is a rounded arrow (see below) that looks a bit like an op amp. Note that
more than two variables can be ANDed, so an AND gate can have more than two inputs. This is
not to be confused with tri-state devices which we will talk about next lab. They have obviously
different symbols. There can only be one output from any logic device, with the slight exception
of the tri-state devices.
OR is indicated by the addition symbol (A + B means A OR B or A U B, using the math
symbols). The schematic symbol for the gate is a “pointy” rounded arrow as shown below.
Again, more than one input can be ORed together.
XOR is indicated by a plus sign in a circle (A  B is A XOR B). The schematic symbol for the
gate looks like an OR but has an extra line on the input side.
Again, regardless of how many inputs a logical function or operation has, it has only one output
(the “answer”). The basic gates work the same way, but some of the more complicated logic
devices will provide both the regular and complementary outputs, like the 74123 did.
Fortunately it turns out that all of the gates given above can be constructed from multiple copies
of a particular type of gate (you only need one type to make the others) either NAND (NOT
AND) or NOR. This requires a bit of thought and/or knowledge of logic and lots of gates, so
when chemists build these circuits, we usually just buy the gates we need to make the simplest
solution we can imagine. The chips are cheap, but your time isn’t.
Doing logic circuit analysis requires that you can read truth tables. We’ll take a couple of simple
gates and see how truth tables can represent the logic operations in a compact, easy to read form.
NAND Gate
The 7400 IC chip (74LS00 or 74HC00) contains four NAND gates with the pin-out shown
below. Each gate has two inputs labeled A and B and one output Y. The numbers correspond to
the four gates, and there are inputs for power (Vcc = 5 V) and ground. There is another way of
representing this chip in schematics that is drawn on the board. The other type emphasizes the
operation of the gates and both types of diagrams are commonly used.
Circuit Exercise 1 - Insert the 7400 IC into the breadboard so the pins are on either side of the
center channel, as usual for the DIP package. All four gates operate from the same power supply
pins: 5 V at pin 14 and ground at pin 7.
Real-world application note: When you are working with logic circuits, it is important that you
have both inputs connected (especially if you want a meaningful output). Don’t assume an input
will be “0” if you don’t connect it to ground. This is true regardless of whether the chip is of
CMOS or TTL construction, but CMOS gates (because of their very high input impedance) are
particularly susceptible to “uncertainty” in output when their inputs are unconnected. This
uncertainty can cause noticeable power drain by CMOS devices that aren’t even being used. (One
of the big virtues of CMOS gates is that they usually don’t draw much power.) If you are using
CMOS gates, the safest thing to do is to tie all unused inputs either “high” or “low”. This isn’t
really a problem with the LS TTL gates that will “float” to their low energy consumption HIGH
state if their inputs are unconnected. We won’t worry about that in this class.
Circuit Exercise 1 (continued) - Connect the two inputs of one gate to two of the 0/5 V SPDT
switches and connect the DMM (20 V range) to the output of the NAND gate, and then turn on
the trainer. (These are pretty rugged chips, but making connections while the power is on is never
a good idea.)
Fill in the observed states of the output (0 or 1, not the actual voltages) as the two inputs are
varied according to the following truth table.
NAND Truth Table
A
B
0
1
0
1
Output
0
0
1
1
Now make an inverted input and output version of an AND gate – (A*B*)* = NOT {(NOT A)
AND (NOT B)}. You’ve already got an inverted output AND; you just need to invert the inputs.
One slick way to make an inverter (NOT) is to put the same signal into both inputs of a NAND
(i.e., each SPDT switch gets connected to both inputs of a NAND and the outputs of these two
gates are connected to a third NAND’s inputs). Check your truth table to see how the inverter
(NAND version of NOT) works.
Construct the truth table for the inverted input and output AND.
Negated input NAND Truth Table
A
B
Output
0
0
1
0
0
1
1
1
Stare at this truth table for a second and see if you recognize it. What else do we call this thing?
(This is an illustration of the fact that you can build all of the gate types from multiple NANDs.)
How can you make an AND from two NANDs?
So far, we’ve only used manually controlled static signals as inputs to the gates. Now we’ll look
at the use of repetitive signals with the logic ICs. Later on, we’ll see why this is a powerful
combination.
Using the scope, adjust the TTL clock generator (the red post at top left on the trainer) for ~1
kHz. Connect this square wave to input A of a NAND gate. Connect input B of that gate to one
of the SPDT switches and then connect the output of that gate to both inputs of another NAND
gate, inverting the first output to make an AND. Observe the input square wave and the output
waveforms from the second gate for each state of input B. Leave this circuit set up for the next
exercise.
Record your observations below.
Explain why logic devices are called gates. (In the real world, what are gates used for?)
Don’t try this at home! (This is something you wouldn’t usually do with digital devices.) Use the
function generator (or a summing amplifier) to produce a triangle wave from approximately 0 to
2 V, by turning the offset control all the way up and the amplitude down. Connect this triangle
wave to input A of the first NAND, replacing the TTL clock.
Describe the input and output waveforms, with input B at 5 and 0 V.
Look at the output of the first NAND and describe its behavior with respect to the input for both
switch states.
Over what input voltage range does the output change states?
What happens when the input goes negative? This isn’t supposed to happen in digital electronics,
so the results are unpredictable and may include irreparable damage to the gate.
Gates (recap): Using the other type of simple gates (AND, OR, etc.) in digital electronic circuits
is similar to using NANDs. The process is to lay out the logic that you need in the experiment,
then think about how that translates into devices that are driven by real world inputs. And finally,
you build and test the circuit to see if it behaves correctly.
Concept Question 1 – Imagine that you would like to make your laser lab a little safer (both for
the laser and the people around it). You want the switch that turns on the laser to work only if
cooling water is flowing through the laser AND the red blinking light out in the hall has been
switched on. Circuits of this type are referred to as “interlocks” and are a rudimentary type of
control application. Assume that the following sensors are installed: 1) The cooling water line
has a little mechanical flapper switch that closes when the water flow is sufficient to hold it
down. This switch has zero resistance when closed (flow), infinite when open (no flow). 2) The
electrician that installed the red light in the hall put a relay in series with the AC voltage for the
light that produces a +5 V signal when the light is on and 0 V when it is off.
Describe (in words) or diagram the schematic and/or logic diagram (including truth table) for the
system and discuss any conditioning that you have to apply to the sensor’s “signals” to make
them compatible with the logic circuit.
(Do this if there is time). Set up a mockup of this system using switches, and fill in the truth
table. Does your circuit have any unexpected “bad operating modes”?
Toward Counting: Simple Latch
Logic gates only operate on what is at their inputs at that instant in time. They recognize changes
in the state of the inputs but can’t “remember” once the input changes back, and thus they make
terrible counters. If you wanted to look for a change, you’d have to keep asking them, “has
anything changed yet?” and if you happened to be looking away when something interesting did
happen, you’d miss it. We need to have logic devices that operate on digital inputs, but can
remember changes too. These types of logic devices are known as latches (they’ll change and
stick) or flip-flops (they can be made to toggle from one output state to another). If you use a
latch, you just have to check every once in a while to see if the inputs have changed (often
enough that you can reset the latch before the next event happens).
Circuit Exercise 2 - Connect two NAND gates together as shown below to form a simple
memory device (latch). Don’t forget power and ground. (I won’t say that anymore, I promise.)
You can use the built-in LEDs on your trainer instead of the monolithic ones shown in the
diagram, in which case you don’t need the 1 KΩ resistors (they are built in to the LED input).
The nice thing about this circuit is that a lit LED indicates that the output is in state 1 (high
voltage), so you can put away your DMM.
Vary the input states for S and R (short for set and reset) according to the following truth table
and record the outputs ( 0 or 1) of Q and Q’. The notation 1  0 means that input is switched
from one state to another.
Latch Truth Table
S
R
0
1
1
0
0
0
1
1
1 -> 0
1
1
1 -> 0
Q
Q'
What is the effect of repeatedly turning off one of the inputs - i.e., the 1  0 sequence?
What does the circuit remember (in your own words)?
Try to explain the operation of the circuit. Start your explanation with the Q and Q’ outputs in a
given state (you choose) and both of the inputs held “high”, then see what happens when you
switch one of the inputs to “low” and then bring it back to “high”. Then try the other switch.
Sad but true: Using this type of latch you could build circuits that do things like count the
number of times things happen and add two binary numbers, but you never will. This simple
little latch has some quirks that make it really tough to deal with. This exercise was to get you
thinking about how feedback is used to generate memory. The other way of creating a memory
function (it’s called synchronous because all of the chips in a circuit are synchronized to an
external clock) is much more stable and easier to work with. The “innards” of these chips are
also complicated, so we won’t even think about what’s going on in the black box in this case. If
you are interested, the text has a schematic and you could figure out how they do what they do.
A Quirk: You will see a number of chips (like the JK flip-flop below and the 555 from before)
that “switch” on the transition from high to low in the clock (rather than the other, apparently
more intuitive direction). This is called active low and making a device switch states is called
asserting, so EEs would say that the JK requires you to assert an active low.
JK Flip-Flop
We’re going to skip the most common type of flip-flop used in electronics and computers (the D
flip-flop) and move on to the second most common type, which is the one that Chemists use
more often, the JK. One reason for doing this is that the JK can do everything the D can do, but
also has the toggle function that we will need for counting. You might wonder how often we
actually need to count discreet events in science, rather than measuring analog signals. The
answer is surprisingly often - from simple counting experiments like “how many times has the
bucket dumped in a rain meter?” to more elaborate ones like gated photon counting. The most
accurate and precise way to determine the length of time between two events is to count the
number of pulses from a very stable clock operating at a high frequency (a crystal oscillator).
Because these are the types of applications we use most often and because of the flexibility of the
JK type (it’s sometimes called the Cadillac of flip-flops) it is the type most widely used by
scientists. (We’d prefer to only have to learn how one device works and we’re willing to pay the
extra 50 cents per chip for that.)
Circuit Exercise 3 – There are two independent flip flops on the 7473 IC chip and both are
powered by connecting 5 V to pin 4 and ground to pin 11 (near the middle of the chip). The
pinout of the 7473 is shown below, along with a simplified diagram (called a functional
diagram) of a single JK FF to the right of the pinout. As with gates, the label on the pinout
combines a number that identifies the FF and a code specifying which of the various input or
output functions the pin is. Looking at the functional diagram, there are two logical inputs J and
K and a clock input, marked with the arrowhead > (that has a bubble on it). There are also
connections (one or two with bubbles) shown on the top and bottom of the diagram that are clear
functions (CLR’ on the pinout). These inputs can be used to override the normal function of the
chip and force the outputs into a defined state. Sometimes the clear functions assert immediately,
which is known as a jam clear, and sometimes they only become active on the next clock pulse.
This is an important specification of the chip, when it is necessary to use the clear function.
Finally, there are two complementary outputs (Q and Q’) for maximum application flexibility.
Concept Question 2 – Inputs marked with a bubble are asserted on an active low. Which inputs
described above will assert, or cause a change in the state of the output, on a negative going edge
or as a result of a low level?
Connect the TTL clock (red post) to the clock input for FF1, pin 1. Test the clear input (1CLR’)
and the J and K inputs according to the table below (using the 0/5 V SPDT switches, all of which
must be connected first) and for each set of connections, observe the input and output waveforms
with the scope. Record the states of Q and Q’ (always the inverse of Q) as 0, 1, or T (for toggle a change of states with each downward clock transition).
JK FF Truth Table
CLR
J
0
0
1
1
1
1
K
1
0
1
0
1
0
Q
Q'
1
0
1
1
0
0
Does anything ever happen when the clock isn’t switching? (You might have to disconnect it to
be sure.)
Do the changes in output state occur on the clock edge (up or down) that we expected?
What is the impact of the clear? Does it care what J and K are?
Does the “toggling” action occur when the J and K inputs are the same or when they are
different?
How could the JK FF be used as a latch? That is, how could we “load” a logical 0 to one of the
outputs on a clock pulse and then have it stay there for a while (storage or memory function) like
we did with the RS latch? This is the function of the D-type flip-flop that provides a subset of
the operating modes of the JK FF.
When the toggling action is observed, what is the frequency of the output pulse train with respect
to that of the input? This is a divide by what number?
Connect the two flip-flops (on the same 7473 chip) in series as shown below. The clock inputs
(pins 1 and 5) are both connected to the TTL clock (set for 1 kHz). Compare the outputs at Ql
(pin 12) and Q2 (pin 9) to the input signal.
By what factor does this circuit divide the input frequency (at Q2, the last output)?
The above implementation is important; sometimes we need to step the frequency of a waveform
down. What dividing factor would we obtain if we added one more FF to the chain?
The more interesting application of this type of circuit is as a counter. Let’s analyze how this
circuit counts using binary numbers:
1) Using the drawing tools or the paint program, draw the three waveforms at the input and two
output stages of the FFs. Start with all three chips in the “off” state.
2) Identify the least and most significant bits (LSB and MSB) in the counting scheme.
3) For each level you drew for the LSB, indicate which binary number is represented by all three
bits in the scheme.
4) Identify each of the binary numbers with a corresponding decimal number.
How many flip-flops would a counter need to be able to count to ten (decimal system)?
How could you prevent the circuit from counting to eleven? (I.e., how can it be reset at 10?)
Real World Example
After working with the flip-flop circuit, it may have occurred to you that your circuit design for
the laser safety interlock above could be improved. Describe how a flip-flop could be used in that
circuit to alleviate some of the potential timing problems associated with turning on the laser.
Revised 4/29/11