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Using Binary Resistors to Achieve Multilevel Resistive
Switching in Multilayer NiO/Pt Nanowire Arrays
Yen-Chun Huang, Po-Yuan Chen, Kuo-Feng Huang, Tzu-Chi Chuang, Yann-Wen Lan, Hsiu-Hau Lin,
Tsung-Shune Chin, Chii-Dong Chen, Ru-Shi Liu and Chih-Huang Lai*
Y. C. Huang, K. F. Huang, T. C. Chuang, Prof. C. H. Lai
Department of Materials Science and Engineering, National Tsing Hua University
Hsinchu 30013, Taiwan, R.O.C
Dr. P. Y. Chen
Institute of Electro-optical Science and Technology, National Taiwan Normal University
Taipei 116, Taiwan, R.O.C
Prof. H. H. Lin
Department of Physics, National Tsing Hua University
Hsinchu 30013, Taiwan, R.O.C
Prof. T. S. Chin
Department of Materials Science and Engineering, Feng Chia University
Taichung 40724, Taiwan, R.O.C
Dr. Y. W. Lan, Prof. C. D. Chen
Institute of Physics, Academia Sinica
Taipei 115, Taiwan, R.O.C
Prof. R. S. Liu
Department of Chemistry, National Taiwan University
Taipei 106, Taiwan, R.O.C
Keywords: nonpolar resistive switching, NiO, anodic aluminum oxide, multilayered nanowires,
multilevel memory effect
Supporting information S1 I-V characteristics of the AAO matrix (no RS behavior)
Supporting information S2 Variations of resistance with cycles of multilayered NiO/Pt nanowire
array devices with (a) unipolar and (b) bipolar operation; the resistance is read at 0.5 V. (c) The
retention data of the multilayered NiO/Pt nanowire array device.
Supporting information S3 Detail derivations for the total conductance within the binary-resistor
model are presented here. Note that the nanowire arrays consist of N w nanowires connected in
parallel while each nanowire contains N l cells connected in series. In total, the nanowire arrays
contain N w Nl conducting cells. When no conduction path is available, the resistance of a
conducting cell is high, denoted by R . The voltage pulses help the formation of the conduction path
in a cell and its resistance drops to a much smaller value r . In real samples, one expects that the
binary values R and r in each conducting cell should be different. However, if their variances are
small, it is reasonable to approximate all cells with the same binary resistances.
Within the binary-resistance model, LRS of the nanowire arrays exhibits the maximum
conductance Gmax = N w / Nl r while HRS shows the minimum conductance Gmin = Nw / Nl R . The
transport measurement starts with LRS. Upon application of one voltage pulse, it generates finite
probability p to flip the resistance of a cell from r to R . Suppose the binary-flip probability p
generated by one voltage pulse is small (several percentiles in our samples). The effect caused by n
successive voltage pulses is additive and the resultant binary-flip probability is simply np . The
finite binary-flip probability accounts for the inhomogeneous distribution of resistances in different
cells and the total conductance G of the nanowire arrays is
G = = å = Nw
V i=1 Ri
Note that the ensemble average in the above equation is justified because we have many nanowires
connected in parallel. The average reciprocal of the resistance 1/ R within each wire is described
by the usual binomial distribution,
æ 1 ö Nl
Nl -k
= åCk (np) (1- np)
÷ å Pk gk
r(Nl - k) + Rk è Nl r ø k=0
Here gk =
is the dimensionless conductance (normalized to the maximum
(Nl - k) + k(R / r)
conductance) for a wire with k flipped conducting cells, depending only on the resistor ratio R / r
governed by the binomial probability distribution Pk = CkNl (np)k (1- np)Nl -k . The maximum
conductance of the nanowire arrays in LRS (all cells in lower binary resistance) is Gmax = N w / Nl r
and it is convenient to re-express the total conductance as
Nw l
å k k max å Pk gk
N l r k=0
This is the major prediction of the binary-resistor model. In general, the summation is rather
complicated and needs to be carried out numerically. However, for large resistor ratio
R / r » 106 >>1, the summation is dominated by the k = 0 term and the expression for the total
conductance is greatly simplified. The claim can be easily verified by noticing that the conductance
for the flipped configurations is gk¹0 =
» l » 0 and thus can be ignored. The
(Nl - k) + k(R / r) kR
total conductance is well approximated by the k = 0 term alone,
= å Pk gk » P0 g0 = (1- np)Nl » e- Nl np
Gmax k=0
Note that P0 = (1- np) Nl and g0 =1 according to the previous definitions. Therefore, the total
conductance of the nanowire arrays exhibits simple dependence on the number of layers within each
wire N l , the number of applied voltage pulses n and the binary-flip probability p caused by a
single voltage pulse. The exponential form predicted by the binary-resistor model agrees with
experimental data rather well.
Supporting information S4
Renormalized current I / I max  G / Gmax versus the number of voltage pulses n . The experimental
data for the initial run are shown in red squares and those for the second run after reset are shown in
green diamonds. The blue curve is the theoretical prediction from the binary resistor model. The ratio
of the binary resistance R / r = 569010 is extracted experimentally and the estimated number of
units in each wire is Nl =100 . The only fitting parameter is the binary-flip probability p caused
by a single voltage pulse, fitted to the value p = 3.2% in this figure.
Supporting information S5 (a) The SEM image of the single multilayered NiO/Pt nanowire device
and the schematic diagram of the device measurement; (b) I-V characteristics of a single
multilayered NiO/Pt nanowire device
Supporting information S6
Let us estimate the robustness of the multilevel resistive state caused by a single voltage pulse.
Because the nanowire arrays consist of N w wires, the fluctuation in the total conductance is related
to that in a single wire,
1 Dg
Nw g
P0 (1- P0 )
where P0 » e- Nl p is the probability for the k = 0 term. For simplicity, we assume the conductance
for all k ¹ 0 terms are negligibly small and the fluctuations can be captured by the typical “shot
noise”. The total conductance of the resistive state caused by a single voltage is G = Gmax e- Nl p and
the next multilevel resistive state caused by two successive voltage pulses is Gmax e-2 Nl p = P0G . The
robustness of the resistive state requires the fluctuation DG smaller than the conductance difference
G - P0G between adjacent resistive states,
1 æ DG ö
÷ <<1.
G - P0G 1- P0 è G ø
After some algebra, it is straightforward to show that the criterion for the number of wires is
N w >>
P0 (1- P0 )