Download ECE 3235 Electronics II

ECE 3235 Electronics II
Experiment # 9
Gain Margin and Phase Margin
Note: (1) For this lab, you are going to use only Cadence software.
(2) It is suggested that you study Example 9.9 on page 617, Example 9.10 on page 619, and example
9.11 on page 623 of the textbook.
1. Design for phase margin of 45o
A differential amplifier has poles frequencies at f1 = 1 MHz, f2 = 8 MHz and f3 = 20 MHz. Use Ao = 10000,
Rin = 1 M ohms, Ro = 20 ohms and Beta = 0.1.
1.1 Compensate the amplifier by adding a pole at fc such that the phase margin is 45o, go
through the following steps to determine fc for Beta=0.1
 Build the amplifier macro model as shown in Figure 1 and modify its components with your
calculated values from step 1. (You can set resistor to a certain value, and use the pole frequencies to
calculate capacitance values, similar to the example 9.11 on page 623 of the book).
Note: the following circuit does not contain diodes in the output, so it is not able to shown voltage limiting
effects. You are suggested to include also the diodes as you did in previous experiments. So the output
voltage limits should be -14.6V to 14.6V.
Figure 1. Three-pole macromodel circuit for OpAmp
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Create a symbol for your amplifier.
Edit the amplifier symbol by deleting the entire green rectangle and using the Add => Shape =>
Polygon to a triangle as shown in the Figure 2 below.
Figure 2. Symbol for the macromodel circuit of Figure 1
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Using your amplifier symbol to build the following circuit in Figure 3.
Figure 3. A test circuit for Open-Loop frequency analysis
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Generate phase and magnitude bode plots for the uncompensated amplifier.
From the phase plot of the uncompensated amplifier phase, determine fPM. (it should have a phase shift
of -45 degrees)
From the magnitude plot of the uncompensated amplifier determine 20log|A(fPM)|.
Calculate 20log|Ac(fPM)|, which is the gain of the amplifier after compensation at frequency f= fPM.
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Use 20log|A(fPM)| and 20log|Ac(fPM) to find the additional attenuation introduced by the compensation
pole at fPM
Calculate the compensation frequency (fc) using additional attenuation of a single pole
-10{log[1+(f/fc)2]}
Now, find values for the compensation pole i.e. find Rc and Cc.
Modify the amplifier macromodel as shown below in Figure 4 by adding the compensation pole.
Figure 4. Macromodel circuit for the OpAmp with compensation pole
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Create a symbol for the compensated amplifier in Figure 4 (do not overwrite the one you had before).
Simulate the compensated amplifier using a similar test circuit as shown in Figure 2.
Generate phase and magnitude plots for the compensated amplifier.
From the phase plot of the compensated amplifier phase, determine the phase at fPM.
From the magnitude plot of the compensated amplifier determine 20log|Ac(fPM)|.
Now, if you can not achieve 45o of phase margin, then try to adjust your capacitor values in the compensation
stage so that you slowly change the compensation pole until you can achieve 45o of phase margin.
1.2 Design a series voltage feedback with Beta = 0.1
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Now, you can build a non-inverting amplifier with feedback Beta=0.1, construct the circuit in Cadence
Simulate the closed loop frequency response and record the frequency peak if any and 3db bandwidth
Simulate the closed loop transient response and record the rise time and overshoot (note that to do this,
first you have to give a square wave pulse, set the pulse width to 75*0.35/B, where B is the closedloop 3db bandwidth of the amplifier. You can estimate the bandwidth as we discussed in class. Also,
note that the pulse should change from 0 to at most 1.0V, because you amplifier output will be clipped
at +/- 15V. Second, note that the rise time is defined as the transition time needed to reach 90% of the
final steady value from 10% of the final steady value. For example, the you give the 1.0V pulse, the
final steady value should be 10V. So, you can measure the time rising from 0.1V to 0.9V. You do not
necessarily need to write an expression in Analog Design Environment for that, you can just record
that value. Third, the overshoot is defined as the maximum output minus the final steady value. Also,
record that value).
2. Design for Phase margin of 60o
In this part, you repeat the design process outlined in Part 11. and 1.2, but with a new goal of phase margin of
60o. Compare the closed-loop 3db bandwidth, frequency peak if any, rise time and overshoot with the case of
45o of phase margin.
Appendix 1: Cadence tips
(1) Use Vsin from AnalogLib for AC/frequency analysis
(2) Use Vsource from AanlogLib for transient analysis
(3) Always make use that circuit component, such as resistor, capacitors, VCCS should show their
resistance, capacitance and gain values beside its symbol in the schematic
(4) You might need to include the diode models during simulation if you include diodes in Figure 1
(5) Use dB20( ) calculator statement if you want to convert the gain into db format
(6) Use phase( ) calculator statement if you want to find phase of the output, note that you need to
subtract 180 to get the actual phase
Appendix 2: A large view of Figure 1