74VCX16374 Low Voltage 16-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs 7
... LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. ...
... LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. ...
LTM2882 - La documentation de Thierry LEQUEU sur OVH
... required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Coupled inductors and an isolation power transformer pro ...
... required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Coupled inductors and an isolation power transformer pro ...
AD8313 数据手册DataSheet 下载
... The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impeda ...
... The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impeda ...
MAX7306/MAX7307 SMBus/I C Interfaced 4-Port, Level-Translating GPIOs and LED Drivers
... transmission, regardless of the transmission actually addressing the device or not. The MAX7306 distinguishes whether address input AD0 is connected to SDA, SCL, V DD , or GND during the transmission. Therefore, the MAX7306 slave address can be configured dynamically in an application without toggli ...
... transmission, regardless of the transmission actually addressing the device or not. The MAX7306 distinguishes whether address input AD0 is connected to SDA, SCL, V DD , or GND during the transmission. Therefore, the MAX7306 slave address can be configured dynamically in an application without toggli ...
Power Efficiency of Multiple Clock, Multiple Voltage Cores
... designs compared to synchronous designs. However, their work targets a regular ASIC design flow with simpler clocking strategies rather than the aggressive clock distribution networks used in microprocessors. Of great importance in GALS designs is the choice of the asynchronous communication mechani ...
... designs compared to synchronous designs. However, their work targets a regular ASIC design flow with simpler clocking strategies rather than the aggressive clock distribution networks used in microprocessors. Of great importance in GALS designs is the choice of the asynchronous communication mechani ...
Rotary Encoder Interface Spartan
... work with, one side of each switch is connected to ground. So when the switch contacts are closed, the signal to the Spartan-3E is definitely Low or ‘0’. When the switch contacts are opened during rotation, a PULL-UP resistor is required to raise the signal to High or ‘1’. A nice feature of Spartan ...
... work with, one side of each switch is connected to ground. So when the switch contacts are closed, the signal to the Spartan-3E is definitely Low or ‘0’. When the switch contacts are opened during rotation, a PULL-UP resistor is required to raise the signal to High or ‘1’. A nice feature of Spartan ...
Input Impedance Measurement Using ADC FFT
... analog network response before RSx if the change in RSx value does not affect the analog network response. In other words, if RSx does not change the signal behavior at the earlier stages, then the measurement result is a function of RSx and the ADC input impedance only. ...
... analog network response before RSx if the change in RSx value does not affect the analog network response. In other words, if RSx does not change the signal behavior at the earlier stages, then the measurement result is a function of RSx and the ADC input impedance only. ...
a AN-402 APPLICATION NOTE •
... Another way to look at setting the clamp levels is by noting that the clamp signals (VH and VL) are alternate noninverting inputs that are selected when the conventional noninverting input goes outside the “window” that they establish. See Figure 7. It is desired to clamp 100 mV higher and lower tha ...
... Another way to look at setting the clamp levels is by noting that the clamp signals (VH and VL) are alternate noninverting inputs that are selected when the conventional noninverting input goes outside the “window” that they establish. See Figure 7. It is desired to clamp 100 mV higher and lower tha ...
DR230 Hybrid Recorder
... The DR230 is a high performance desk-top hybrid recorder that can measure data from 10 to 300 channels in 500 ms. Compact input modules measure input variables, such as temperature, flow rate, strain, etc. and can simultaneously record and transfer the measured data to a personal computer or store i ...
... The DR230 is a high performance desk-top hybrid recorder that can measure data from 10 to 300 channels in 500 ms. Compact input modules measure input variables, such as temperature, flow rate, strain, etc. and can simultaneously record and transfer the measured data to a personal computer or store i ...
Si838x Data Sheet
... Figure 2.2. SPI Communication Packet Structure, Write Operation and Control Byte Structure The SPI master will provide the timing of the signals and framing of the communication packets for all Si838x SPI inputs: NSS, SCLK, and MOSI. Data is communicated from the SPI master to the Si838x using the M ...
... Figure 2.2. SPI Communication Packet Structure, Write Operation and Control Byte Structure The SPI master will provide the timing of the signals and framing of the communication packets for all Si838x SPI inputs: NSS, SCLK, and MOSI. Data is communicated from the SPI master to the Si838x using the M ...
MapDCCD Version 2 Installation and setup guide
... signal wire switches between a high voltage and ground so that associated electronics correctly recognise the state change. If you are using an after-market hand brake or are not using the OEM wiring, you will need to install a pull up resistor into your hand brake wiring loom. You will need a 1k Oh ...
... signal wire switches between a high voltage and ground so that associated electronics correctly recognise the state change. If you are using an after-market hand brake or are not using the OEM wiring, you will need to install a pull up resistor into your hand brake wiring loom. You will need a 1k Oh ...
MAX8643A 3A, 2MHz Step-Down Regulator with Integrated Switches General Description
... o Lead-Free, 24-Pin, 4mm x 4mm Thin QFN Package ...
... o Lead-Free, 24-Pin, 4mm x 4mm Thin QFN Package ...
Lecture 1-1 Introduction to Micro Tranducers
... voltage connection (A): Zout low, Zin High. current connection(B) : Zout high, Zin low. Excitation The signal needed for the active transducer operation, usually specified as a range of voltage or current (sometimes including frequency, stability). Variations in the excitation may alter the transduc ...
... voltage connection (A): Zout low, Zin High. current connection(B) : Zout high, Zin low. Excitation The signal needed for the active transducer operation, usually specified as a range of voltage or current (sometimes including frequency, stability). Variations in the excitation may alter the transduc ...
Design and Analysis of High Speed Capacitive Pipeline DACs
... charge/discharge switches, and charge redistribution switches. The clock feed-through caused by the data switches is not meaningful because there is always a low time-constant path either to Vref or GND. Unlike this, the feed-through related to the charge switches changes the capacitor voltage when ...
... charge/discharge switches, and charge redistribution switches. The clock feed-through caused by the data switches is not meaningful because there is always a low time-constant path either to Vref or GND. Unlike this, the feed-through related to the charge switches changes the capacitor voltage when ...
OPA2683 Very Low-Power, Dual, Current-Feedback Operational Amplifier APPLICATIONS
... The output capability for the OPA2683 also sets a new mark in performance for very low-power, current-feedback amplifiers. Delivering a full ±4VPP swing on ±5V supplies, the OPA2683 also has the output current to support this swing into a 100Ω load. This minimal output headroom requirement is comple ...
... The output capability for the OPA2683 also sets a new mark in performance for very low-power, current-feedback amplifiers. Delivering a full ±4VPP swing on ±5V supplies, the OPA2683 also has the output current to support this swing into a 100Ω load. This minimal output headroom requirement is comple ...
MAX13181E–MAX13184E +5.0V, ±15kV ESD-Protected, Half-Duplex/ Full-Duplex, RS-485 Transceiver in µDFN General Description
... Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high. Similarly, a high on DI forces noninverting output high and inverting output low. ...
... Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high. Similarly, a high on DI forces noninverting output high and inverting output low. ...
RF3854 LOW NOISE, MULTI-MODE, QUAD-BAND, QUADRATURE MODULATOR AND PA DRIVER
... The RF3854 is a low noise, multi-mode, quad-band direct I/Q to RF modulator and PA driver solution designed for digital modulation applications ranging from 800MHz to 2000MHz. Frequency doublers, dividers and LO buffers are included to support a variety of LO generation options. Dynamic power contro ...
... The RF3854 is a low noise, multi-mode, quad-band direct I/Q to RF modulator and PA driver solution designed for digital modulation applications ranging from 800MHz to 2000MHz. Frequency doublers, dividers and LO buffers are included to support a variety of LO generation options. Dynamic power contro ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.