GS2989 - Semtech
... The input coupling capacitor must be set accordingly for lower data rates. Turning on input trace equalization will reduce jitter in most applications. Rise/Fall time measured between 20% and 80% applies to 800mV output swing only. Single-ended into a 75Ω external load. Calculated as the actual posi ...
... The input coupling capacitor must be set accordingly for lower data rates. Turning on input trace equalization will reduce jitter in most applications. Rise/Fall time measured between 20% and 80% applies to 800mV output swing only. Single-ended into a 75Ω external load. Calculated as the actual posi ...
Power Factor Correction Using PIC Microcontroller
... The main part of the circuit is Microcontroller (18F452) with crystal of Il MHz After acquiring voltage and current signals they are then passed through the zero cross detector block (ZCD V and ZCD l), that converts both voltage and current waveforms in square-wave that are further provided to micro ...
... The main part of the circuit is Microcontroller (18F452) with crystal of Il MHz After acquiring voltage and current signals they are then passed through the zero cross detector block (ZCD V and ZCD l), that converts both voltage and current waveforms in square-wave that are further provided to micro ...
USB-OTG full-speed transceiver
... VBUS valid status means that the voltage is above VBUS_VLD. Session valid status means that the VBUS voltage is above VSES_VLD level. ...
... VBUS valid status means that the voltage is above VBUS_VLD. Session valid status means that the VBUS voltage is above VSES_VLD level. ...
Evaluates: MAX1982/MAX1983 MAX1982 Evaluation Kit General Description Features
... The MAX1982 has an active-low shutdown control input to enable/disable its output. The 3-pin header JU1 selects the shutdown mode. Remove the shunt when driving shutdown with an external signal. Table 1 lists the jumper selectable options. ...
... The MAX1982 has an active-low shutdown control input to enable/disable its output. The 3-pin header JU1 selects the shutdown mode. Remove the shunt when driving shutdown with an external signal. Table 1 lists the jumper selectable options. ...
EPC 8 Patch Clamp Amplifier
... of the EPC 8 via LIH 1600 is included with the EPC 8 delivery volume thus allowing the use of this patch clamp amplifier together with your own programmed data acquisition software. Anybody, therefore, can use this patch clamp amplifier with his/her own data acquisition software. ...
... of the EPC 8 via LIH 1600 is included with the EPC 8 delivery volume thus allowing the use of this patch clamp amplifier together with your own programmed data acquisition software. Anybody, therefore, can use this patch clamp amplifier with his/her own data acquisition software. ...
AFV User Manual - Intepro Systems
... power supply has stable output frequency and good continuity. AFV series power supplies provide continuous, pure and stable sinusoidal voltage. They can achieve local control via remote control through the user’s PC using internal control and communication modules. The internal electronic circuit ca ...
... power supply has stable output frequency and good continuity. AFV series power supplies provide continuous, pure and stable sinusoidal voltage. They can achieve local control via remote control through the user’s PC using internal control and communication modules. The internal electronic circuit ca ...
TPS74901EVM-210 (Rev. B
... The EVM uses ±1% feedback resistors. Therefore, the EVM output tolerance is the ±2% internal reference tolerance plus 2 × (1 – VREF/VOUT) × TOLFBRES = 2 × (1– 0.8V/1.2V) ×± 2% = 1.3% or ±3.3%. For tighter output tolerance, tighter tolerance feedback resistors must be used. ...
... The EVM uses ±1% feedback resistors. Therefore, the EVM output tolerance is the ±2% internal reference tolerance plus 2 × (1 – VREF/VOUT) × TOLFBRES = 2 × (1– 0.8V/1.2V) ×± 2% = 1.3% or ±3.3%. For tighter output tolerance, tighter tolerance feedback resistors must be used. ...
TAS5111A 数据资料 dataSheet 下载
... necessary. The RESET must be asserted LOW before the valid PWM signal is removed. When TI TDAA modulators are used with TI TDAA back ends, the correct timing control of RESET and PWM_xP is performed by the modulator. ...
... necessary. The RESET must be asserted LOW before the valid PWM signal is removed. When TI TDAA modulators are used with TI TDAA back ends, the correct timing control of RESET and PWM_xP is performed by the modulator. ...
TGA2514 数据资料DataSheet下载
... The TGA2514 provides a nominal 38 dBm of saturated power with a small signal gain of 24 dB. Typical return loss is 14 dB. The TGA2514 is 100% DC and RF tested on-wafer to ensure performance ...
... The TGA2514 provides a nominal 38 dBm of saturated power with a small signal gain of 24 dB. Typical return loss is 14 dB. The TGA2514 is 100% DC and RF tested on-wafer to ensure performance ...
Variable Regulated DC Power Supplies PAD
... Note: The unit has Intake port for the ventilation of forced cooling, therefore, it is required to install the blank panel in case of assembling ...
... Note: The unit has Intake port for the ventilation of forced cooling, therefore, it is required to install the blank panel in case of assembling ...
DC Measurements, Voltage Dividers, and Bridges
... No formal error analysis is required, but you are required to estimate your errors and use them to evaluate whether the theory being tested is correct. 1. Build three copies of the simple voltage divider circuit of prelab Figure 2.4(a), with both resistors approximately equal to each other. In the f ...
... No formal error analysis is required, but you are required to estimate your errors and use them to evaluate whether the theory being tested is correct. 1. Build three copies of the simple voltage divider circuit of prelab Figure 2.4(a), with both resistors approximately equal to each other. In the f ...
lab sheet - Faculty of Engineering
... 2. Adjust the sending-end voltage E1 to 300 V and keep it constant for the reminder part of the experiment. Use a three-phase resistive load and increase the load in steps making sure that the loads are balanced. Take readings of sending end and receiving end voltages and powers, E1, Q1, P1, E2, Q2, ...
... 2. Adjust the sending-end voltage E1 to 300 V and keep it constant for the reminder part of the experiment. Use a three-phase resistive load and increase the load in steps making sure that the loads are balanced. Take readings of sending end and receiving end voltages and powers, E1, Q1, P1, E2, Q2, ...
Real Time Modeling and Simulation of Cyber-Power System
... Local control systems typically make use of the data available within a single substation. These control systems do not take into account the state of the system in other locations to take control decisions and actions. The control action may be opening/closing of circuit breakers to reroute power, ...
... Local control systems typically make use of the data available within a single substation. These control systems do not take into account the state of the system in other locations to take control decisions and actions. The control action may be opening/closing of circuit breakers to reroute power, ...
AsyncRFID : Fully Asynchronous Contactless Systems
... ¨ Only active where and when needed F Reduction of global power consumption for digital blocks ...
... ¨ Only active where and when needed F Reduction of global power consumption for digital blocks ...
SG3524 SMPS control circuit
... shutdown terminal: i.e., the output will be off with Pin 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the network of Figure 10. This circuit can reduce the short-circuit current (ISC) to approximately one-third the maximum available output current (IMAX) ...
... shutdown terminal: i.e., the output will be off with Pin 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the network of Figure 10. This circuit can reduce the short-circuit current (ISC) to approximately one-third the maximum available output current (IMAX) ...
Stress and Strain Lab - Gateway Engineering Education Coalition
... Select the lightest and heaviest person in your team. These two will ride the bike. Set up the data logger as described in the Quick Reference Guide. Use the “real-time data acquisition” mode to view the data collected by the data logger. Make sure that the initial output signal without a rider is n ...
... Select the lightest and heaviest person in your team. These two will ride the bike. Set up the data logger as described in the Quick Reference Guide. Use the “real-time data acquisition” mode to view the data collected by the data logger. Make sure that the initial output signal without a rider is n ...
lab sheet - Faculty of Engineering
... 2. Adjust the sending-end voltage E1 to 300 V and keep it constant for the reminder part of the experiment. Use a three-phase resistive load and increase the load in steps making sure that the loads are balanced. Take readings of sending end and receiving end voltages and powers, E1, Q1, P1, E2, Q2, ...
... 2. Adjust the sending-end voltage E1 to 300 V and keep it constant for the reminder part of the experiment. Use a three-phase resistive load and increase the load in steps making sure that the loads are balanced. Take readings of sending end and receiving end voltages and powers, E1, Q1, P1, E2, Q2, ...
network theorems module
... As the voltage source does not contribute any output voltage, Only the current source has the effect. ...
... As the voltage source does not contribute any output voltage, Only the current source has the effect. ...
MAX3892 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis General Description
... Relative to the falling edge of the SCLKO. Measurement bandwidth is BW = 12kHz to 20MHz. Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the Jitter Generation vs. RCLK to PCLK/PDI[3:0] Phase plot in the Typical Operating Characteristics section. Deterministic jit ...
... Relative to the falling edge of the SCLKO. Measurement bandwidth is BW = 12kHz to 20MHz. Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the Jitter Generation vs. RCLK to PCLK/PDI[3:0] Phase plot in the Typical Operating Characteristics section. Deterministic jit ...