installer`s reference xtant technologies
... ports dedicated to the amplifier are labeled Amp Vert/Horiz Acc. Port and Amp Vert. Acc. Port. The fifth port is dedicated to the RCA line outputs and is labeled Line Out Vert. Acc. Port. Xtant offers two types of accessory modules which are designed for either “Horizontal” or “Vertical” mounting. T ...
... ports dedicated to the amplifier are labeled Amp Vert/Horiz Acc. Port and Amp Vert. Acc. Port. The fifth port is dedicated to the RCA line outputs and is labeled Line Out Vert. Acc. Port. Xtant offers two types of accessory modules which are designed for either “Horizontal” or “Vertical” mounting. T ...
OP497
... 25ⴗC: 100 pA max –55ⴗC to +125ⴗC: 450 pA max Very High Open-Loop Gain: 2000 V/mV min Low Supply Current (per Amplifier): 625 A max Operates from ⴞ2 V to ⴞ20 V Supplies High Common-Mode Rejection: 120 dB min ...
... 25ⴗC: 100 pA max –55ⴗC to +125ⴗC: 450 pA max Very High Open-Loop Gain: 2000 V/mV min Low Supply Current (per Amplifier): 625 A max Operates from ⴞ2 V to ⴞ20 V Supplies High Common-Mode Rejection: 120 dB min ...
MAX2754.pdf
... polarity, an external inverter and three-state buffer would be required. These devices are offered in small single-logic gates in SC-79 style packages from various manufacturers (e.g., Fairchild—Tiny Logic, On Semiconductor, or Rohm). Figure 1 illustrates the frequency versus VMOD characteristic of ...
... polarity, an external inverter and three-state buffer would be required. These devices are offered in small single-logic gates in SC-79 style packages from various manufacturers (e.g., Fairchild—Tiny Logic, On Semiconductor, or Rohm). Figure 1 illustrates the frequency versus VMOD characteristic of ...
ADS5231 数据资料 dataSheet 下载
... If the offset at temperatures T1 and T2 are O1 and O2, respectively (where O1 and O2 are measured in LSBs), the offset temperature coefficient in ppm/°C is calculated as (O1 – O2)/(T1 – T2) × 1E6/4096. Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold ampl ...
... If the offset at temperatures T1 and T2 are O1 and O2, respectively (where O1 and O2 are measured in LSBs), the offset temperature coefficient in ppm/°C is calculated as (O1 – O2)/(T1 – T2) × 1E6/4096. Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold ampl ...
ADA4922-1 数据手册DataSheet 下载
... amplifier, the ADA4922-1 requires no external components to drive ADCs. The ADA4922-1 provides essential benefits such as low distortion and high SNR that are required for driving ADCs with resolutions up to 18 bits. With a wide supply voltage range (5 V to 26 V), high input impedance, and fixed dif ...
... amplifier, the ADA4922-1 requires no external components to drive ADCs. The ADA4922-1 provides essential benefits such as low distortion and high SNR that are required for driving ADCs with resolutions up to 18 bits. With a wide supply voltage range (5 V to 26 V), high input impedance, and fixed dif ...
A4923 - Allegro Microsystems
... Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the i ...
... Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the i ...
SFX-424G Synchronous Clock Generators Applications
... translates up to four inputs from 8 kHz to 100MHz, to output frequencies between 8 MHz and 800 MHz. The SFX-424G supports all major FEC rates such as 15/14, 255/237 etc. SFX-424G is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, ph ...
... translates up to four inputs from 8 kHz to 100MHz, to output frequencies between 8 MHz and 800 MHz. The SFX-424G supports all major FEC rates such as 15/14, 255/237 etc. SFX-424G is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, ph ...
A Simple Control Scheme for Single
... appropriate switching. For obtaining negative half cycle of output the positive half of the input is inverted and fed across load by making S2 and S3 on and the negative half of the input is fed directly across load as S1 and S4 are made on. This can be clearly understood by Fig.3 (a) and (b) which ...
... appropriate switching. For obtaining negative half cycle of output the positive half of the input is inverted and fed across load by making S2 and S3 on and the negative half of the input is fed directly across load as S1 and S4 are made on. This can be clearly understood by Fig.3 (a) and (b) which ...
stgipq8c60t-hz - STMicroelectronics
... internal voltage reference VREF connected to the inverting input, while the non-inverting input on pin (CIN) can be connected to an external shunt resistor for simple overcurrent protection. When the comparator triggers, the device is set to the Shutdown state and both its outputs are switched to th ...
... internal voltage reference VREF connected to the inverting input, while the non-inverting input on pin (CIN) can be connected to an external shunt resistor for simple overcurrent protection. When the comparator triggers, the device is set to the Shutdown state and both its outputs are switched to th ...
DM9374 7-Segment Decoder/Driver/Latch with Constant Current
... Another ’74 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 mA typ). This allows many ’74s to be driven from a MOS device in multiplex mode without the need for drivers on the data lines. The ’74 also provides automatic blanking of the leading and/or trailing ...
... Another ’74 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 mA typ). This allows many ’74s to be driven from a MOS device in multiplex mode without the need for drivers on the data lines. The ’74 also provides automatic blanking of the leading and/or trailing ...
The Bride of Zen: A Single Gain Stage Preamplifier Intro This is the
... response. We will have much less reason to employ feedback in this circuit, and so we will not. Another advantage that the preamp circuit will enjoy over the power amplifier is the relatively small dissipation involved. The Zen single-ended power amplifier idles at more than four times its output ra ...
... response. We will have much less reason to employ feedback in this circuit, and so we will not. Another advantage that the preamp circuit will enjoy over the power amplifier is the relatively small dissipation involved. The Zen single-ended power amplifier idles at more than four times its output ra ...
MAX11205 16-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface General Description
... 16-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface The MAX11205 is an ultra-low power (< 240FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications tha ...
... 16-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface The MAX11205 is an ultra-low power (< 240FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications tha ...
MAX3880 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery General Description
... The synchronization inputs (SYNC+, SYNC-) realign the output data word. Realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal’s positive transition. During synchronization, the first incoming bit of data during that PCLK cycle is ...
... The synchronization inputs (SYNC+, SYNC-) realign the output data word. Realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal’s positive transition. During synchronization, the first incoming bit of data during that PCLK cycle is ...
OP97
... The ac characteristics of the OP97 are highly stable over its full operating temperature range. Unity-gain small-signal response is shown in Figure 30. Extremely tolerant of capacitive loading on the output, the OP97 displays excellent response even with 1000 pF loads (see Figure 31). In large signa ...
... The ac characteristics of the OP97 are highly stable over its full operating temperature range. Unity-gain small-signal response is shown in Figure 30. Extremely tolerant of capacitive loading on the output, the OP97 displays excellent response even with 1000 pF loads (see Figure 31). In large signa ...
DS1843 Fast Sample-and-Hold Circuit General Description Features
... designed to operate in fiber optic burst-mode systems; however, it can be used in other applications requiring a fast sample-and-hold circuit. The output can be configured for single-ended operations. ...
... designed to operate in fiber optic burst-mode systems; however, it can be used in other applications requiring a fast sample-and-hold circuit. The output can be configured for single-ended operations. ...
Analog-to-digital converter
An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input. The result is a sequence of digital values that have been converted from a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.An ADC is defined by its bandwidth (the range of frequencies it can measure) and its signal to noise ratio (how accurately it can measure a signal relative to the noise it introduces). The actual bandwidth of an ADC is characterized primarily by its sampling rate, and to a lesser extent by how it handles errors such as aliasing. The dynamic range of an ADC is influenced by many factors, including the resolution (the number of output levels it can quantize a signal to), linearity and accuracy (how well the quantization levels match the true analog signal) and jitter (small timing errors that introduce additional noise). The dynamic range of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise. An ideal ADC has an ENOB equal to its resolution. ADCs are chosen to match the bandwidth and required signal to noise ratio of the signal to be quantized. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then perfect reconstruction is possible given an ideal ADC and neglecting quantization error. The presence of quantization error limits the dynamic range of even an ideal ADC, however, if the dynamic range of the ADC exceeds that of the input signal, its effects may be neglected resulting in an essentially perfect digital representation of the input signal.An ADC may also provide an isolated measurement such as an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. The digital output may use different coding schemes. Typically the digital output will be a two's complement binary number that is proportional to the input, but there are other possibilities. An encoder, for example, might output a Gray code.The inverse operation is performed by a digital-to-analog converter (DAC).