ADP1740 数据手册DataSheet 下载
... of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced, proprietary architecture, the ADP1740/ ADP1741 provide high power supply rejection ratio (P ...
... of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced, proprietary architecture, the ADP1740/ ADP1741 provide high power supply rejection ratio (P ...
MAX14778 Dual ±25V Above- and Below-the-Rails 4:1 Analog Multiplexer General Description
... When VDD = 0V, the DC input leakage current into the A_, B_, ACOM or BCOM pins will typically be below 1µA. Some devices can have a larger leakage current up to mA range due to technology spread. With VDD not powered, internal diodes between the analog pins and the VP and VN will charge up the exter ...
... When VDD = 0V, the DC input leakage current into the A_, B_, ACOM or BCOM pins will typically be below 1µA. Some devices can have a larger leakage current up to mA range due to technology spread. With VDD not powered, internal diodes between the analog pins and the VP and VN will charge up the exter ...
AD5304 数据手册DataSheet 下载
... Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the seria ...
... Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the seria ...
AD5313 数据手册DataSheet 下载
... Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. It may be configured as a buffered or an un ...
... Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. It may be configured as a buffered or an un ...
SP3220E 数据资料DataSheet下载
... was active at 1000kbps and loaded with an RS-232 receiver in parallel with 250pF capacitors. A solid RS-232 data transmission rate of 250kbps provides compatibility with many designs in personal computer peripherals and LAN applications. ...
... was active at 1000kbps and loaded with an RS-232 receiver in parallel with 250pF capacitors. A solid RS-232 data transmission rate of 250kbps provides compatibility with many designs in personal computer peripherals and LAN applications. ...
MAX9374/MAX9374A Differential LVPECL-to-LVDS Translators General Description Features
... single-ended input signal to the D input. Similarly, an inverting input is produced by connecting VBB to the D input and applying the input signal to the D input. With a differential input configured as single ended (using VBB), the single-ended input can be driven to VCC and GND or with a single-en ...
... single-ended input signal to the D input. Similarly, an inverting input is produced by connecting VBB to the D input and applying the input signal to the D input. With a differential input configured as single ended (using VBB), the single-ended input can be driven to VCC and GND or with a single-en ...
Design of Single-Switch Inverters for Variable Resistance / Load
... with Qfil selected in the range of 2 to 10 for adequate filtering over a 10:1 load resistance range. Note that although larger values for Qfil result in output voltage waveforms with less harmonic content, they also give rise to higher circulating currents in the output tank, and hence yield higher ...
... with Qfil selected in the range of 2 to 10 for adequate filtering over a 10:1 load resistance range. Note that although larger values for Qfil result in output voltage waveforms with less harmonic content, they also give rise to higher circulating currents in the output tank, and hence yield higher ...
an area efficient 64-bit square root carry
... consumption of their circuits. In the process, it is found that the schematic given in [4] contains an error and the circuit has been rectified to ensure its correct functionality before simulations. A simulation environment realistic to the actual circuit operational conditions has been set up, whe ...
... consumption of their circuits. In the process, it is found that the schematic given in [4] contains an error and the circuit has been rectified to ensure its correct functionality before simulations. A simulation environment realistic to the actual circuit operational conditions has been set up, whe ...
Design of Single-Switch Inverters for Variable Resistance
... with Qfil selected in the range of 2 to 10 for adequate filtering over a 10:1 load resistance range. Note that although larger values for Qfil result in output voltage waveforms with less harmonic content, they also give rise to higher circulating currents in the output tank, and hence yield higher ...
... with Qfil selected in the range of 2 to 10 for adequate filtering over a 10:1 load resistance range. Note that although larger values for Qfil result in output voltage waveforms with less harmonic content, they also give rise to higher circulating currents in the output tank, and hence yield higher ...
S8VM (15/30/50/100/150/300/600/1,500
... 3. If the output voltage adjuster (V. ADJ) is turned, the voltage will increase by more than +20% of the voltage adjustment range. If the adjuster is turned too far, it may activate the overvoltage protection function and interrupt the output. When adjusting the output voltage, confirm the actual ou ...
... 3. If the output voltage adjuster (V. ADJ) is turned, the voltage will increase by more than +20% of the voltage adjustment range. If the adjuster is turned too far, it may activate the overvoltage protection function and interrupt the output. When adjusting the output voltage, confirm the actual ou ...
MAX3453E–MAX3456E ±15kV ESD-Protected USB Transceivers General Description Features
... The MAX3453E–MAX3456E ±15kV ESD-protected USBcompliant transceivers interface low-voltage ASICs with USB devices. The devices fully comply with USB 1.1 and USB 2.0 when operating at full (12Mbps) and low (1.5Mbps) speeds. The MAX3453E–MAX3456E operate with VL as low as +1.65V, ensuring compatibility ...
... The MAX3453E–MAX3456E ±15kV ESD-protected USBcompliant transceivers interface low-voltage ASICs with USB devices. The devices fully comply with USB 1.1 and USB 2.0 when operating at full (12Mbps) and low (1.5Mbps) speeds. The MAX3453E–MAX3456E operate with VL as low as +1.65V, ensuring compatibility ...
INA21x Voltage Output, Low
... Quiescent Current: 100 μA (max) SC70 and Thin UQFN Packages: All Models ...
... Quiescent Current: 100 μA (max) SC70 and Thin UQFN Packages: All Models ...
Old Company Name in Catalogs and Other Documents
... (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. ...
... (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. ...
ADL5367 数据手册DataSheet 下载
... 1700 MHz RF input frequency range. Performance is optimized for RF frequencies from 500 MHz to 1200 MHz using a high-side LO and for RF frequencies from 900 MHz to 1700 MHz using a low-side LO. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −35 dBm, and ...
... 1700 MHz RF input frequency range. Performance is optimized for RF frequencies from 500 MHz to 1200 MHz using a high-side LO and for RF frequencies from 900 MHz to 1700 MHz using a low-side LO. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −35 dBm, and ...
AD5061 数据手册DataSheet 下载
... from a single 2.7 V to 5.5 V supply. The part offers a relative accuracy specification of ±4 LSB and operation is guaranteed monotonic with a ±1 LSB DNL specification. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPI®, Q ...
... from a single 2.7 V to 5.5 V supply. The part offers a relative accuracy specification of ±4 LSB and operation is guaranteed monotonic with a ±1 LSB DNL specification. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPI®, Q ...
MAX2411A Low-Cost RF Up/Downconverter with LNA and PA Driver ________________General Description
... input third-order intercept point (IP3). The downconverter mixer has a low 9.2dB noise figure and 4dBm input IP3. Image and local-oscillator filtering are implemented off-chip for maximum flexibility. The PA driver amplifier has 15dB of gain, which can be reduced over a 35dB range. Power consumption ...
... input third-order intercept point (IP3). The downconverter mixer has a low 9.2dB noise figure and 4dBm input IP3. Image and local-oscillator filtering are implemented off-chip for maximum flexibility. The PA driver amplifier has 15dB of gain, which can be reduced over a 35dB range. Power consumption ...
ADCLK854 数据手册DataSheet 下载
... responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog ...
... responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog ...
CM1235 - Small Footprint ESD Clamp Array for
... makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device an ...
... makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device an ...