Synchronous Generator Load Angle Measurement and Estimation
... The load angle estimation algorithm was implemented on the developed digital system DIRES 21 [2] (Figure 4). The algorithm was developed by graphical oriented software tool. In graphical environment, basic blocks implemented via assemble programming language, were connected in more complex control s ...
... The load angle estimation algorithm was implemented on the developed digital system DIRES 21 [2] (Figure 4). The algorithm was developed by graphical oriented software tool. In graphical environment, basic blocks implemented via assemble programming language, were connected in more complex control s ...
DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS
... This research work is an attempt to design a full adder Custom Cell Design using 8 transistors in 0.18 µm CMOS Technology. It involves use of 3-T XOR gate to implement the SUM circuit and Cout is implemented using a CMOS Multiplexer and suitable CMOS logic. Total Power dissipation through wei et al ...
... This research work is an attempt to design a full adder Custom Cell Design using 8 transistors in 0.18 µm CMOS Technology. It involves use of 3-T XOR gate to implement the SUM circuit and Cout is implemented using a CMOS Multiplexer and suitable CMOS logic. Total Power dissipation through wei et al ...
UPS-Genset Compatibility
... UPSs and gensets in high-availability installations The combination of a UPS (Uninterruptible Power Supply) and a generator set is an increasingly frequent solution used to supply sensitive loads such as computers, telecommunication centres, industrial processes, hospitals, airports, etc. These two ...
... UPSs and gensets in high-availability installations The combination of a UPS (Uninterruptible Power Supply) and a generator set is an increasingly frequent solution used to supply sensitive loads such as computers, telecommunication centres, industrial processes, hospitals, airports, etc. These two ...
A.D. Sagneri, D.I. Anderson, and D.J. Perreault, “Optimization of Integrated Transistors for Very High Frequency dc-dc Converters,” IEEE Transactions on Power Electronics , Vol. 28, No. 7, pp. 3614-3626, July 2013.
... Semiconductor device losses place critical limits on the design and performance of power converters. As a result, significant effort has been devoted to the optimization of power devices. Most converters operate under hard-switching conditions, or at frequencies below a few megahertz, and optimizati ...
... Semiconductor device losses place critical limits on the design and performance of power converters. As a result, significant effort has been devoted to the optimization of power devices. Most converters operate under hard-switching conditions, or at frequencies below a few megahertz, and optimizati ...
Optimization of Integrated Transistors for Very High Frequency DC-DC Converters Please share
... Semiconductor device losses place critical limits on the design and performance of power converters. As a result, significant effort has been devoted to the optimization of power devices. Most converters operate under hard-switching conditions, or at frequencies below a few megahertz, and optimizati ...
... Semiconductor device losses place critical limits on the design and performance of power converters. As a result, significant effort has been devoted to the optimization of power devices. Most converters operate under hard-switching conditions, or at frequencies below a few megahertz, and optimizati ...
Chapter 8 UFSAR Table of Contents
... The Class 1E dc and UPS system has sufficient capacity to achieve and maintain safe shutdown of the plant for 72 hours following a complete loss of all ac power sources without requiring load shedding for the first 24 hours. ...
... The Class 1E dc and UPS system has sufficient capacity to achieve and maintain safe shutdown of the plant for 72 hours following a complete loss of all ac power sources without requiring load shedding for the first 24 hours. ...
paper - Auburn University
... circuit, its threshold voltage should be decreased by the same factor, which increases the subthreshold (leakage) current of transistors exponentially [1]. Therefore, with the trend of CMOS technology scaling, leakage power is becoming a dominant contributor to the total power consumption. To reduce ...
... circuit, its threshold voltage should be decreased by the same factor, which increases the subthreshold (leakage) current of transistors exponentially [1]. Therefore, with the trend of CMOS technology scaling, leakage power is becoming a dominant contributor to the total power consumption. To reduce ...
MAX9716/MAX9717 Low-Cost, Mono, 1.4W BTL Audio Power Amplifiers General Description
... power into a 4Ω load with less than 1% Total Harmonic Distortion (THD) while operating from a single +5V supply. With an 8Ω load, both devices deliver 1W continuous power. These devices also deliver 350mW continuous power into an 8Ω load while operating from a single +3.0V supply. The devices are av ...
... power into a 4Ω load with less than 1% Total Harmonic Distortion (THD) while operating from a single +5V supply. With an 8Ω load, both devices deliver 1W continuous power. These devices also deliver 350mW continuous power into an 8Ω load while operating from a single +3.0V supply. The devices are av ...
SiC Power Device
... including: high breakdown voltage, low power consumption, and high-speed switching operation not provided by conventional silicon devices. In response to the growing demand for SiC products, ROHM has implemented the world's first full-scale, mass production of next-generation SiC components. ...
... including: high breakdown voltage, low power consumption, and high-speed switching operation not provided by conventional silicon devices. In response to the growing demand for SiC products, ROHM has implemented the world's first full-scale, mass production of next-generation SiC components. ...
AT-1.0 Manual.qxd
... 1. Pull four-conductor wire from each room (home runs) to the AT-1.0 near the controlled components. Note: Use 24 gauge unshielded solid or stranded copper wire up to 1200' (Cat. 5e ok), 22 gauge up to 2000', 20 gauge up to 3000' and 18 gauge up to 5300'. Total lengths include all wire runs from eac ...
... 1. Pull four-conductor wire from each room (home runs) to the AT-1.0 near the controlled components. Note: Use 24 gauge unshielded solid or stranded copper wire up to 1200' (Cat. 5e ok), 22 gauge up to 2000', 20 gauge up to 3000' and 18 gauge up to 5300'. Total lengths include all wire runs from eac ...
Optimization of LDMOS Transistor in Power Amplifiers for Communication Systems
... design of power amplifiers (PAs), which is considered as a heart of basestation. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much m ...
... design of power amplifiers (PAs), which is considered as a heart of basestation. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much m ...
PDF
... 400-V/22-kW class SiC inverter to check the limit for reducing power loss with the SiC inverter. Figure 5 shows an external view of the prototype inverter and the inside of the SiC module. An effective way of reducing the SiC inverter loss is by using a high-speed drive for the SiC device, which red ...
... 400-V/22-kW class SiC inverter to check the limit for reducing power loss with the SiC inverter. Figure 5 shows an external view of the prototype inverter and the inside of the SiC module. An effective way of reducing the SiC inverter loss is by using a high-speed drive for the SiC device, which red ...
