Download CMOS Logic Design with Independent-gate FinFETs

FinFETs: From Circuit to
Architecture
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University
Joint work with: Anish Muttreja, Prateek Mishra,
Chun-Yi Lee, Ajay Bhoj and Wei Zhang
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd/Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Why Double-gate Transistors ?
Feature size
32 nm
Bulk CMOS
DG-FETs
Gap
10 nm
Non-Si nano devices
• DG-FETs can be used to fill this gap
• DG-FETs are extensions of CMOS
– Manufacturing processes similar to CMOS
• Key limitations of CMOS scaling addressed through
–
–
–
–
–
Better control of channel from transistor gates
Reduced short-channel effects
Better Ion/Ioff
Improved sub-threshold slope
No discrete dopant fluctuations
What are FinFETs?
• Fin-type DG-FET
– A FinFET is like a FET, but the channel has been “turned on its edge”
and made to stand up
Si Fin
Independent-gate FinFETs
Oxide insulation
Back Gate
• Both the gates of a FET can be independently controlled
• Independent control
– Requires an extra process step
– Leads to a number of interesting analog and digital circuit
structures
FinFET Width Quantization
• Electrical width of a FinFET
with n fins: W = 2*n*h
• Channel width in a FinFET is
quantized
• Width quantization is a
design challenge if fine
control of transistor drive
strength is needed
–E.g., in ensuring
stability of memory
cells
FinFET structure
Ananthan, ISQED’05
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd/Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Motivation: Power Consumption
• Traditional view of CMOS power
consumption
– Active mode: Dynamic power (switching +
short circuit + glitching)
– Standby mode: Leakage power
• Problem: rising active leakage
– 40% of total active mode power consumption
(70nm bulk CMOS) †
†J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction
techniques,” in Proc. ICCAD, 2002.
Logic Styles: NAND Gates
SG-mode NAND
pull up bias
voltage
LP-mode NAND
pull down
bias voltage
IG-mode NAND
IG-mode
pull up
IG/LP-mode NAND
LP-mode
pull down
Comparing Logic Styles
Design Mode
Advantages
Disadvantages
SG
Fastest under all load
conditions
High leakage† (1μA)
LP
Very low leakage
(85nA), low switched
capacitance
Slowest, especially under
load. Area overhead
(routing)
IG
Low area and switched
capacitance
Unmatched pull-up and
pull-down delays.
High leakage (772nA)
IG/LP
Low leakage (337nA),
area and switched
capacitance
Almost as slow as LP mode
†
Average leakage current for two-input NAND gate (Vdd = 1.0V)
FinFET Circuit Power Optimization
32 nm PTM
FinFET
models
inFET
models
FinFET
models
(UFDG,
PTM)
Logic
Logicgate
gate
designs
designs
Delay/power
characterization in
SPICE
IG
SG
Synopsys libraries
IG/LP
•
•
•
Benchmark
Minimum-delay
synthesis in
Design Compiler
SG-mode
netlist
Power-optimized
mixed-mode netlists
LP
†D. Chinnery and K. Keutzer,
“Linear programming for sizing, Vdd
and Vt assignment,” in Proc.
ISLPED, 2005.
Construct FinFET-based
Synopsys technology libraries
Extend linear programming
based cell selection† for FinFETs
Use optimized netlists to
compare logic styles at a range
of delay constraints
Linear programming
based cell selection
SG+
IG/LP
SG+LP
SG+IG
Power Consumption of Optimized Circuits
Estimated total power
consumption for
ISCAS’85 benchmarks
Vdd = 1.0V, α = 0.1, 32nm
FinFETs
Available modes
Total power savings
• 110% arrival time (a.t.) (34%)
• 120% a.t. ( 47.5%)
Leakage power savings
• 110% a.t. (68.5%)
• 120% a.t. (80.3%)
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd/Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Dual-Vdd FinFET Circuits
• Conventional lowpower principle:
Reverse bias
Vgs=+0.08V
1.08V
– 1.0V Vdd for critical logic,
0.7V for off-critical paths
• Our proposal:
overdriven gates
– Overdriven FinFET gates
leak a lot less!
Higher Vth
1V
Leakage
current
Vin
Overdriven
inverter
Vth Control with Multiple Vdd’s (TCMS)
• Using only two Vdd’s saves leakage only in
P-type FinFETs, but not in N-type FinFETs
• Solution
– Use a negative ground voltage (VHss) to
symmetrically save leakage in N-type FinFETs
–
VddH
VddL
–
VddH
1.08V
VddL
1.0V
VssH
-0.08V
VssL
0.0V
Symmetric
threshold control
for P and N
VssH
VssL
TCMS buffer
Exploratory Buffer Design
L
VHdd V dd
L
VHdd V dd
i’
i
S1
VHss
S2
VLss
lopt
S1
VHss
S2
VLss
• Size of high-Vdd inverters kept small to minimize
leakage in them
• Wire capacitances not driven by high-Vdd inverters
• Output inverter in each buffer overdriven and its size
(and switched capacitance) can be reduced
Power Savings
Chart Title
Power
component
Saving
s
80
Dynamic
power
-29.8%
60
Total power (dual Vdd)
50
Total power (TCMS)
40
Leakage power (dual Vdd)
Leakage
power
57.9%
30
Leakage power (TCMS)
20
Dynamic power (dual Vdd)
Total power
50.4%
10
Dynamic power (TCMS)
Power (μW)
70
0
p1
r1
p2
r2
r3
r4
r5
• Benchmarks are nets extracted from real layouts
and scaled to 32nm
http://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_inse
rtion.html
Fin-count Savings
700000
Number of fins
600000
500000
400000
300000
Dual Vdd
200000
TCMS
100000
0
p1
r1
p2
r2
r3
r4
r5
Average
• Transistor area is measured as the total
number of fins required by all buffers
• TCMS can save 9% in transistor area
TCMS Extension
e
e
X2
b
X1
inv101
d
X8
nor11011
X1
b
X1
d
nor10011
X2
X2
X1
nor01100
X8
X2
inv101
c
X16
b
c
inv101
X8
X8
X4
a
X16
X4
inv101
a
X8
X16
Level:
1
b
X2
d
X16
nand01001
inv101
X2
X8
d
X1
nor00111
X4
nor10011
nor01100
nand00110
X2
X1
3
4
X2
X8
2
3
inv101
4
Level :
Delay-minimized netlist
Power : 283.6uW
Area: 538 fins
1
2
Power-optimized netlist
Power : 149.9uW
Area: 216 fins
Power Reduction (ISCAS’85 Benchmarks)
% reduction in power
90
80
% reduction in power
70
60
50
40
30
20
10
0
110%
130%
150%
ATCs
170%
190%
Power-minimized vs Delayminimized Netlists at 130% ATC
TCMS
TCMS (SingleVth
Dual-Vdd
% reduction in
dynamic power
53.3
49.8
51.4
% reduction in
leakage power
95.8
95.7
95.8
% reduction in
total power
67.6
65.3
66.3
% reduction in
Fin-count
65.2
59.5
61.6
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd/Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Orion-FinFET
• Extends ORION for FinFET-based
power simulation for interconnection
networks
• FinFET power libraries for various
temperatures and technologies nodes
• Power breakdown of interconnection
networks for different FinFET modes
• Power comparison for different FinFET
modes under different traffic patterns
Router Microarchitecture & Pipeline Stages
VC allocation
arbiters
Req
Input buffers
From source
RC
……
RC
Grant
Crossbar
.
From north
Switch
allocation
arbiters
To sink
To north
……
.
From south
RC
To south
……
.
From east
RC
To east
……
.
From west
RC
……
To west
.
Route
calculation
VC
allocation
Switch
allocation
Switch
traversal
Link
traversal
Power Simulation Flow
FinFET
model card
Logic-level
router circuits
Run UFDG
SPICE simulation
FinFET logic gate
characteristics
Fin count specification
for logic gates
Router traffic
profile
Capacitance & leakage
extraction
Router
FinFET power
power model
library
Router dynamic & leakage
power calculation
Clock/link
power model
Clock tree & link power
calculation
Router power profile
Clock & link power profile
Number of tiles
in the network
Network power
Network
configuration
Power Breakdown for SG/LP Modes
• 4X4 mesh network: 5 ports/router, 48-flit buffer/port
• Flit width = 128 bits
• Clock frequency = 1GHz
0.03
0.7
0.025
0.6
0.5
Watt
Watt
0.02
0.015
0.01
0.4
0.3
0.2
0.005
0.1
0
0
SG
Buffer
Crossbar
LP 1.2/-0.2
Arbiter
LP1.4/-0.4
Clock
Leakage
Router power breakdown
SG
Router
LP 1.2/-0.2
Link
Clk dist
LP1.4/-0.4
Driver leak
Network power breakdown
Bulk CMOS vs. LP-mode FinFETs
• Bulk CMOS simulation: 32nm predictive
technology model
• Leakage power of bulk CMOS network 2.68X as
compared to an LP-mode FinFET network
4
3.5
Watts
3
2.5
2
1.5
1
0.5
0
Bulk CMOS
Router Dynamic
LP mode (1.2/-0.2)
Link
Clk dist
Leakage
Router Leakage Power vs. Temp.
• Leakage power of SG-mode router grows
much faster with temp. than for LP-mode
• Leakage power ratio at 105oC: 7:1
0.014
SG
LP 1.2/-0.2
Leakage power (Watt)
0.012
0.01
0.008
0.006
0.004
0.002
0
25
35
45
55
65
75
Temperature
85
95
105
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd/Dual-Vth Circuits
• Architectural Impact
• Other ongoing work
• Conclusions
FinFET SRAM and Embedded DRAM
Design
• FinE: Two-tier FinFET simulation framework for
FinFET circuit design space exploration:
– Sentaurus TCAD+UFDG SPICE model
– Quasi Monte-Carlo simulation for process variation
analysis
– Thermal analysis using ThermalScope
– Yield estimation
• Variation-tolerant ultra low-leakage FinFET
SRAMs at lower technology nodes
• Gated-diode FinFET embedded DRAMs
Extension of CACTI for FinFETs
• Selection of any of the FinFET SRAM and
embedded DRAM cells
• Use of any of the FinFET operating modes
• Scaling of FinFET designs from 32nm to
22nm, 16nm and 10nm technology nodes
• Accurately modeling the behavior of a
wide range of cache configurations
FPGA vs. ASICs
•
CMOS fabrication
compatible
Nano RAM
on-chip storage
•
Run-time
reconfiguration
Temporal
logic folding
NATURE
Design
flexibility
Distributed non-volatile nano
RAMs: main storage for
reconfiguration bits
Fine-grain reconfiguration
(even cycle-by-cycle) and
logic folding
 More than an order of magnitude
increase in logic density and areadelay product
 Competitive performance and
moderate power consumption
 Non-volatility: useful in low
power & secure processing
Logic
density
•
NanoMap to map application
to NATURE
 Significant area-delay trade-off
flexibility
Conclusions
• FinFETs a necessary semiconductor evolution step
because of bulk CMOS scaling problems beyond 32nm
• Use of the FinFET back gate leads to very interesting
design opportunities
• Rich diversity of design styles, made possible by
independent control of FinFET gates, can be used
effectively to reduce total active power consumption
• TCMS able to reduce both delay and subthreshold
leakage current in a logic circuit simultaneously
• Time has arrived to start exploring the architectural
trade-offs made possible by switch to FinFETs