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LECTURE 1
NUMBER SYSTEM
Number System: - There are two types of number system used: Non-positional
number system and Positional number system:
1) Non-Positional number system: - Roman number system is a non-positional
number system. There is a symbol for each digit. E.g.: - I for 1,II for 2. This is quite
complicated due to the absence of a symbol zero.
2) Positional number system: It is widely used number system. Positional number
systems have a radix or a base. A number system with radix ‘r’ will have ‘r’ symbols.
In the decimal number system the radix is 10. It consists of 10 numbers:
0,1,2,3,4,5,6,7,8,9
In the binary number system the radix is 2. It consists of only 2 numbers: 0 and 1
Similarly, octal number system has radix 8 and hexadecimal number system has radix
16.
Decimal Number System: The number system that utilizes 10 distinct digits is known
as decimal number system. The decimal number system has a radix 10. It consists of 10
numbers: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. Each of the ten digits has a place value or
weight depending on the position. The weights are the units, tens, hundreds and so on.
For ex 1290.
Binary Number System: A number system that uses only 2 digits, 0 and 1 is known
as binary number system. These two digits are known as bits. The binary number
system has a radix 2. Computer cannot understand the decimal number system. It
understands the binary number system. The weight or place value of each position can
be expressed in terms of 2.
Octal Number system: In the octal number system, the base is 8, as there are eight
symbols (0,1,2,3,4,5,6,7) used in this system. The weight or place value of each
position can be expressed in terms of 8.
Hexadecimal Number system: In the hexadecimal number system, the base is 16, as
there are 16 symbols (0,1,2,3,4,5,6,7,8,9,A, B, C, D, E, F) used in this system.
A, B, C, D, E, F represents the decimal values 10,11,12,13,14,15 respectively.
Decimal to Binary conversion:
In this method, the decimal number is repeatedly divided by 2 and the remainder after
each division is used to indicate the coefficient of the binary number to be formed.
Binary number is derived by writing from the bottom to up.
For ex: convert 64 into its binary number.
2
64
2
32
0
2
16
0
2
8
0
2
4
0
2
2
0
1
0
So, 1000000 is the binary equivalent of 64.
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LECTURE 2
Decimal Fraction to Binary conversion:
In this method, multiply decimal number system continuously by 2 and record the carry
in the integer positions. The binary number is derived by writing from up to bottom.
For ex: convert 0.625 to binary
0.625 * 2 = 1.250 with a carry of 1
0.250 * 2 = 0.500 with a carry of 0
0.500 * 2 = 1.000 with a carry of 1
So, 0.101 is the binary equivalent of 0.625
Binary to Decimal conversion:
For ex:
Conversion of 11001 into decimal:
1*24 + 1*23 + 0*22 + 0*21 + 1*20 = 25
25 is the required decimal number.
Octal to binary conversion:
In this conversion, replace each octal digit by its equivalent three bit binary numbers.
For ex:
Convert octal number 552.47 into binary equivalent. On replacing each octal
digit by its corresponding three bits binary number, we get
(552.47)8 = (101 101 010.100 111) 2
LECTURE 3
Binary to Octal conversion:
Since 23=8, each octal digits corresponds to three binary digits. Therefore the binary
number is partitioned into group of three digits, each for its conversion into its octal
equivalents. The corresponding octal digit is then assigned to each group.
For ex:
Convert binary number 11011101.11010101 into octal.
11 011 101.110 101 01
3 3 5 6 5 1
Hence 11011101.11010102  335.6518 .
Hexadecimal to Binary conversion:
In this method, each hexadecimal digit is converted to its four digit binary equivalent.
For ex:
Convert (305.F)16 into binary.
(305.F) 16 = (305.15)16= (011 0000 0101.1111)2
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LECTURE 4
Binary to Hexadecimal conversion:
Since 24=16, each hexadecimal digit corresponds to four binary digits. So the
conversion is accomplished by partitioning the binary number into group of four digits.
For ex:
Convert (11011101.11010101)2 into its hexadecimal equivalent
1101 1101.1101 0101
13 13 13
5
Hence (11011101.11010101) 2= (DD.D5)16
Hexadecimal to Octal conversion:
In this, first convert hexadecimal number to binary and then convert it into octal.
For ex:
Convert (3FC.82)16 into its octal equivalent.
(3FC.82)16 = (0011 1111 1100.1000 0010)2
001 111 111 100 . 100 000 100
1
7 7 4
4 0 4
Hence (3FC.82)16 = (1774.404)8
Octal to Hexadecimal conversion:
In this, first convert octal number to binary and then convert it into hexadecimal.
For ex:
Convert (764.352)8 into its octal equivalent.
(764.352)8 = (111 110 100 . 011 101 010)2
0001 1111 0100 . 0111 0101 0000
1
F
4
7
5
0
Hence (764.352)8 = (1F4.75)16
LECTURE 5
Floating Point Representation Of Numbers: The floating point representation of a
number consists of two parts. The first part represents a signed, fixed point number
called the mantissa. The second part designates the position of the decimal point and
is called the exponent.
For ex the following numbers are represented in floating point representation as
follows:
1) 567800 = 5678 * 102
2) 0.00456 = 0.456 * 10-5
Here the first part or the integer part is known as the mantissa and the power of 10 is
known as the exponent.
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Floating point is always interpreted to represent a number in the following form:
M * Re
Only the mantissa M and the exponent e are physically represented in the register. The
radix R of the mantissa are always assumed.
For ex the number +1001.11 is represented in a 16-bit register as follows:
0 100111000
0 00100
Mantissa
Exponent
The mantissa occupies 10 bits and the exponent 6 bits.
A floating number is said to be normalized if the most significant position of the
mantissa contains a non zero digit. The number +0.95756 * 102 = 95.756 is normalized
because the mantissa has a non-zero digit 9 in its most significant position. This number
can be represented in an unnormalised form as +0.00957 * 104 = 95.7. This
unnormalised number contains two most significant zeros and therefore mantissa can
accommodate only three significant digits.
Arithmetic operations with floating point numbers are more complicated than
arithmetic operations with fixed point numbers.
LECTURE 6
Arithmetic Operations
Binary Addition:
Binary addition is performed in the same way as decimal addition. There are 4 cases
that occur in adding the two binary digits in any position.
1) 0 + 0 = 0
2) 1 + 0 = 1
3) 0 + 1 = 1
4) 1 + 1 = 10 ( 1 is carry )
for ex :
11 1
carry
01100111001
+ 10000111001
11101110010
Binary Subtraction:
In subtraction , it is necessary to subtract a large digit from a small digit. The rules for
binary subtraction are:
1) 0 – 0 = 0
2) 1 – 0 = 1
3) 1 – 1 = 0
4) 0 – 1 = 1 ( with a borrow of 1)
5) 10 – 1 = 1
for ex:
10000
- 00111
01101
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Complement Representation Of Numbers: There are two methods for representing
negative numbers. These are 1’s compliment and 2’s compliment representation.
1’s Compliment Representation: In 1’s compliment representation the number is
obtained by replacing every 1 by 0 and every 0 by 1.
For ex:
Binary number
1’s compliment
110011
001100
2’s Compliment Representation: The 2’s compliment representation of a negative
number is obtained by adding a 1 to the one’s complement representation of that
number.
For ex:
Binary number
1’s compliment
2’s compliment
110011
001100
001101
LECTURE 7
1’s complement subtraction:
Case a) Subtrahend is smaller than the minuend
1. Complement the subtrahend by converting all 1’s to 0’s and all 0’s to 1’s
2. Proceed as in addition
3. Disregard the carry and add 1 to the total (end-around-carry)
Example:
Perform the subtraction using 1’s complement addition of the following binary numbers
110010
- 101101
Solution:
110010

110010
-101101
+010010
-----------1000100
end-around-carry
1
---------000101
Case b) Subtrahend is larger than the minuend
1. Complement the subtrahend
2. Proceed as in addition
3. Complement the result and place a negative sign in front of the result
Example:
Perform the subtraction using 1’s complement of the following binary numbers:
1011010

1011010
-1101010
+0010101
1’s complement of 1101010
-------------1101111
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LECTURE 8
TEST
LECTURE 9
2’s complement subtraction:
Case a) Subtrahend is smaller than the minuend
1. Determine the 2’s complement of the smaller number
2. Add this to the large number
3. Disregard the carry
Example : subtract the following using 2’s complement method
1100
-1011

1100
+0101 2’s complement of 1011
-------Carry
1 0001
The carry is disregarded. Thus the answer is (0001)2
Case b) Subtrahend is larger than the minuend
Example: Subtract (1011)2 from (1101)2,
1101 
1101
-1011
+ 0101 2’s complement of 1011
-------------1110
No carry is obtained. Thus, the difference is negative and the true answer is 2’s
complement of (1110)2 i.e., (0010)2.
LECTURE 10
Signed Binary Representation:In computers, the binary numbers are represented by a
set of binary storage devices. Each device represents one bit. Since computers handle
positive and negative numbers both, so some means are required for representing the
sign of the number ( + or - ). This is usually done by placing another bit called sign bit
to the left of the magnitude bits.
A 0 in the sign bit represents a positive number and a 1 represents a negative
number.
In this kind of representation, the sign bit is treated as separate from the
magnitude bits.
7
6
5
4
3
2
1
0
Sign bit
Bit pattern representing the integer
0-positive
1-negative
Three main signed number binary codes are used. The most commonly used system is
2’s complement system.
2’s complement arithmetic:
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1) Addition in 2’s complement system: There are four possible cases:
a) Both numbers positive
b) A positive number and a negative number
c) Both numbers negative
Case 1: Both numbers positive
29+19 
+ 0001 1101(augend)
+ 0001 0011(addend)
--------------------------0011 0000(sum = 48)
----------------------------Case 2: one positive number, one negative number
39+ (-22) 
0010 0111
1110 1010
-----------1 0001 0001
--------------Carry is disregarded, so the result is 10001
Case 3: both numbers negative
-32 + (-44) 
1110 0000
1101 0100
-----------------1 1011 0100(sum =-76)
-----------------Carry is disregarded, so result is 10110100
LECTURE 11
2) Subtraction in 2’s complement
Case 1: Both positive numbers
28-19 
0001 1100
1110 1101
------------------1 0000 1001(sum=9)
Carry is disregarded
Case 2: one number positive, one number negative
39 – (-21)  39 +21
In this case both numbers will be added as it is.
Case 3: both numbers negative
-33 – (-57)  57-33
1100 0111
8
0010 0001
---------------1110 1000 (result = -24)
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LECTURE 12
LOGIC GATES
A logic gate is an electronic circuit, which makes logic decisions. Logic gates have
only one output and two or more inputs except for the NOT gate, which ahs only one
input. To make logic decisions, three basic logic circuits are used: the OR , AND, and
NOT gate. Each gate has a distinct symbol and its operation can be described by means
of an algebraic function.
OR Gate: This circuit has two or more inputs and a single output and it operates as
follows: “The output of an OR gate assumes the 1 state if one or more inputs assume
the 1 state”.
Logical Symbol of OR gate
Truth table of OR gate: It is a compact way of representing the statements that define
the values of dependent variables. In this there are two inputs named as A and B and
one output Y.
A
0
0
1
1
B
0
1
0
1
Y=A+B
0
1
1
1
AND Gate: This circuit has two or more inputs and a single output and it operates as
follows: “The output of a AND gate assumes the 0 state if any one or more inputs are 0.
It assumes the state 1 if all the inputs assume the state 1”.
Logical Symbol of AND gate
Truth table of AND gate: There are two inputs named as A and B and one output Y.
A
0
0
1
1
B
0
1
0
1
Y=A.B
0
0
0
1
10
LECTURE 13
NOT Gate: It is also known as inverter gate. This gate has only one input and one
output. It gives the output by taking compliment of the input. It means, if input is 0 then
output will be 1 and vice versa.
Logical Symbol of NOT gate:
Truth table of NOT gate: It has one input A and one output Y.
A
0000000
1
Y=A’
1
0
NAND Gate: The NAND gate is a combination of AND and NOT gates. It is a
complement of the AND gate it is indicated as AND gate followed by small circle. It is
defined as Y=(A.B)’.
Logical Symbol of NAND gate:
Truth Table of NAND gate: It is just the complement of the outputs produced in the
AND gate.
A
B
Y=(A.B)’
0
0
1
0
1
1
1
0
1
1
1
0
NOR Gate: The NOR gate is a combination of OR and NOT gates. It is a complement
of the OR gate it is indicated as OR gate followed by small circle. It is defined as
Y=(A + B)’.
Logical Symbol of NOR gate:
11
Truth Table of NOR gate:
OR gate.
A
B
0
0
0
1
1
0
1
1
It is just the complement of the outputs produced in the
Y=(A+B)’
1
0
0
0
LECTURE 14
Exclusive OR (XOR Gate): The output of the two input XOR assumes the logic 1
state is one and only one input assumes a logic state 1. This gate is made up of AND,
OR and NOT gates as shown in the logical symbol. It is defined as: Y = A’B + AB’
Logical Symbol of XOR gate:
Truth Table of XOR gate:
A
0
0
1
1
B
0
1
0
1
Y=(A’B+AB’)
1
0
0
0
Exclusive NOR gate (XNOR) Gate: The output of the two input XNOR assumes the
logic 0 state when the inputs have an odd number of 1’s. It is defined as:
Y=(A’B+AB’)’
Logical Symbol of XNOR gate:
Truth Table of XNOR gate:
A
0
0
1
1
B
0
1
0
1
Y=(A’B+AB’)’
1
0
0
1
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LECTURE 15
TEST
LECTURE 16
BOOLEAN ALGEBRA
Basic Laws Of Boolean Algebra: The following are the basic laws of Boolean
algebra:
1) Boolean Addition: The basic rules of addition of Boolean addition are given below:
0+0=0
0+1=1
1+0=1
1+1=1
2) Boolean Multiplication:The basic rules of multiplication of Boolean multiplication
method are given below:
0.0=0
0.1=0
1.0=0
1.1=1
Properties of Boolean Algebra:
1) Commutative Laws: Boolean addition and multiplication is commutative and
is given by
X+Y=Y+X
X.Y=Y.X
2) Associative Laws:
X+(Y+Z)=(X+Y)+Z
X.(Y.Z)=(X.Y).Z
3) Distributed Laws:
X.(Y+Z)=X.Y+X.Z
4) Absorptive Laws:
X+XY=X
X.(X+Y)=X
X+X’Y=X+Y
X.(X’+Y)=XY
5) Consensus Laws:
XY+X’Z+YZ=XY+X’Z
(X+Y)(X’+Z)(Y+Z)=(X+Y)(X’+Z)
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LECTURE 17
Demorgans Theorm: De morgans theorms are extremely useful in simplifying
expression in which product a sum of variables is complemented. The two theorms are:
Theorm 1: (A+B+C…….)’ = A’B’C’…….
Theorm 2: (A.B.C………)’= A’+B’+C’…..
Sum Of Products: The logical sum of two or more logical product terms is called a
sum of products expression. It is logical OR of multiple product terms. Each product
term is the AND of binary literals. For ex:
Y=AB+BC+AC
Product Of Sums: A product of sums is the logical AND of multiple OR terms. Each
sum term is the OR of binary literals. For ex:
Y=(A +B)(B+C)(A+C)
Minterm: A minterm is a special case product (AND) term. A minterm is a product
term that contains all of the input variables that make up a Boolean expression. A 2variable function has four possible combinations viz., AB, A’B, AB’ and A’B’
Maxterm: A maxterm is a special case sum (OR) term. A maxterm is a sum (OR) term
that contains all of the input variables that make up a Boolean expression. A 2-variable
function has four possible combinations, viz. A + B, A’ + B, A + B’ and A’ + B’.
LECTURE 18
Deriving SOP Expressions From Truth Table: The SOP expression for a boolean
function can be derived from its truth table by summing the product terms that
correspond to the combinations containing a function value. In the product term, the
input variable appears either in uncomplemented form if it possesses the value 1, or in
complement if it contains the value 0.
A
B
C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y
Output
0
0
1
1
0
0
1
1
Product
Terms
------A’BC’
A’BC
------ABC’
ABC
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The general expression for obtaining the output expression from a truth table in SOP
can be summarized as follows:
1) Write a product term for each case in the table where the output is 1.
2) Each product term contains each input variable in either complemented or
uncomplemented form.
3) All the product terms are then added together to produce the final expression of
the output.
LECTURE 19
Deriving POS Expressions From Truth Table: The POS expression for a boolean
function can be derived from its truth table by multiplying the sum terms that
correspond to the combinations containing a function value. In the sum term, the input
variable appears either in uncomplemented form if it possesses the value 0, or in
complement if it contains the value 1.
A
B
C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y
Output
1
0
0
1
0
1
0
1
Sum Terms
---A+B+C’
A+B’+C
---A’+B+C
---A’+B’+C
----
The general expression for obtaining the output expression from a truth table in POS
can be summarized as follows:
1) Write a sum term for each case in the table where the output is 0.
2) Each sum term contains each input variable in either complemented or
uncomplemented form.
3) All the sum terms are then multiplied together to produce the final
expression of the output.
LECTURE 20 AND 21
Karnaugh Map: K map is a graphical method used to simplify a logic equation or to
convert a truth table to its corresponding logic circuit in a simple, orderly process. The
map method gives us a systematic approach for simplifying a Boolean expression.
K map contain cells. Each cell is represented by one particular combination of
variables in product form or sum form. Cells are assembled in a n orderly arrangement
such that adjacent cell represents minterms which differ by only one variable. A 0
denotes a complemented variable and a 1 an uncomplemented form.
Number of cells in K map depends upon the number of variables of Boolean
expression. K map can be used for any number of variables.
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For 2 variable: It contains 4 cells.
For 3 variable: It contains 8 cells
For example: Represent the following Boolean Expression by K-Map
Y=(A+B)(B+C’)(A’+B’+C’)
Solution:
Y=(A+B)(B+C’)(A’+B’+C’)
=(A+B+CC’)(AA’+B+C’)(A’+B’+C’)
=(A+B+C)(A+B+C’)(A+B+C’)(A’+B+C’)(A’+B’+C’)
= M0
M1
M1
M5
M7
Now, Boolean Expression can be written as:
Y(ABC)= (0,1,5,7)
K-Map representation of the given expression is shown below:
16
LECTURE 22
ARITHMETIC CIRCUITS
Half Adder:
A half adder is an electronic device that performs the arithmetic addition of two bits. It
receives two digital inputs A and B, producing sum and carry outputs. Truth table for
half adder may be given as follows:
Input
A
Output
B
Sum (s) Carry (c)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Logic Diagram of half adder
A
S
B
C
Block diagram of Half Adder.
Full Adder:
A half adder has only two inputs and there is no provision to add a carry coming from
the lower order bits when multibit addition is required.
A full adder is a combinational circuit that can add three single bit numbers. It gives the
sum and carry output for the three input variables. It consists of three inputs and two
outputs.
17
The truth table for full adder is as follows:
Input
Output
Z
y
z
sum(s) carry(c)
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Logic Diagram of Full adder:
x
y
S
z
C
LECTURE 23
Half Subtractor: The combinational circuit that is used to perform subtraction of two
binary bits is known as half-subtractor. It has two inputs, A and B and two outputs
D(difference) and C(borrow out). It is made up of XOR, NOT and an AND gate. Its
truth table is as follows:
A
B
D
C
(Minuend) (Subtrahend) (Difference) (Borrow)
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
18
Block Diagram Of Half Subtractor:
Logic Diagram Of Half Subtractor:
Full Subtractor: A full subtractor is a combinational circuit that performs 3-bit
subtraction. It has three inputs and two outputs. . Its truth table is as follows:
An
0
0
0
0
1
1
1
1
Bn
0
0
1
1
0
0
1
1
Block Diagram Of Full Subtractor:
Cn-1
0
1
0
1
0
1
0
1
D
0
1
1
0
1
0
0
1
Cn
0
1
1
1
0
0
0
1
19
Logic diagram of full subtractor:
20
LECTURE 24
Multiplexers: Multiplexers means many into one. Multiplexing is the process of
transmitting a large number of information units over a small number of channels or
lines.
A digital multiplexer is a combinational circuit that accepts several digital data inputs
and selects one of them and transmits information on a single output line. Control lines
are used to make selection.
The Block diagram of a multiplexer with n input lines, m control signals and one output
line is as follows:
Basic Four Input Multiplexer:
Block Diagram:
Logical Diagram:
21
LECTURE 25
Demultiplexers: A demultiplexer is a circuit that receives information on a single line
and transmits this information to one of output lines. It ahs one input signal, m control
select inputs and n output signals.
Block Diagram:
Decoder: A decoder is a combinational circuit which converts binary information from
n input lines to a maximum of 2n unique output lines such that each output line will be
activated for only one of the possible combinations of inputs. It is same as
demultiplexer, with one exception that there is no data line.
3 To 8 Decoder: In this, 3 inputs are decoded into 8 outputs. Each output represents
one of the minterms of the 3 input variables.
22
LECTURE 26
Encoders: It performs the inverse operation of a decoder. It is a circuit that converts an
active input signal into a coded output signal. It has a number of input lines, only one of
which is activated at a given time and produces an m-bit output code depending on
which input is activated.
Decimal To BCD Encoder:
23
LECTURE 27
FLIP FLOPS
The logic circuits whose outputs at any instant of time are entirely dependent upon the
input signals present at that time are known as combinational circuits.
The logic circuits whose outputs at any instant of time are dependent not only
on the present inputs but also on past inputs are called sequential circuits.
Flip Flops: Bistable memory elements, used in sequential circuits to store binary
information are called flip-flops. The outputs of a digital circuit are dependent entirely
on the input circuits and previous state. If the input changes the output also changes.
The requirements for digital device to output remain unchanged even if there is a
change in the input. Such a device could be used to store a binary number. A flip-flop is
one such circuit. Thus, a flip-flop is a binary cell capable of storing one bit of
information. It has two outputs Q and Q’.
Types Of Flip-Flops: Flip-flops are of different types depending on how their inputs
and clock pulses cause transition between two states. Different types of Flip Flops are:
1. R-S Flip-Flop
2. S-R Flip-Flop
3. D- Flip-Flop
4. J-K Flip-Flop
RS Flip Flop:
It consist of two NAND gates connected back to back. We can also construct by using
two NOR gates.
1) NAND RS Flip Flop: In this flip flop, the output of a NAND gate is 0 when all of its
inputs are 1.
The input and the output possibilities for NAND gate R-S Flip Flop is shown in the
truth table:
INPUTS
OUTPUTS STATE
R
S
Q
Q’
0
0
1
1
Race condition
0
1
1
0
Set
1
0
0
1
Reset
1
1
0
1
No Change
1
0
24
2) NOR RS Flip Flop: The output of a NOR gate is 1 if all the inputs are 0.
The input and the output possibilities for NOR gate R-S Flip Flop is shown in the truth
table:
INPUTS
R
S
0
0
0
1
1
1
0
1
OUTPUTS
Q
Q’
1
0
0
1
1
0
0
1
0
1
STATE
No Change
Set
Reset
Forbidden
LECTURE 28
TEST
LECTURE 29
Clocked SR Flip Flop:
A clocked flip flop is that which changes states only in synchronization with the clock
pulse. A clocked SR Flip-Flop has three inputs, which are labeled S (for Set), R (for
Reset) and C (for Clock). The graphic symbol of the SR flip-flop is shown in the figure
below. It has two outputs Q and Q’ which is the complemented output, and it is
indicated with a small circle at the output terminal. The arrow-head in front of C is
dynamic input which means that the flip-flop responds to a positive transition, i.e., from
0 to 1 of the input clock signal.
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Block diagram of clocked S-R Flip Flop:
R
Q
CP
S
Q
1
D Flip Flop:
The D (Data) flip-flop is a modified version of the SR flip-flop. The D flip flop has
only one input called the delay input D and a clock input. It has two outputs Q and
Q’.The graphic symbol and characteristic table of the D flip-flop are shown below.
From the characteristic table we note that the next state Q(t+1) is determined from the
D input. The Q output of the flip-flop receives it’s value from the D input, every time
when the clock signal changes from 0 to 1. No input condition exists that will leave the
state of the D flip-flop unchanged.
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LECTURE 30
J-K Flip Flop :
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate condition of
the SR type becomes defined in the JK type. Inputs J and K behave like inputs S and R
to set and clear the flip-flop, respectively. But when inputs are J =1 and K =1, a clock
transition switches the outputs of the flip-flop to their complement state. The graphical
and tabular representation is as follows.
LECTURE 31
MEMORIES
Memory is used to store the data. Mainly it is of two types:
1) Primary memory or main memory
2) Secondary memory
Memories are also classified as:
1) Registers, Main memory and Secondary memory
2) Sequential access memory and Random access memory
3) Static and Dynamic memory
4) Volatile and Non-volatile memory
5) Magnetic and Semiconductor memory
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Registers:- The CPU uses a number of memory units called registers. Since, there is
a movement of the information between the various units of the computer system, so in
order to handle the process and to speed up the rate of information transfer, the
computer uses registers. Registers in CPU are used to store data temporarily during
arithmetic and logical operations. They have very low access time.
Primary Memory Or Main Memory: Primary memory is also called working
memory. Main memories are available external to the CPU to store program and data
during the execution of a program. A program and any data used by the program reside
in the main memory while the computer is working on that program. RAM and ROM
are the examples of the main memory. Computer use this memory for internal
processes.
Secondary Memory: As the storage of main memory is inadequate, then secondary
memory is used to enhance storage capabilities. The secondary memory generally
operates at a slower speed than the registers and main memory. They are used to store
large quantities of data. Hard disks, floppy disks, and optical disks are some of the devices used for mass storage.
Sequential Access Memory: It is a device that is used to access a particular memory
location sequentially i.e first block will be accessed first, then second and so on. It is a
memory device in which the access time is not constant but varies depending on the
address location. A particular stored word is found by sequencing through all address
location until the desired address is reached. It uses much less hardware. Magnetic tape
is an example of this kind of device.
Random Access Memory: The RAM is a random access memory that has both read
and write capability. RAM’s stores information can be recalled, or “remembered”.
Primary storage is usually referred as RAM because it is possible to randomly select
and use any location of this memory to directly store and retrieve data and instructions.
It is used for temporary storage.
The disadvantage of this memory is that it is volatile and will lose all stored
information if power is turned off.
Static Memory: In static memory, the content does not change with time. That is, the
stored data will remain permanently stored as long as power is applied, without the
need for periodically rewriting the data into a memory. Static memory cells uses flipsflops as the storing elements. Registers are the example of this kind of memory.
Dynamic Memory: In dynamic memory, the content change with time. That is, the
stored data will not remain permanently stored even with power applied, unless the data
are periodically rewritten into memory. Dynamic memory cells use the capacitance of a
transistor as the storage device. The capacitor must be refreshed periodically without
being discarded in order to prevent any loss of information. Semiconductor dynamic
RAM is the example.
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LECTURE 32
Volatile Memory: In this memory, if the electrical power is turned off, all information
stored in the memory will be lost. Many semiconductor memories are volatile.
Non-volatile memory: Memory units that retain the stored information even when
power is turned off are said to be non-volatile. It is permanent unless rewritten. All the
secondary memories are non-volatile.
Magnetic Memory: Memories that utilize magnetic materials are known as magnetic
memories. Magnetic memories are slower than semiconductor memories and occupy a
much greater volume. A great deal of data can be stored on a magnetic tape, disks or
drums. Magnetic memories are non-volatile. Example: Magnetic drum, Magnetic core
memories.
Semiconductor memory: Semiconductor memory is computer memory implemented
on a semiconductor-based integrated circuit. These are used as the main memory of the
computer. Examples of semiconductor memory include static random access memory
(RAM), and ROM. It is faster, smaller in size and lighter in weight. It consumes less
power compared to other type of memory devices.
Memory Structure:
Memory cells can be placed in one of the tow stable states (0 and 1). The cell has an
input data line to input and output data line to output. If the contents of a cell is to be
read, read control signal is sent, and if the contents of the cell are to be written, then the
write control signal is sent via write line.
A memory unit is a collection of storage cells together with associated circuits need to
transfer information in and out of the device. Data is stored in form of groups of bits
called words. Each word is stored in a location called address. The capacity of a
memory unit is usually stated as the total number of bytes that it can store.
29
Communication is done through data input and output lines, address lines, and control
lines that specify the direction of transfer.
This diagram has n data input lines and n data output lines. The k address lines specify
the particular word. It has tow control inputs: Read and Write.
LECTURE 33
TEST
LECTURE 34 AND 35
REVISION