Download Basic Logic Devices

Logic Families
Characterizing Digital ICs
Digital ICs characterized several ways
Circuit Complexity
Gives measure of number of transistors or gates
Within single package
Four general categories
SSI - Small Scale IC
< 12 gates or so
MSI - Medium Scale IC
< 100 gates or so
LSI - Large Scale IC
< 1000 gates or so
VLSI - Small Scale IC
> 1000 gates or so
Main Characteristics
Voltage Levels
Input
Output
Low
High
Supply
Noise Margins
Based upon voltage levels
Propagation delay
Low to High
High to Low
Setup and hold times
Storage devices
Fan In and Fan Out
Based upon
Input sink capability
Output drive capability
Power dissipation
Circuit Technologies and Topologies
Describes
Process used to implement devices
Input and output structure of the device
Four general categories
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TTL
Transistor Transistor Logic
Bipolar transistors on input and output
NPN, PNP, diodes
Input
Diode
Transistor BE junction
Output
Typically two transistors
Configured in totem pole arrangement
ECL
Emitter Coupled Logic
Bipolar
Input
Configured in non-saturating differential pair
Output
Emitter follower type of configuration
Logic done in emitter circuitry rather than collector
High speed
MOS
Metal Oxide Semiconductor Field Effect Transistors
MOS transistors on input and output
N MOS
N Channel transistors
Operating in enhancement mode
Less common as single technology in new designs
Input
Gate
Output
Typically two transistors
Configured in totem pole arrangement
Upper configured as depletion mode load
P MOS
P Channel transistors
Operating in enhancement mode
Rarely used alone in new designs
Input
Gate
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-V
Output
Typically two transistors
Configured in totem pole arrangement
Upper configured as depletion mode load
C MOS
N - P Channel transistor pairs
Operating in enhancement mode
Input
Gate
Output
Two transistors
Configured in totem pole arrangement
Upper P channel
Lower N channel
BICMOS
Both CMOS and Bipolar transistors
Bipolar mainly on output
Used for speed
Works well for combining
Analog and digital circuitry on same substrate
Circuit Topology
Output Stages
Three different types
Normal
Active drive logic both high and low states
TTL
CMOS
Open Collector / Drain
Active drive logic low state passive pull up to high state
Used in applications where
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Wire OR bus
Sink large amounts of current
Lamp
LED
Relay
TTL
CMOS
Tristate
Two states
Behave as Normal
Active drive logic low and high states
Third state
Both devices turned OFF
Output floats
Tristate mode
Selected by control line
Typically
Low enables drive
High disables
Used in applications where
Bus configurations
Bus usually pulled high passively
Size of pullup determined by
Logic family
CMOS - higher value
TTL - lower value
Desired bus speed
Input Stages
TTL
Two forms
Multiple emitter
Diode
Multiple Emitter
Input transistor behaves in interesting way
When any input low
Q1
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Q1
Q2
Emitters act as emitters
Operates in forward direction
Turns on to ground
Q2
Turns off
When all inputs high
Q1
Emitters act as collectors
Operates in reverse direction
Supplies current/voltage to Q2
Q2
Turns on
Diode Input
Diode inputs work like traditional DTL
Both inputs High
Q2 turns on
Any input low
Q2 turns off
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CMOS
Input structure
1 N channel and 1 P channel
For each input
Circuit above shows "AND" configuration
Reverse configuration for "OR" function
Logic Families
Continually changing as technologies improve
Common
Bipolar
LS
Low Power Schottky
AS
Advanced Schottky
ALS
Advanced Low Power Schottky
54 / 74
Military / Commercial
CMOS
HC / HCT High Speed CMOS TTL Compatible
4000
Typical numbering
A Look at the Real World
Logic gates and circuits always work perfectly on paper
Let’s now look at some of the things we encounter
When working with real parts
Voltage Levels
TTL or CMOS we have supply voltage of +5 VDC
ECL will use a negative supply -5.2 VDC
Denoted
Vcc - Bipolar
Vdd - MOS
Vee - ECL
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Logic Levels
On paper we deal with logical 0 or logical 1
In physical parts
Represented by different voltage levels
Most typically
Logical 0 - 0 volts
Logical 1 - +5 volts
Newer logics
Logical 0 - 0 volts
Logical 1 - +1.5 or 3.0 volts
We refer to
Logic 0 as low
Logic 1 as high
Problem
When dealing with real parts
Logic high never exactly 5.0 v
Logic low never exactly 0.0v
If logic
High gets too low
Interpreted as logic 0
Low gets too high
Interpreted as logic 1
Max and Min Values
For TTL family we specify
Min logic high voltage 2.0 volts
Lower either interpret as logic 0 or
Don’t know
This can be a problem
Max logic low voltage 0.7 volts
Higher either interpret as logic 1 or
Don’t know
This can be a problem
Nominal Values
We rarely work with parts at max voltages specify
Typical
Nominal values
Must consider when doing worst case design
Typical logic high voltage 3.5 volts
Typical logic low voltage 0.2 volts
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Noise immunity
Difference between
Min (Max) values and nominal values
Gives noise immunity
Consider if
VOH from a gate is 3.5 v
VIHmin is 2.0 v
VOH - VIHmin = 1.5v
What this says is we can have 1.5 v of low going noise spike
Before it’s interpreted as a logic 0
Consider if
VOL from a gate is 0.2 v
VILmax is 0.7 v
VOL - VILmin = 0.5v
What this says is we can have 0.5 v of high going noise spike
Before it’s interpreted as a logic 1
Observe
Based upon typical values have
1.5 v of high noise immunity
0.5 v of low noise immunity
TTL
Fan
In
and
Fan
Out
Noise Margins
5.0
3.5 VOHtyp
CMOS
4.5 VOHtyp
5.0
Noise Margins
2.4 VOHmin
2.7 VOHmin
2.0 VIHmin
2.0 VIHmin
0.4 VOLmax
0.7 VILmax
0.5 VOLmax
0.8 VILmax
0
0
0.2 VOLtyp
Amount of current a device can source or
sink
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0.0 VOLtyp
Limited
Such limits determine how many other devices
Can be driven
Fan Out
Measure of output drive capability
Specifies how current device can
Supply to other devices in logic high state
Sink from other devices in logic low state
Fan In
Measure of device input requirements
Specifies how current device
Supplies to other devices in logic low state
Sink from other devices in logic high state
Analyzing
Let’s specify drive capability for typical gate
IOL
8 mA
@ VOL = 0.5VDC
IOH
-400 A @ VOH = 3.4 VDC
IIL
-400 A @ VIL = 0.4VDC
IIH
20 A
@ VIH = 2.7 VDC
For such analysis Ohm’s law must hold
If high drive required to supply additional current
Voltage must drop
If low drive required to sink additional current
Voltage must increase
For this device
Logic 0 State
When output at logic 0
Can sink 8mA
When input at logic 0
Sources -400 A
Thus
Can sink current from 20 devices
Logic 1 State
When output at logic 1
Can supply -400 A
When input at logic 1
Requires 20 A
Thus
Can source current to 20 devices
Thus fan out for device is 20
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Can connect up to 20 devices
Can support up to 20 unit loads
Observe on input
Device typically requires
20 A for logic 1
-400 A for logic 0
Call this a unit load
State fan in is 1 unit load
If values double
State fan in is 2 unit loads
Increasing Drive Capability
Are occasions when require more drive capability
Handle several ways
Buffers / Drivers
Such devices designed for purpose of driving
Often open collector configuration
High sink - intended to drive low
Such devices tend to be slower
Parallel Devices
Another common technique
Connect several standard devices in parallel
Assumption
If one device will sink/source x mA
Then n devices will sink/source nx mA
Is belief valid?
Let's consider following circuit configuration
A
B
Let's put a step input into the circuit
input
device A
device B
tpd1
tpd2
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From the diagram we see
Propagation delay through two devices is different
If device A faster that device B
When A tries to go high B still (partially) off
Tries to hold signal low
Two devices fighting
Conflict in two logic states can potentially damage part
May not occur immediately
More often will appear as premature failure
Problem
In any random sample of parts
Have no guarantee of device speed
Hand selecting parts not solution
Possible solution
If paralleled devices in same package
Thus on same small portion of die
Prop delays much closer than on arbitrary parts
Still real world parts and will be different
Unused Inputs
Gate inputs should always be defined
Never let them float
Problem with TTL
Larger problem with CMOS
Floating input
Has parasitic capacitors connected
To ground
Surrounding circuitry
Such capacitors
Charge up to threshold voltage of device
Cause device to change state
Uncontrolled or unknown ways
Defining Inputs
Direct connection to VDD, VCC, VSS permitted
Both CMOS and LS TTL
Direct connection to VDD, VCC, prohibited
Standard TTL
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Must be done through pullup
Preferred method
Connect to VCC or VDD
Through pullup resistor
CMOS
10 - 100K
Since input current negligible size insignificant
LS TTL
Remember IIH and IIL
Must calculate current to ensure voltage drop not too large
With such scheme
Can connect to ground for test
Only works if several inputs not connected to same pullup
Unused Gates
Similarly must define inputs to unused devices
Goal to place device in low power state
Devices left undefined
Can enter state in which all internal devices conducting to ground
Basic Logic Devices
Classified according to function
Will include
SSI - Small Scale Integrated circuits
MSI - Medium Scale Integrated Circuits
Combinational Logic
SSI Devices
Basic Logic Gates
Comprises basic logic gates
AND / NAND
OR / NOR
Invertor
Exclusive OR / NOR
Bus Drivers and Transceivers
Serve two main purposes
Provide high current drive
Perform multiplexing function
Output configuration
Open collector
Tristate
Inverting / Noninverting
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If tristate output configuration
Control may be high or low
TTL Configuration
Driver
Transceiver
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ENB
CMOS
ENB
Configuration
ENB
Driver
Transceiver
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ENB
MSI Devices
Encapsulate standalone piece of functionality
Types
Arithmetic circuits
Data formatters and convertors
Selection devices
Simple communication circuits
When we choose to use MSI parts
Give up some flexibility
Must use features the manufacturer has designed in
Top Level View
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Can represent as a box
Signals
Inputs
Input
Data input signals
Output
Data output signals
May or may not be same a input signals
Control
Provide timing reference
Clock or strobe
Selection
Select
From alternate input sources
Different outputs
Enable / Disable
Inputs or Outputs
Outputs
Control
Data Encoding and Decoding
These are simply combinational logic problems
We work with truth table
Identify input patters
Corresponding output patterns
Design logic to do mapping
Control
Usually these devices
Have some form of selection or enable
Output enable / disable
Perhaps tri state control
Output
Logic level, tristate, or open collector
Logic level may be
High true
Output high when desired logical condition satisfied
Low true
Output low when desired logical condition satisfied
Let’s consider a couple of examples
Encoders
Devices that
Accept one set of signals
Encode them into second set
Generally go from 2n inputs to n outputs
8 Line to 3 Line Priority Encoder
This device
Inputs
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Has 8 data inputs
Outputs
0
3 data outputs
1
2
2 Output for cascading
3
Controls
4
5
1 Input enable
6
Function
7
Map each input to encoded
EI
output pattern
Output pattern based upon
priority of input
Assume 7 highest and 0 lowest
Input lines
5-7 inactive
4 active
0-3 don't care
Output code
A0-A2  011
If 5 goes active
A0-A2  010
EI is logical 0
A0
A1
A2
E0
GS
Decoders
Opposite of encoders
Devices that
Accept one set of signals
Decode them into second set
Generally go from n inputs to 2n outputs
3 to 1 of eight Decoder
This device
Inputs
Has 3 data inputs
Three inputs represent 8 combinations
As reflected in 3 variable truth table
Outputs
8 data outputs
Controls
2 active low
1 active high
Usually these are low true
Function
Map each input combination to one of 8 outputs
Corresponding output to be logical 1 when
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A
B
C
Output = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
O0
O1
O2
O3
O4
O5
O6
O7
Enable is satisfied
A
Data Selection
B
Data selection devices permit one to select from
C
Several alternate data sources
G1
G2A
Usually because of pin limitations
G2B
Number of choices limited to 2
D00
Combine devices to increase number of
D01
alternatives
D10
4 Bit Data Selector
Inputs
D11
Has 8 data inputs
D20
Grouped as 2 sets of 4
Outputs
D21
4 data outputs
D30
Controls
2
D31
Enable
Select Device
Logical 0 active
Select
Selector
Select one of 2 input sets
~enable
Function
Cause one or the other of the 2 input data sets to
Appear on output
When enable is logical 0
Selector = 0
Selects one group
Selector = 1
Selects other group
1 of N Data Selector - Multiplexer
We can build a variation on the above device
Multiplex number of data bits onto single line
Inputs
Has 4 data inputs
Outputs
1 data output
Controls
3
Enable
Select Device
Logical 0 active
2 Selectors
Select one of 4 input bits
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0
1
2
3
4
5
6
7
D0
D1
D2
D3
D0
Function
Cause one of the four input data bits to
Appear on output
Based upon selector pattern
When enable is logical 0
D1
D2
Storage Elements
D3
Two basic types
Latch
Flip flop
Distinguished by clocking scheme
Latch
Control signal
When control signal
Active
Output tracks input
Inactive
Output holds last value
Flip flop
Control signal called clock
Input signal stored on output
Clock transitions from
High to low
Low to high
Types
D, JK, SR, T
Uses
Basic Component
Use flip flops to build more complex sequential circuits
Will cover these shortly
Registers or Latches
Use either as
Register
Latch
Will hold data or address type information
Registers or Latches
Packaged in 4 or 8 bit sizes
May have set of control lines
Select or address
Enable or disable tristate outputs
Permit use in bus type applications
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A
B
Enable
Dout
Counters
Collection of flip flops
Configured to count transitions on input line
May count
Up, down, or both
Asynchronously or synchronously
Async
Each element changes with respect to another element in the collection
Sync
Each element changes with respect to a common signal
May have
Carry in and / or carry out
Permit devices to be cascaded
Clear / Preset
Constrain device into
Reset state
Known state
Synchronous or asynchronous
Typical configurations
BCD
HEX
Shift Register
Collections of flip flops
Configured to store collections of bits
Shift the bits
Left, right, or selectable left/right
Shift by one position with each clock
Inverted Logic
We often will use to indicate active state of signal
In large systems clarifies intent of designer
Let's examine on simple gates
Invertor
Observe the invertor truth table and function
If input
A get ~A out
~A get A out
We use the bubble to indicate the two different forms
With bubble on input
Implies 0 in gives 1 out
With bubble on output
Implies 1 in gives 0 out
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NOT
a
0
1
~A
~a
1
0
A
AND
Observe the AND truth table and function
We have
3 zero terms
1 one term
Writing logic equation for 1 term
AND
AB
0 0
0 1
1 0
1 1
C
0
0
0
1
C=1=A*B
Writing the equation for the 0 term
~C = 0 = ~A~B + ~A B + A~B
= ~A (~B + B) + ~B ( ~A + A)
= ~A + ~B
Observe we now have a OR type function
If A is 0 or false or if B is 0 or false
Then C is 0 or false
If we are to express this using bubbles to indicate inversion
First the basic logic function is an OR so we draw that
Then we want 0’s on the inputs and the output
~A
~B
~C
Thus our two symbols now look like
A
B
Thus the
AND of logical 1’s
OR of logical 0’s
~A
~B
C
~C
gate implements
OR
Observe the OR truth table and function
We have
1 zero term
3 one terms
Following same reasoning as with AND
OR
AB
0 0
0 1
1 0
1 1
Thus our two symbols now look like
~A
~B
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~C
C
0
1
1
1
C
A
B
Thus the gate implements
AND of logical 0’s
OR of logical 1’s
NAND
Observe the NAND truth table and function
We have
3 one terms
1 zero term
a
0
0
1
1
b
0
1
0
1
a
0
0
1
1
b
0
1
0
1
AND
NAND
a*b
0
0
0
1
~(a * b)
1
1
1
0
OR
NOR
a+b
0
1
1
1
~(a + b)
1
0
0
0
Thus our two symbols now look like
A
B
~C
~A
~B
C
Thus the gate implements
AND of logical 1’s
OR of logical 0’s
NOR
Observe the NOR truth table and function
We have
1 one term
3 zero terms
Thus our two symbols now look like
A
B
C
~A
~B
Thus the gate implements
AND of logical 0’s
OR of logical 1’s
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C