Download Varactor Topologies for Adaptivity with Improved Power Handling Linearity and

Varactor Topologies for RF Adaptivity with Improved Power Handling
and Linearity
K. Buisman, C. Huang, A. Akhnoukh, M. Marchetti, L.C.N. de Vreede, L.E. Larson*, and L.K. Nanver
Department of Microelectronics, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT
Delft, The Netherlands, *University of California at San Diego UCSD, La Jolla, CA 92093, USA.
To facilitate use of these novel components in linear
adaptive wireless applications, flip-chip compatible varactor
components have been realized with integrated biasing
networks and a MIM capacitor in the RF path to decouple the
capacitance tuning from external DC bias conditions.
Abstract-Ultra linear silicon-on-glass varactor topologies with
improved power handling and linearity have been realized. The
resulting components include integrated bias networks and
provide excellent low-loss performance for large capacitances
(e.g. C=2OpF Q>100 at 2GHz with V,Ot=2V). Using a novel center
tap circuit the linearity has been improved for narrowband twotone signals yielding measured IIP3V values above 75V for tone
spacings >1OkHz. By implementing two varactor stacks in series
with integrated bias networks the power handing improves 4x,
while the IIP3V doubles. The resulting devices can be used as
flip-chip components enabling linear adaptive wireless
applications.
Index Terms - Adaptive systems, distortion, nonlinearities,
II. VARACTOR DESIGN CONSIDERATIONS
Although varactors have been around for decades and antiseries diode structures are used in oscillators or even, recently,
for smart antennas [8], no commercially available varactor
technology is currently suited to fulfill the high demands for
wireless applications requiring low-distortion operation,
Q>100 at 2GHz for capacitor values larger than lOpF and high
capacitance tuning range. For this reason, a dedicated siliconon-glass varactor technology was developed for these
applications at Delft University of Technology [7].
A. Linearity
tuners, varactors.
I. INTRODUCTION
Next-generation wireless systems, such as multi-mode
transceivers and "cognitive radios," require adaptive circuits
like tunable filters and matching networks to enable frequency
band and mode switching. To enable these adaptive circuits,
researchers have focused on the implementation of very high
performance varactors. These devices require a high quality
factor, linearity, capacitance density, power handling and low
cost. Potential varactor candidates currently under
investigation are based on semiconductor diodes, MEMS [1]
and variable dielectrics (e.g. BST [2]). Although the MEMS
and variable dielectric approaches potentially provide superior
linearity and Q, the varactor approach provides a high
capacitance density, fast tuning and high reliability. Recent
work showed that by using silicon-on-glass technology [7],
the loss of the substrate, the series resistance of the buried
layer and the need for finger structures can be eliminated,
yielding varactor devices with a very compact layout and high
Q at 2GHz for large capacitance values [4]. In addition, by
using dedicated varactor topologies with a proper selection of
the varactor doping profile [3]-[5] high linearity for large tone
spacing was reported for both individual components as well
as for integrated tunable matching circuits [6]. In this work we
report on further improvements in the effective capacitance
tuning range, power handling and linearity improvements for
signals with narrow tone spacing. These improvements are
supported with analytical considerations and extensively
verified by measured data which demonstrated excellent
device performance in terms of linearity and quality factor.
1-4244-0688-9/07/$20.00 C 2007 IEEE
Since varactors are non-dissipative elements, we will
qualify their linearity by considering the third-order
intermodulation and fundamental current through the varactor.
The extrapolated intercept of the currents as a function of the
applied two-tone RF voltage yields the third order-intercept
voltage IIP3V. Note that this quantity is independent of the
operating frequency as well as capacitance value and is
therefore a very suitable linearity measure for a given varactor
technology. To develop analytical relations for the varactor
linearity of the topologies of interest we first consider the
classical capacitance-voltage behavior of a varactor given
by, C(V) = K/(0 + V) where 0 is the built-in potential of the
diode, V is the applied voltage, n is the power law exponent of
the diode capacitance, and K is the capacitance constant. For a
diode power law exponent of n=0.5 the anti-series varactor
configuration of Fig. l(a) exhibits basically no distortion [3],
provided that the center-tap impedance is significantly higher
than the impedance offered by the varactors CA and CB for all
frequency components present in the circuit. Note that for a
two-tone signal this requirement includes the base-band
mixing product at (f2-f1) which will appear at the center tap
node. When the tone spacing (Af) approaches zero, the
reactance of the varactor diodes for this frequency component
rises with no bound, consequently the center tap impedance
should be infinite. In practical situations however, the center-
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than the difference frequency. In addition, to maintain good
linearity, the varactor diodes should not become forward
biased nor exceed the diode voltage-breakdown conditions
during the RF signal cycle.
tap impedance is finite and distortion for signals with a low
tone-spacing will occur.
To improve the impedance level of the center-tap
connection an anti-parallel diode pair was proposed (Fig. 1(b))
[9]. Note that such a configuration provides extremely high
center-tap impedance provided that no DC current is flowing.
5.103'
CmIm I
CA
GB
.1 x DFV
IP3 Limited by CD
CY)
0-
CB
IP3
inproverenit
due to center
102
tap diodes
Resistor bias
(a)
(b)
1
2CO2 (2CO + CD )4
C
VCENTER) CD
-
10
10°
10"
10
Tone spacing Af (Hz)
Simulated IIP3V single varactor and (multi)-DFVS
When considering the anti-series connection of two
identical uniformly doped varactor diodes under low RF
power and reverse biased operation, the applied RF voltage
will split almost equally over the individual diodes. However,
at high power levels, the diode capacitances will be modulated
by the RF signal, and the voltage distribution between the two
diodes will not be exactly equal. In practice, this is not a
problem, since the largest RF voltage will be across the
smallest capacitance, which is offered by the most strongly
reverse biased diode. With the above consideration in mind, it
is clear that the voltage handling capabilities of the varactor
stack can be improved by stacking multiple anti-series
varactor diode pairs (Fig. 3). The major penalty for this action
is a larger device area for a given capacitance (roughly four
times the area for each doubling of the number of varactor
diodes).
(1)
(2)
This illustrates the importance of low parasitic capacitances
for the anti-parallel diode pair and the physical layout of the
anti-series configuration. Finally, for a resistive center-tap
configuration, the 3dB corner frequency for the high tone
spacing regime where the linearity starts to approach the ideal
distortion free operation (infinite IIP3V) can be expressed as:
Oi+V
|b CENTER
3
Af
t Si~~~Sngle diode
B. Improving the Power Handling Capabilities
where C0 is the zero bias capacitance, which can be
approximated, for the uniformly doped case (n=0.5) and for
small values of CD as:
IIP3V
fc-
A Soner
Fig. 2.
configurations, featuring two, four and eight anti-series diodes, using
a two-tone test as function of the tone spacing (fC=lGHz, CO=lOpF,
Vcenter =5V, n=0.5, CD=O.lpF, e-lV, Rcenter=lOOkQ ).
Fig. 2 shows the resulting linearity of the configurations of
Fig. 1(a) and Fig. 1(b). Three distinct regions of operation are
found, namely: very low tone spacing, where the center-tap
impedance is not effective, yielding an AC short for the base
band component with an IIP3V level given by
IIP3V 8Q(+ VCENTER ) . For the configuration of Fig. 1(b) at
moderate tone spacing the anti-parallel diodes are effective but
their zero-bias capacitance CD limits the effective center-tap
impedance yielding a rather constant IIP3V value, given by:
V3C12CD (CD + 4COCD2 + 6CO2CD + 2Co )
--
10o
Fig. 1. (a) Low-distortion anti-series diode configuration with
resistor bias including MIE capacitor. (b) Low-distortion anti-series
diode configuration with resistor and anti-parallel diode (APD) bias.
IIP3V=
2 x DFVS
resistor bias
103
RCENTEF
VCENTER
4x DFVS
Anti-parallel diode
4V
0
2zrC O R CENTER
3
Fig. 3. Multi-varactor stacks in series to lower the RF voltage per
diode and consequently improve the voltage handling and tuning
range capabilities.
In Fig. 2 we observe that the distortion-free varactor stack
(DFVS) performs much better than the single varactor in
terms of linearity; however, the best results are obtained when
the cut-off frequency of the dc bias network is much lower
The reduced voltage swing per diode in this multi-stacked
configurations directly benefits the linearity. This is illustrated
320
are flip-chip compatible with their footprints given in Fig. 5.
The related Q factors of a -2OpF DFVS and 2xDFVS
(effective capacitance also -2OpF) configuration with /
without MIM capacitor are presented in Fig. 6. Note that these
are scaled versions of the ones given in Fig. 5. The footprints
of these experimental structures can be reduced by simplifying
the layout of the integrated bias network.
in Fig. 2 where the IP3V is given for a single diode, a DFVS,
a multi-DFVS configuration with four anti-series diodes (as
given in Fig. 3) and a multi-DFVS configuration featuring
eight anti-series diodes. Fig. 2 shows the exact doubling of the
IIP3V, at very low tone spacing, for each halving of the RF
voltage per diode when utilizing multi-DFVS configurations.
Also the requirement on the high center-tap impedance for a
lower tone-spacing is somewhat relaxed, since this impedance
is kept constant, while the capacitance doubles to keep the
same effective capacitance.
The use of multi-DFVS configurations also affects the
effective capacitance tuning ratio, i.e. the difference between
the minimum and maximum capacitance for a given RF level
without forward biasing or exceeding breakdown. The
improvement in tuning range of these multiple varactor stacks
for higher applied RF voltages is illustrated in Fig. 4.
T
(d)
(C)
Fig. 5. Microphotographs of the 2.3pF varactor stacks used in the
linearity measurements (a) 2xDFVS (b) 2xDFVS with MIM
capacitor (c) DFVS with MIM capacitor and (d) DFVS.
N =4.10 UcMVNGcenter ma x-20V
Silicon: Q=156,GaAs: Q=394
0
10
5
VRF
250
I
D
DFVS
15
2X
DFVS
-
200
20
DFVS
150
Fig. 4. Calculated maximum effective capacitance tuning ratio for
the uniformly doped multi-stacked DFVS configuration, featuring
two, four and eight anti-series diodes, (Nd=2.1IO" and Nd=4.1016) as
function of applied RF voltage.
DFVS+MIM
a
]UU
2x DFVS+MIM
50
In this figure we have assumed for simplicity a uniform
voltage division over the diodes, while VRF represents the
applied RF voltage to the whole varactor stack. Note that
GaAs based varactors have a Q advantage over silicon due to
the higher mobility, and provide limited improvement in
tuning range over silicon for a given uniform doping
concentration of the varactor. The control voltage of these
multi-varactor stacks is constrained by the breakdown voltage
of a single varactor and in these cases limited to -20V (GaAs:
-25V) and -30V (GaAs: -40V) for Nd=4. 1016 and Nd=2. 1016
respectively.
6
8
10
V,4
BIAS
Fig. 6. Measured deembedded quality factor at 2 GHz of 2OpF
flip-chip compatible DFVS and 2xDFVS devices with and without
MIM capacitor versus bias voltage.
-2
0
2
B. Linearity measurements
Narrow tone spacing, In order to test the narrow tone spacing
linearity, a two-tone test (fc=2.14 GHz) was performed on a
DFVS and a multi-varactor stack (2x DFVS) using 50Q twoport test conditions. For the calibrated power measurement of
all frequency components of interest, we used the system of
[10]. Fig. 7 shows the measured IM3 components for a DFVS
with 8OkQ center tap impedance, a DFVS with anti-parallel
diodes in the center tap and a double stacked DFVS
III. EXPERIMENTAL RESULTS
A. Qfactor measurements
Both DFVS as well as double-stacked DFVS structures with
integrated biasing networks and optional MIM decoupling
capacitance have been realized in the silicon-on-glass
technology using a uniform doping of 4. 1016 cm3. The devices
configuration with anti-parallel diodes for biasing. The
devices have been measured as a function of power for a tone
spacing of 1OOkHz. Note the dramatic linearity improvements
when introducing the anti-parallel diode configuration as well
the double stacking of the DFVS. In Fig. 7(b) the power level
321
required to reach an IM3 level of -6OdBc is indicated as a
function of bias. Clearly, for low tone spacings an
improvement can also be seen for increased reverse bias, as
implied by the theory. Furthermore the multi-DFVS can
withstand higher power levels (-6dB more) for a given
distortion level and biasing.
Large tone spacing, Fig. 8 plots the measured and simulated
IM3 components as function of tone-spacing at a power level
of 2ldBm. The multi-stack clearly offers a superior
performance over the DFVS and the results match the theory
quite well. Note that the presence of leakage currents will
determine the lower boundary of the linearity improvement for
narrow tone-spacing by the anti-parallel diode configuration.
As predicted by theory for larger tone-spacings the linearity
further improves and cannot be measured by our equipment.
~~~anti-parallezI diodes +
>t
.
~~~bias i-esistorm
IV. CONCLUSION
Improved ultra-low distortion varactor topologies with
integrated bias networks have been presented for enabling RF
adaptivity in future wireless applications. By improving the
center tap circuitry, excellent linearity was achieved not only
for large tone spacing, but now also for very narrow tone
spacing. The use of multiple stacked anti-series varactors
further improves the voltage handling, linearity and
capacitance tuning range. Experimental data shows
remarkable performance in Q factor, linearity and power
handling. It is our expectation that these improved, costeffective components will dramatically impact the
performance of future adaptive wireless systems.
0
I-,
7,5
S~~~~
IM3high
.1
innt
/
~~~~o
11\31ow
-- nois Lfloor- simulation
/
_1
-
2xE )DFVS
{
/
/
-90
18
1
(a)
33
Applied
23
power
28
(dBm)
33
11
I
m
xDFVS
28
a
S'
0
",A-.A
23
r,
a,
-5I18
-Qa
el
k
--"'-anti-parallel diodes +
bias resistor
ACKNOWLEDGEMENT
"i
t- bias resistor
The authors acknowledge STW, Philips and NXP for
supporting this project. Special thanks goes to T.L.M.
Scholtes and H. Schellevis of DIMES, TU Delft, for
processing the silicon-on-glass wafers.
1
8
10
8
4v center6
Fig. 7. Narrow tone spacing linearity testing (f,=2.14 GHz,
Af=iOOkHz) of DFVS configurations with a purely resistive center
tap (Rcenter=80k), a center tap connection with resistor and antiparallel diodes, and 2xDFVS with resistor and anti-parallel diodes.
(a) Measured and simulated IM3 as function of power (Veenter=4V).
(b) Measured contours of applied power, resulting in -6OdBc IM3 as
function of Vcenter.
2
0
(b)
'
-110
KNoise Floor
cUaco
2xoFVSX
<
REFERENCES
[1]
J. T. M. van Beek, et al., "High-Q integrated RF passives and micromechanical capacitors on silicon," BCTM2003, Toulouse, France, Sep.
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diodes," Journal of Solid-State Circuits, vol. SC-10, issue 1, pp. 47-55,
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[8] Q. Han, et al., "Harmonic distortion suppression technique for varactorloaded parasitic radiator antennas," IEICE Trans. on Electronics, vol.
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[10] M. Spirito et al., "A novel active harmonic load-pull setup for on-wafer
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pp. 1215-1218.
765
I/
242
-90- /-
242
r.eiti-paraIleldiodel +
=bias resistor
7AV
-6 ---_._.._I__
bias resistor
Simulation
(}Sf Sim. including leakage
5
XAOMeasrmn|
-5G
1E2
E6
1E4
Tone
43
spacing
24
E8
(Hz)
Fig. 8. Simulated (lines) and measured (points) IM3 and IIP3 for a
DFVS with and without anti-parallel diodes and a double 2.3pF
DFVS with resistor and anti-parallel diodes as function of tonespacing Af; Vcenter=5V, f =2.14 GHz, applied power: 2 1dBm.
322