Download Graduate Category: Engineering and Technology Degree Level: Ph.D Abstract ID# 1016

Graduate
Category: Engineering and Technology
Degree Level: Ph.D
Abstract ID# 1016
High Frequency Noise Immune Low-Dropout Regulator and Active Loop Filter for a Low Jitter and Power Phase-Locked Loop
Gyunam Jeon Faculty Advisor: Yong-Bin Kim, High Performance VLSI Research Laboratory
Abstract
Supply Noise Mitigation Techniques
This paper presents high frequency noise immune low dropout
(LDO) regulator and active loop filter (ALF) for a low jitter and
power phase-locked loop (PLL) on 110nm CMOS technology and
with 1V supply voltage. The high frequency noise of supply
voltage is regulated by low-dropout (LDO) regulator. Other
noises generated by each PLL block are filtered
by ALF. Therefore, high frequency noise of the VCO's control
voltage is eliminated and stable control voltage decreases PLL
jitter. The LDO regulator provides 0.8V output, -83 dB PSRR with
PLL load, 0.578mW power consumption, and 99.8% current
efficiency with 40mA load current. As a result, the jitter of the
PLL with LDO regulator and ALF improves from 44.9ps to 4.6ps.
Simulation Setup and Results
I. Low-Dropout Regulator
Vin
Vref
M20
EA
MP
Vout_LDO
Vin
M21
CZ
Vref
EA
•
M22
MP
Vout_LDO
M21
CZ
M23
•
•
Rfb1
•
Error amplifier
zero compensation
M23
Rfb1
CL
Error
amplifier
gain
compensation
Rfb2
•
LDO regulator provides a clean power supply
voltage to the VCO
The compensation stages are cancel out the
supply noise
A folded cascode amplifier provides high swing
(2 2·VDS(sat) < Vout(max) <VDD - 2VDS(sat)) and high gain
(71dB) to reduce supply noise
The LDO regulator provides -83dB of PSRR
and load current from 100μA to 40mA
Vout_LDO supplies all VDD of each block in
PLL
CL
Error
amplifier
gain
compensation
Error amplifier
zero compensation
M20
M22
Rfb2
C1
Vin
Current Starved VCO
VVCO_ctrl
R
R
C2
C2
6.37us
AF and LDO regulator with CSVCO
•
•
Supply noise with 100mVpk-pk at 100kHz is injected to the Transient response of the LDO regulator
unregulated VDD of the LDO regulator.
The regulated VDD(0.8v) supplies all other PLL circuits
PSRR enhanced LDO regulator
Keywords – Phase locked loop, active loop filter, Low Dropout
regulator, supply noise, current-starved voltage controlled
oscillator
PLL: Supply Noise Migration
AC response of the LDO regulator
4.6ps
How does supply noise limit to
jitter performance?
A conventional folded cascode
operational amplifier used in the
regulator
UP
Clock In
•
A jitter increases as the
required frequency increases
in modern IC design
PFD
VCO
•
•
•
The jitter should be reduced
in order to provide the good
timing clock signal to other
systems
Supply voltage of PLL
usually comes from dc-dc
converter which has ripple
through the output
AC response of the operational amplifier
II. Active Loop Filter
•
DN
•
Clock Out
Butterworth active low-pass filter with
pole compensation
High frequency noise attenuation due to
the LPF
•
LPF
Jitter without the
proposed LDO
regulator
Jitter with the
proposed LDO
regulator
Jitter with 10
samples by MC
Specifications
This work
Process Node
110 nm
Supply Voltage
1.0 V
Supply Noise
100mV @ 100kHz
Operating
Frequency
0.4 - 1.6GHz
Jitterpk-pk
17.2ps
Total Power
0.944mW @
1.6GHz
C1
Conclusion
Divider
 Supply regulation techniques with LDO regulator and ALF for low jitter of PLL.
VDD
Supply noise migration in PLL
 100mV at 100kHz supply noise is injected to VDD of the LDO regulator.
VVCO_ctrl
Vin
 The LDO regulator provides -83dB of PSRR and load current from 100μA to 40mA
 PLL with LDO regulator and ALF improves from 44.9ps to 4.6ps.
R
R
C2
 Jitter with 10 samples by Monte Carlo simulation is 17.2ps
C2
The most sensitive block to
the supply noise is the VCO
The injected supply noise
into the VCO should be
filtered for less fluctuation of
control voltage of VCO
17.2ps
 0.944mW power dissipation at 1.6 GHz and 1.0 V in a 110nm technology.
References
A conventional Butterworth active low-pass filter
PSNR of each block in PLL
AC response of Buwtterworth ALF
[1] Gyunam Jeon and Yong-Bin Kim, "A Low Jitter PLL Design Using Active Loop Filter and LowDropout Regulator for Supply Regulation ", 2015 IEEE International SoC Design Conference(ISOCC),
November 2-5, Kyeongju. South Korea, pp.223-224.