Download A Spiking-Neuron Collective Analog Adder with Scalable Precision

A Spiking-Neuron Collective Analog Adder with
Scalable Precision
Sung Sik Woo and Rahul Sarpeshkar
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Cambridge, MA 02139
Email: [email protected]
Abstract—Although neurons function with locally imprecise
analog computational units, they can collectively interact to
achieve computations with high complexity, low error rate, or
high precision. In this work, we show how many moderately
precise integrate-and-fire analog units interact via the
mechanism of a spiking ‘carry’ to collectively add numbers to
arbitrary precision. For example, in a proof-of-concept
implementation that we implemented with chips built in a 0.5
µm CMOS process, we show that four 4-bit precise analog units
can collectively interact to implement 16-bit-precise addition.
Errors in the analog computation are minimized via novel timebased calibration techniques. Our work may lay a foundation
for future collective analog computation that is arbitrarily
precise just as current digital computation is today.
I.
INTRODUCTION
Neurons are computational cells in the brain that function
with noisy, imprecise, and unreliable inputs, synapses, and ion
channels whose local accuracy is relatively poor. Nonetheless,
the brain routinely does tasks of evolutionary importance such
as 0.1% relative frequency discrimination amongst sounds,
10-s-precise discrimination amongst inputs gathered from 1ms-precise cells, and complex visual pattern recognition and
learning. Given that the brain is incredibly energy and space
efficient [1], and that the naive averaging of information in
time and space is not an efficient way to compute precisely,
there is an increasing appreciation that the brain likely uses
clever strategies to optimize reliability and precision [2].
The use of several moderate-precision analog units that
collectively interact to compute functions with higher
complexity and precision has been termed ‘collective analog
computation’. Such computation is an important reason for
why biological and neuronal systems are so efficient [1, 3].
Fig. 1 provides an example that illustrates the ideas behind
collective analog computation with respect to encoding 8-bitprecise computations: Such computation is neither purely
analog (one 8-bit-precise analog computational unit) nor
purely digital (eight 1-bit-precise logic units) but a
combination of both as shown. Each unit exploits physics or
chemistry to efficiently compute an analog basis function at
moderate precision and the interactions amongst such units
lead to higher global precision or higher complexity.
Collective analog computation is commonly found in
biological systems, including in the retina, the cochlea, spiking
neuronal systems, and gene-protein networks [1].
978-1-4673-5762-3/13/$31.00 ©2013 IEEE
Figure 1. 8-bit-precise computations in analog, digital, and collective analog
systems [3].
In this paper, we take a step towards demonstrating
collective analog computation in electronics by implementing
arbitrarily precise addition with interacting moderate-precision
analog units. Our work on addition provides time-based
calibration and error-correction mechanisms that may
generalize to other collective analog systems of the future.
II.
STRATEGIES FOR ADDITION
A.
Analog Basis Functions for Addition
The analog basis function that we use for addition in each
unit exploits Kirchoff’s Current Law and the integrating action
of a capacitor. That is, two numbers are added on a capacitor
by pouring corresponding amounts of charges one after
another onto it. When a capacitor is charged by a constant
current source (IREF), the voltage on the capacitor is set by the
sum of the turn-on times (TON) of the current source, which is
described by
VC  I REF TON 1  TON 2  / C
(1)
In order to generate the desired TON, a reference clock is used,
with the duration of one clock period defined as the value
‘one’. The main purpose of the clock is to ‘write’ accurate
digital inputs to each adding unit via a time-based digital-toanalog converter. The units themselves operate in a self-timed
and asynchronous fashion. To detect overflows (sum ≥ 16) in
each adding unit, if any, we use a reference threshold voltage
(VREF) and an associated comparator. The overflow
comparator output signals a pulsatile ‘carry’ that is used to
communicate carry information amongst units. Each unit
effectively functions like an integrate-and-fire spiking neuron
that we have configured to perform addition.
Analog charge information in the units is ‘read’ via a
simple counting analog-to-digital operation or can be
1620
Figure 2. Four phases for addition. The purpose of the Copy phase is to
compensate for the negative error voltage due to the comparator delay.
Figure 4. The schematic of the Analog Switching Network, drawn with two
copies of IREF and capacitors CA, CB, and CREF.
Figure 3. The block diagram of a 4-bit adding unit.
Figure 5. The schematic of the comparator. The selection of the negative
input occurs inside the comparator, preventing a charge-sharing problem.
preserved on the capacitor for short-term storage. The overall
adder appears to be ‘digital’ from an input-output or writeread point of view but is ‘analog inside’: The adder uses no
multi-level or binary-logic rules to add or to generate carries.
The resolution of the digital-to-analog write and the analog-todigital read set the local precision of the adding unit from an
input-output point of view. The precision of the analog
operations within the adder are designed via calibration and
error-correction mechanisms to be compatible with the
resolution required by these write and read operations. The
ability to write and read digital information from our analog
adder also allows us to verify that it is computing with no
error.
B. Four Phases for Addition
Fig. 2 illustrates four phases required for addition. First, in
the Add and Carry phases, the first and the second number,
and the carry-in are added to CA sequentially. If the voltage on
CA exceeds VREF (stored in CREF), an overflow signal (a short
pulse) is promptly fired by the comparator and the input is
redirected to CB. Next, in the Copy phase, the value on CB is
copied to CA. The purpose of the latter copy is to correct the
the negative error voltage (minus yellow bar in Fig. 2) due to
the comparator delay by adding a compensating positive
voltage (plus yellow bar in Fig. 2). The resulting voltage is
converted back to a digital number during the Read phase.
C. Architecture
The block diagram of the adder is shown in Fig. 3. Similar
to a digital adder, A<3:0>, B<3:0>, S<3:0>, Cin, and Cout are
the two digital inputs, the sum output, the carry-in, and the
carry-out pulses, respectively. In addition, Clk is the reference
clock, and Cal, Add, and Read are request signals to trigger
corresponding operations.
The analog computational core of the system consists of
the current source (IREF), three capacitors (CA, CB, and CREF),
the comparator, and the Analog Switching Network. The latter
network controls which capacitors IREF is directed to, since IREF
is used to charge different capacitors on different phases.
The Write Unit and the Read Unit perform digital-toanalog and analog-to-digital conversion, respectively. The
Calibration Unit digitally calibrates the reference threshold
voltage (VREF), compensating for various errors as we discuss
later. The Asynchronous Finite State Machine coordinates the
sequential operation of the system in its various phases.
III.
CIRCUIT OPERATION
A. The Analog Switching Network
The Analog Switching Network, shown in Fig. 4, is a set
of switches that are responsible for charging (M1, M3, and
M6) and discharging (M2, M4, and M7) of the capacitors CA,
CB, and CREF, using two copies of IREF. Inputs to the switches
come from the Asynchronous Finite State Machine. The
transistors M8 and M9 are used to discharge CREF at a
relatively slow rate during digital calibration. In addition, M5
and M10 are differential-pair switches that are turned on to
redirect IREF when none of their adjacent switches are turned
on. The use of the latter switches minimizes charge injection.
The use of minimum-size transistors for all switches reduces
charge injection and clock feedthrough as well. The use of a
single common current source between CA and CB eliminates
current-source mismatch during Add, Carry, Copy, and Read
phases.
B. The Comparator
The comparator is a crucial component of our system,
since it is used in several phases. Its schematic is shown in
Fig. 5 and consists of a classic two-stage amplifier
1621
Figure 7. The operation of the Digital Calibration Unit. INC_VREF and
DEC_VREF pulses are generated to adjust the moment of threshold crossing.
Figure 6. Simplified behavior of the Write Unit.
(preamplifier + high gain OTA) topology [1], except for the
fact that the first stage has an additional branch for the
negative input terminal. The use of this additional branch
prevents charge sharing between capacitors after switching:
Depending on the phase, the negative input terminal is
connected either to CB or to CREF, which requires selection
circuitry. The presence of the additional branch causes such
selection to occur inside the comparator rather than via
switches connected to CB and CREF, thus eliminating a chargeredistribution problem among CB, CREF, and the parasitic
capacitance at the negative input terminal of the comparator.
C. The Write Unit (Time DAC)
The Write Unit performs time-based digital-to-analog
conversion, whose behavior is depicted in Fig. 6: When an Nbit (N=4 in this system) digital number is input into the Write
Unit, N clock signals are generated by repeatedly dividing the
input clock (CLK<0>) by two. Thus, the pulse width of each
of these clock signals corresponds to the weight of each digital
bit. The output pulse, OUTPULSE is then generated by
outputting the first pulse of each clock signal, in a sequential
fashion, but gated by each corresponding bit of the digital
input. Therefore, the total duration during which OUTPULSE
is high (TON in (1)) is proportional to the digital input value.
Integrating an IREF current onto a capacitor for a duration
determined by OUTPULSE then creates an analog output
voltage, VOUT, that is proportional to the digital input,
thereby performing digital-to-analog conversion.
The exact instant of the threshold crossing should occur when
15.5 pulses of charge have been input to CA such that the
distinction between 15 and 16 can be discerned with maximal
noise margin. Our closed-loop calibration ensures that,
independent of absolute capacitor values, current values, or
threshold values, an adding unit always generates carries that
are consistent with digital computation.
Fig. 7 reveals how we calibrate an adding unit: If the
comparator output pulse, COMPOUT, fires before 15.5, an
INC_REF pulse is generated that serves to increase VREF and
delay firing. If the COMPOUT pulse occurs after 15.5, a
DEC_REF pulse is generated that serves to decrease VREF and
hasten firing. The INC_REF and DEC_REF pulses
respectively increase and decrease the value of VREF as shown
in Fig. 4. Several iterations of calibration of VREF lead to
successively smaller correction pulses and ensure that the
calibration converges to an accurate value.
F. The Asynchronous Finite State Machine
The Asynchronous Finite State Machine (FSM) serves as
the main controller of our system, and operates in an
asynchronous and self-timed fashion. Its functions include the
orchestration of the ‘Add-Carry-Copy-Read’ phases,
generation of enable/reset signals to charge/discharge
capacitors, storing and processing of incoming carry signals,
the selection of comparator inputs, communication of request
signals to other digital blocks, and other housekeeping
functions.
IV.
D. The Read Unit (Counting ADC)
The Read Unit converts an analog voltage on a capacitor
(CA) into a digital number (summed output): CB is charged
repeatedly, 1 LSB at a time, until the voltage on CB becomes
greater than that on CA. This threshold crossing is detected by
the comparator, which fires a short pulse. By counting the
number of LSB pulses until the comparator firing event, we
obtain the digital equivalent of the analog voltage.
E. The Digital Calibration Unit
The Digital Calibration Unit calibrates the threshold
reference voltage (VREF) such that the comparator signals the
VREF threshold crossing with little temporal error. To ensure
that the digital bits output by the adder are correct, it is
important to minimize this temporal error. The temporal error
is caused by several sources that are outlined in Section IV.
TABLE I.
ERROR COMPENSATION
SOURCES OF ERRORS AND COMPENSATION METHODS
Source of Error
Compensation Method
Comparator input offset voltage
Comparator & digital gate delay
Capacitor charge errors
(Charge injection, Charge sharing,
Clock feedthrough, Leakage)
Autozeroing, Dig. calibration
Copy phase correction
Use of differential-pair switching,
Use of minimum-size transistors,
Internally switched comparator
Dig. calibration,
Common centroid layout
Dig. calibration,
Use of single current source
Capacitor mismatch
Current-source mismatch
In order to achieve reliability and energy efficiency, for
each error source, corresponding error-correction methods
were designed. A summary of our error-correction methods is
1622
Figure 8. A die photograph of the collective analog adder chip.
listed in Table I. First, the input offset voltage of the
comparator is compensated for by two different methods:
Digital calibration compensates for offsets between the CA and
CREF nodes while a standard auto-zeroing technique
compensates for offsets between the CA and CB nodes. The
delay of the comparator and digital gates is compensated for
by Copy phase as described in Fig. 2. Sources of errors
affecting the capacitor nodes (charge injection, charge sharing,
clock feedthrough, and leakage) are compensated for by the
use of differential-pair transistors for switches, minimum-size
devices for comparator input transistors and switches, and
through the use of internal switching in the comparator. The
CA–CREF mismatch is compensated for by digital calibration
while CA–CB mismatch is attenuated by common-centroid
layout. IREF mismatches between our two current sources (one
used for charging CA/CB and one used for charging CREF) is
effectively compensated for by digital calibration. The
charging of CA and CB is immune to current-source mismatch
since the same current source is used for charging both
capacitors.
V.
TABLE II.
EXPERIMENTAL RESULTS
MEASURED PERFORMANCE CHARACTERISTICS
Parameter
Value
Technology
Supply voltage
Clock frequency
Capacitor size (CA, CB, CREF)
IREF
VREF
1 LSB voltage
Calibration time
Add~Read time
Compensated error in VREF
Power consumption (analog parts)
Power consumption (total)
Chip size
On-Semi 0.5 µm
2.5 V
250 kHz
59 pF
830 nA
~900 mV
56.3 mV
~800 µs
~400 µs
< 0.5 LSB
11.0 µW
16.4 µW
1.5 mm × 1.5 mm
Figure 9. An example of measured waveforms of the chip, computing
1010+1010+Cin=0101+Cout. The digital calibration and Add-Carry-CopyRead phases can be observed. Autozeroing occurs right before addition but is
not visible in the figure since its results are stored on an internal capacitor.
answers for all input sets. Fig. 9 shows an example of
measured waveforms that correspond to the additive inputs
1010+1010+Cin=0101+Cout. Seven iterations of digital
calibration and the four phases that we use to add are depicted
in Fig. 9. Measured performance for a 4-bit adding unit is
summarized in Table II.
To prove that 16-bit addition was feasible, a printed circuit
board was designed such that two 4-bit adder chips could
interact via their carry signals. Then, two such boards were
connected to create a 16-bit adder, which also produced
correct outputs for every input set: All combinatorial
possibilities were tested and found to be correct.
VI. CONCLUSION
We have presented a collective analog adder with spikingneuron units capable of arbitrarily precise addition. In
particular, we tested that 16-bit-precise addition with four 4bit-precise interacting units was successful in an ONSemiconductor 0.5 µm process. The eight techniques of error
correction that we presented in the paper were critical in
ensuring that digital and analog computations were consistent,
and should be useful in other collective analog systems of the
future.
ACKNOWLEDGMENT
The authors would like to thank MOSIS for providing chip
fabrication. This work was supported in part by the National
Science Foundation under Grant NRI-NSF CCF-1124247 and
by a campus collaboration initiative from MIT Lincoln Lab.
REFERENCES
[1]
[2]
A proof-of-concept collective analog adder chip with a 4bit adding unit was fabricated in an ON-Semiconductor 0.5
µm CMOS process. The die photograph of the chip is shown
in Fig. 8. Five chips were tested, which all generated correct
[3]
1623
R. Sarpeshkar, Ultra Low Power Bioelectronics: Fundamentals, Biomedical Applications, and Bio-Inspired Systems. Cambridge: Cambridge
University Press, 2010.
W. J. Ma, J. M. Beck, P. E. Latham, and A. Pouget, “Bayesian
inference with probabilistic population codes,” Nature Neuroscience,
vol. 9, pp. 1432–1438, 2006.
R. Sarpeshkar, “Analog versus digital: extrapolating from electronics to
neurobiology,” Neural Computation, vol. 10, no. 7, pp. 1601–1638,
October 1998.