Download STEVAL-ISA052V2

STEVAL-ISA052V2
Evaluation board for the PM6675AS high efficiency
step-down controller with embedded 2 A LDO regulator
Data Brief
Features
■
4.5 V to 36 V input voltage range
■
0.6 V, ±1% voltage reference
■
1.5 V fixed output voltage
■
0.6 V to 3.3 V adjustable output voltage
■
1.237 V ±1% reference voltage available
■
Very fast load transient response using
constant on-time (COT) control loop
■
No RSENSE current sensing using RDS(ON) of
the low-side MOSFETs
■
Negative current limit
■
Latched OVP, UVP and thermal shutdown
■
Fixed 3 ms soft-start
■
Selectable pulse-skipping at light load
■
Selectable no-audible (33 kHz) pulse-skip
mode
■
All ceramic output capacitors application
supported
■
Output voltage ripple compensation
■
Output soft-end
STEVAL-ISA052V2
and source up to 2 Apk. Two fixed current limits
(±1 A and ±2 A) can be chosen.
An active soft-end is independently performed on
both the switching and the linear regulator outputs
when disabled.
Description
This evaluation board is based on the PM6675AS
device, which consists of a single high efficiency
step-down controller and an independent lowdropout (LDO) linear regulator.
The constant on-time (COT) architecture assures
fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
Selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33 kHz for audio-sensitive
applications. The LDO linear regulator can sink
May 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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PGND
LGND
LPG
LOUT
LIN
VCCGND
J9
J11
J8
J7
J6
J10
1
1
1
R18
100k
1
1
1
VCC
0
1
2
0
R20
10k
R19
7.5k
0
C5
1u
1
2
10u
C6
0
1
10u
C7
NOSK
SKIP
JP1
2
0
R7
3R9
2
C9
100n
C10
1
0
N.M.
C19
N.M.
C20
1
2
0
R8
12k
R9
13k
1
2
3
4
5
6
25
LGND
LFB
NOSK
SKIP
LPG
SGND
AVCC
AV
THPD
U1
0
C11
10u
R10
0
VCC
6675S
PM66
VSE
VSEL
JP3
LILIM
JP2
VCC
LGATE
PGND
SPG
SP
LEN
SWEN
C12
100n
18
17
16
15
14
13
VCC
1
D1
BA
BAT54J
2
C21
100p
R3 1.2k
0
C22
100p
1
R2
18k
1
2
VCC
1
2
1
2
2
1
1
2
1
2
1
2
24
23
22
21
20
19
LOUT
LIN
BOOT
HGATE
PHAS
ASE
CSNS
VREF
VOSC
VSNS
VS
VSEL
VSE
COMP
LILIM
7
8
9
10
11
12
1
1
2
2
0
1
0
0
LEN-SWEN
R13
100k
2
SW1
2
100k
R12
1
VCC
R17
100k
1
0
2
2
C17
N.M.
R1 330k
R4 3R3
R11
1
C13
100n
0
C14
100n
1
Q2
0
2
680p
C16
0
S12NH3LL
D2
1
S12NH3LL
4
4
Q1
5
6
7
8
1
2
3
5
6
7
8
1
2
3
C1
10u
C18
1n
R16
4R7
R14
TP1
GND_TP
INT-VE
VESR
JP5
0
C2
10u
7.5k
1
2
C15
1
6.8n
2
R15 6.8k
MLC1240-901ML
L1 0.9u
0
2x UMK325BJ106KM-T
1
2
J5
STPS1L30M
1
2
VCC
2
4
6
1
3
5
1
2
1
2
R6
0
220u
C3
2x 4TPE220MF
1
2
2
4
3
1
2
2
4
6
1
3
5
1
2
1
2
1
2
220u
22
C4
J2
J1
1
1
J4
J3
SPG
SP
PGND
VOUT
VIN
PS1L30A
STPS
D3
1
1
Figure 1.
1
2
1
1
2
Circuit schematic
STEVAL-ISA052V2
Circuit schematic
Schematic diagram
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STEVAL-ISA052V2
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Revision history
Revision history
Table 1.
Document revision history
Date
Revision
05-May-2008
1
Changes
Initial release.
3/4
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STEVAL-ISA052V2
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