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Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS inverters http://www.eet.bme.hu/~poppe/miel/en/13-MOSFET2.ppt http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices Overview of MSOFET types 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 2 Budapest University of Technology and Economics Department of Electron Devices Characteristics of enhancement mode MOSFETs inversion layer Now we calculate with this! triode region 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 saturation 3 Budapest University of Technology and Economics Department of Electron Devices Simple model of MSOFETs ► The simplest (logic) model: mo conduction (off) / conduction (on) | VGS | Source (of carriers) Open (off) (Gate = ‘0’) Gate Drain (of carriers) enhancement mode device Closed (on) (Gate = ‘1’) Ron 10-11-2009 | VGS | < | VT | | VGS | > | VT | "open" "short" Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 4 Budapest University of Technology and Economics Department of Electron Devices Let's construct an inverter! ► Resistor at supply voltage (VDD) ► Other end connected to ground (GND) through a swithc ► Switch controlled by a logic signal: 1 (VDD level) – "short" 0 (GND level) – "open" VDD load resistor ► The output is the common node of the switch and the resistor OUT IN GND 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 5 Budapest University of Technology and Economics Department of Electron Devices Let's construct an inverter! ► IN ► IN =1 =0 switch "on" aoutput connected to GND VDD switch "off" output floating at VDD 0 1 OUT OUT OUT = 0 1 OUT = 1 IN 0 IN GND 10-11-2009 VDD Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 GND 6 Budapest University of Technology and Economics Department of Electron Devices Two switches in series: NAND gate ► If A and VDD B equal to 1, then OUT=0 ► This is the NOT (A AND B) function, OUT i.e. NAND A serial conduction path B GND 10-11-2009 In practice with max. 3..4 inputs. If there are parallel conductions paths then we get the NOR function Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 7 Budapest University of Technology and Economics Department of Electron Devices The scheme of the NOR gate: ► If A or B equals to 1, then OUT=0 VDD OUT GND is the NOT (A OR B) function, i.e. NOR B A ► This GND PARALLEL conduction path Complex conduction paths == option for complex logic gates 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 8 Budapest University of Technology and Economics Department of Electron Devices Complex logic gates ► Serial paths connected in parallel VDD OUT D A Out AB C ( D E ) F E C F B GND 10-11-2009 There are 4 paths Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 9 Budapest University of Technology and Economics Department of Electron Devices Inverter realizations Switch = n channle MOSFET: normally OFF device VDD VDD Load resistor: another transistor, e.g. in triode region VDD VGG load OUT OUT OUT drive IN IN GND IN GND GND Needs another supply – not OK 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 10 Budapest University of Technology and Economics Department of Electron Devices nMOS technique – very simple ► Simple process, outdated, many disadvantages VDD Depl. mode tr.: VT shifted by ion implantation OUT ► In Id ~ W/L IN GND 10-11-2009 static consumption if OUT=0 if OUT = 0, it will not be a pure GND level asymmetrical transfer characteristic (see later) both cases the load resistor is replaced by a MOSFET but this transistor was not provided with an active control This is the passive load inverter Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 11 Budapest University of Technology and Economics Department of Electron Devices Complex gates (in nMOS) ► Serial conduction paths in parallel, e.g.: OUT There are 4 paths 10-11-2009 OUT AB C ( D E ) F Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 12 Budapest University of Technology and Economics Department of Electron Devices The CMOS technique ► The name comes from: Complementary MOS ► Idea: the load also should be provided with active control if the nMOS driver (switching) trasistor conducts the load transistor must be an "open" circuit if the nMOS driver (switching) trasistor is an "open circuit", the load must be conducting ► This needs such a normally OFF device which needs "opposite" control signals than the nMOS transistors Such device is a pMOS transistor 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 13 Budapest University of Technology and Economics Department of Electron Devices The CMOS inverter ► VDD ► pMOS An n and a p type enhancement mode device Active load inverter: the two transitors have the same common control In steady state only one device is "on", the other is "off". OUT IN nMOS IN OUT IN OUT=1 GND 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 14 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Transfer characteristic: output voltage vs. input voltage U out f (U in ) The output signal is the inverted version of the logic value of the input signal 10-11-2009 Uout "1" "1" "0" Uin transfer characteristic of an ideal and a realistic inverter Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 15 Budapest University of Technology and Economics Department of Electron Devices Xfer char. of a CMOS inverter VDD pMOS OUT IN nMOS UIN=UGSn UOUT=UDSn GND 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 16 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments immunity: Same Uout corresponds to a wide Uin range There are 3 regions in the charactersitic On the L and H sides the characteristc is flat, i.e. any voltage change in the input has negligible effect on the output. "1" Uout ► Noise 10-11-2009 H "1" "0" L and H regions L Uin transfer characteristic of an ideal and a realistic inverter Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 17 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Signal regeneration U1 U2 1 U3 1 depends on the slope of the middle region U2 Uout U1 is a "bad" logic 0 signal. Output U2 of the first inverter is already close to an acceptable logic 1 level. output voltage U3 at the second inverter is already a "good" logic 0 level. "1" U3 "0" U1 U2 Uin transfer characteristic of an ideal and a realistic inverter 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 18 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Signal regeneration 6.0 U1 U2 1 U1 U2 U3 1 U3 5.0 4.0 3.0 U [V] UL=0V, UH=5V 2.0 1.0 -0.0 -1.0 0.0n 10.0n 20.0n 30.0n 40.0n time [sec] (SPICE simulation) In case of U3 both the voltage level and the signal form are visibly regenerated! 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 19 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Inverter logic threshold voltage The level, under which the signals will be converted into logical 0 and above which the signals will be converted by the inverter chain into logical 1 Uout Vdd Uk Intersection of the Uin=Uout line and the x-fer characteristic 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 Vdd Uin 20 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Logic level ranges The voltage range of the logic 0 and 1 values within which the circuit works safely in the respective logic level Uout Vdd UHm Uk UZ Example: 74HC00, Vdd=3V, ULM=0.9V UHm=2.1V 10-11-2009 ULM Vdd Uin Important voltage values ULM, max. of logic 0 UHm, min. op logic 1 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 21 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Propagation delay Uin U Uout UHm ULH t tpd tpd is difficult to define, and may be different for switching on and off (e.g. nMOS inverters) 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 22 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Inverter pair delay n 1 n+2 1 1 A long chain of uniform inverters is assumed. After a certain number of inverters the signal form will be determined by the inverter properties only. After propagating throug 2 inverters the signal will be the same, the delay will be tpdp – the inverter pair delay U Un Un+2 t tpdp 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 23 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Measuring the inverter pair delay THE RING OSCILLATOR Odd number of inverters connected in a chain, no stable state oscillate 1 1 1 1 1 T=ntpdp 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 24 Budapest University of Technology and Economics Department of Electron Devices Characteristics of inverters, rudiments ► Power-delay product (P) low power and small delay refer to good quality, the product may be a figure of merit for the quality of a circuit family. the physical meaning: the minimal energy, needed to work on 1 bit of information. 10-11-2009 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 25