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MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Department of Electrical Engineering and Computer Science
6.301 Solid State Circuits
Fall Term 2010
Problem Set 4
Issued : Sept. 24, 2010
Due : Friday, Oct. 8, 2010
Suggested Reading: Read as many of the following as you can. All of the recommended references are on
reserve at Barker Library.
1. Lundberg sections 6, 7, 8, 9, and 10.
2. Grebene section 8.3-8.5.
3. Gray and Meyer sections 7.2 and 7.3.
Problem 1: The AC schematics for four amplifiers are shown below. For each of the amplifiers, find the
midband voltage gain and the -3dB frequency using the open-circuit time-constant method. Assume
β=200, IC =2.5mA, cπ =50pF, and cµ =2pF. Neglect rb and ro for this problem.
(a) Common-Emitter:
2k
vo
1k
vi
(b) Emitter-Follower:
1k
vo
vi
2k
1
(c) Common-Base:
2k
1k
vo
vi
(d) CE with emitter degeneration:
2k
vo
1k
vi
2k
Problem 2: For the following CB-CE amplifier, assume that VBE,ON =0.6V, β=200, cπ =20pF, and cµ =2pF
for both transistors. Neglect rb and ro .
+5V
2.8k
2.4k
2k
vo
10pF
1uF
2.2k
1.6k
2k
vi
(a) Calculate the midband small-signal voltage gain.
(b) Estimate the -3dB frequency of the circuit gain using the OCT method.
2
1uF
Problem 3: For the amplifer shown below, use the following data: IS =0.5fA, β=200, cµ0 =0.5pF, cje =4pF
(in forward bias), and fT =500MHz at IC =1mA and VCB =2.5V. Assume m=0.5 and Ψ0 =0.7V for all
junctions. Neglect rb and ro .
6V
5k
10k
5k
10k
vo
vi
10uA
1mA
10uA
-6V
(a) Calculate the low-frequency voltage gain.
(b) Use the OCT method to calculate the -3dB frequency of the circuit gain.
(c) Verify the above results in HSPICE. Turn in your HSPICE input file as well as a plot showing the
high frequency roll-off.
3
Problem 4: For each of the two amplifiers shown below, assume that VBE,ON =0.6V, β=400, cπ =40pF, and
cµ =4pF for both transistors. You may neglect rb and ro . Find the small-signal voltage gain and the
-3dB frequency. Qualitatively, why does one have more bandwidth than the other?
(a) Single-ended Differential Amplifier:
VCC =15V
5k
5k
vo
Q1
Q2
vi
7.5k
-VEE =-15.6V
(b) EF-CB:
VCC =15V
5k
vo
Q1
Q2
vi
7.5k
-VEE =-15.6V
4
Problem 5: In recitation, a capacitively loaded EF such as the one shown below was discussed.
vi
vo
IE
CE
(a) Find the incremental input impedance. For simplicity, neglect cµ in the small-signal model.
(b) Show that for sufficiently small values of CE , the input impedance has a negative real part.
Determine the critical value of CE in terms of transistor parameters.
(c) Why could a negative input impedance be a bad thing?
5
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6.301 Solid-State Circuits
Fall 2010
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