Download When (Low) Power Really Matters Yogesh K. Ramadass, AnanthaGroup Microsystems Technology Laboratory

When (Low) Power Really Matters
Yogesh K. Ramadass, AnanthaGroup
Microsystems Technology Laboratory
Outline
„
Introduction
„
Voltage Scaling techniques
„
Challenges with Low voltage operation
„
System Examples
„
Conclusion
Moore’s Law
Gordon Moore
Co-founder, INTEL
„
No. of transistors doubles every two years
„
Not a physical law, started of as a graphical observation
„
Exponential increase in circuit complexity
Processor Power Levels
„
More Speed Æ More Power
„
More Processing Æ More Power
So Where is the Power Lost?
„
Analog Circuits – Opamps, ADC/DAC’s, Current/Voltage
references
† Bias
Currents
† Switches
„
Digital Circuits – Processors, Memory
† Charging
„
up capacitances
Leakage!!
† Imagine
burning calories when sitting idle
† 30% of total power in big microprocessors
† More on this later
A simplistic view of process scaling
250, 180, 130, 90, 65, 45, 32, 22
Process Scaling enables Moore’s Law
VBAT
E cycle = CLVBAT
2
Power = CLVBAT .fs
2
„
Reduce CL , reduce power
„
Area reduces too!!
†
„
Area = Cost
Faster switches
†
„
CL
More processing
Downside, switches don’t turn off completely
fs
(
V
∝
− VT )
BAT
CL .VBAT
2
Outline
„
Introduction
„
Voltage Scaling techniques
„
Challenges with Low voltage operation
„
System Examples
„
Conclusion
Dynamic Voltage Scaling
fs
(V
∝
− VT )
BAT
CL .VBAT
2
B. Calhoun
Goal: Operate Circuits at just enough voltage
Implementation of a DVS System
Change Voltage with change in workload
V. Gutnik
1996
Power Savings by DVS
Power (Normalized)
Intel Core Duo Processor
Courtesy : intel.com
„
Exponential drop Æ both voltage and frequency scale
„
Linear drop Æ only frequency scales, min. voltage
Energy Constrained Applications
Micro-sensor networks
Target Tracking & Detection
(Courtesy of ARL)
Medical devices
RFID Tags
Portable Electronics
Inductive Link
„
Try to reduce power consumption to fit in energy budget
Sub-threshold Operation
„
Sub-threshold logic operates with VDD < VT
„
Both on and off current are sub-threshold “leakage”
ID (Normalized)
100
Strong Inversion Operation:
fast, high-energy
- 2
10
10
4
Sub-threshold Operation:
slower, minimum energy
10
6
10
8
0
0.2
0.4
0.6
VDD (Normalized)
0.8
1
Speed ∝ I D
Minimum Energy Point (MEP)
ETOTAL = E ACTIVE + E LEAKAGE
= CVDD
2
−VDD
⎛
2
+ IOFF VDTD = VDD ⎜ Ceff + Leff e nVth
⎜
⎝
⎞
⎟
⎟
⎠
Eop (Normalized)
4
3.5
Active
Energy
3
2.5 Total
2 Energy
1.5
MEP
0.5
0.4
0.6
simulation
for 7-tap FIR
filter showing
minimum energy
operation
Leakage
Energy
1
0
0.2
‰ 65nm
0.8
VDD (V)
1
1.2
Motivation – Minimum Energy Tracking
Workload,
Activity
Temperature,
Duration of
Leakage
EACTIVE
VMEP
ELEAKAGE VMEP
Eop (Normalized)
5
2-taps
5-taps
10-taps
12-taps
4.5
4
3.5
3
2.5
2
Increasing
Workload
1.5
1
0.25
0.3
0.35
0.4
VDD (V)
0.45
„
Minimum Energy Point (MEP) varies with workload and
temperature
„
MEP moves when ratio of active to leakage energy
changes
„
Tracking the MEP : 0.5X – 1.5X energy savings
0.5
Operation of the Energy Minimizing Loop
VDD starts at 420mV
VDD
370mV
Loop Start
VDD settles at 370mV
Y. Ramadass
320mV
Loop Stop
Parallelism
„
Reduce Voltage Æ Slower Operation
„
Parallel banks Æ Recover Performance
„
Low power, with good performance (best of both worlds)
400mV 100Mbps baseband processor
Demodulation
Retiming Block
Serial to Parallel
Correlator 1
FIR
Coefficients
5 Tap FIR Filter
5 Tap FIR Filter
5 Tap FIR Filter
Correlator 2
Demodulated
Bits
…
…
…
5-bit Input from ADC
Correlator Bank
Correlator Sub-bank 1
Bit Decoder
5 Tap FIR Filter
Correlator L
Correlator L+1
…
…
…
………
Correlator L+2
Correlator 2L
…
…
…
Correlator Sub-bank M
Threshold Detector/
Position Encoder
Correlator Sub-bank 2
Correlator (M-1)L+1
Correlator (M-1)L+2
…
…
…
Correlator ML
Acquisition/
Timing Control
L = 20
M = 31
Total # of correlators = 620
V. Sze
Outline
„
Introduction
„
Voltage Scaling techniques
„
Challenges with Low voltage operation
„
System Examples
„
Conclusion
A Typical System
Extreme Voltage Scaling:
Sub-threshold Operation
Power Supplies
Modeling and Theory
+ W eff L DP KC g V
2
DD
−
e
V DD
nV th
Standby Power Reduction
- Fine-grained power down
- Standby voltage scaling
Sub-VT Memory
Ultra-Dynamic Voltage Scaling
DMA
E Total = C eff V
2
DD
Accelerators
Data Memory
Instruction
Cache
Sensor(s)
DSP
Radio
Challenges with sub-threshold logic
D
Strong
N1
N2
N3
Q
0.4
N2
0.35
0.3
CK
CK
N3,
nonratioed
0.25
N1
Weak
Ratioed FF
D
Strong
N1
Weak
0.2
CK
0.15
N2
N3
Q
0.1
N3
0.05
CK
0
CK
0
Weak
Weak
Non-ratioed FF
20
40
60
80
time (ns)
100
120
Ratioed FF fails to write a 1 at
strong N, weak P corner at 400mV
Challenges with sub-threshold logic
Order of Magnitude Higher Variability in Sub-VT
Functionality
Performance
Global
Local
J.Kwong
„
Local VT variation → large spread in voltage swing, delay, energy
¾
„
Errors due to degraded noise margins and timing violations
Variation-tolerant circuits (e.g. asynchronous logic, soft error correction)
A 180mV FFT Processor
A. Wang
„
FFT – Fast Fourier Transform
„
Operates down to 180mV!!!
„
5X savings in energy at the
minimum energy point
SRAM Challenges
Problem 2
Problem #1
Bitline leakage impacts read value:
Cannot read correctly!!
Feedback too strong:
Cannot write new data!!
WL
BL
WL
BLB
Problem 3
Static Noise Margin (SNM) degraded by variation:
Cannot hold data during read!!
ƒ
Lowest previous demonstrated SRAM in 65nm is 0.7V
Sub-threshold SRAM design
N. Verma
„
8-transistor SRAM cell
„
Operates down to 350mV!!!
„
20X leakage power savings
Outline
„
Introduction
„
Voltage Scaling techniques
„
Challenges with Low voltage operation
„
System Examples
„
Conclusion
Wireless Sensor Networks
ADC
ADC
¾ Scalable rate
(0-100KS/s) and
precision (12b & 8b)
¾ 25mW at 100kS/s
[N. Verma]
DSP
RF
Sensor DSP
Low-Rate RF
¾16-bit DSP with FFT
(128-1024 points)
¾On-Off Keying using a
rectification based
receiver
¾10pJ/instuction
[D.
D. Finchelstein
and N. Ickes ]
¾Rx Energy: 1-3 nJ/bit
[D. Daly]
Wireless Sensor Networks
ADC
ADC
¾ Scalable rate
(0-100KS/s) and
precision (12b & 8b)
¾ 25mW at 100kS/s
[N. Verma]
DSP
RF
Sensor DSP
Low-Rate RF
¾16-bit DSP with FFT
(128-1024 points)
¾On-Off Keying using a
rectification based
receiver
¾10pJ/instuction
[D. Finchelstein
and N. Ickes ]
¾Rx Energy: 1-3 nJ/bit
[D. Daly]
Ultra-wideband (UWB) Radio
UWB versus Narrowband
UWB
Possible UWB Applications
Narrowband
500Mb
WLAN
50Mb
freq
time
UWB
„
Narrowband
5Mb
500kb
Wireless
USB &
Multimedia
1m
Locationing/Tagging
10m
Advantages of UWB communications include
† High
Data Rate
† Low Interference
„
Integrate UWB radios on battery operated devices
„
Need an energy efficient UWB System
100m
distance
Ultra-low-Power Low Rate UWB
Transmitter
data
PPM Del
PRF
Clock
Digital Calibrated
Channel Selection
„ Transmitter
uses no
static power
N
Pulse-width
Phase Scrambling
Edge Combiner
RFout
Receiver
Center
Freq
S/H
Duty
Cycle
Gain
Control
RFin
S/H
S/H
S/H
RF
Front-end
„ Duty
4:2
MUX
Bits Out
cycled at the bit level for
power savings
D. Wentzloff and F. Lee
Hybrid CMOS/Carbon Nanotube Systems
Carbon Nanotube Characterization
CNT RF Impedance
Characterization
Parasitics
Parasitics
Parasitics
Parasitics
CNT DC Impedance
Characterization
Carbon Nanotube – CMOS Hybrid System Design
CNT Sensors
CMOS Interface
Chemical Sensor System
CNT Power Transistor Design
T. Cho, K. Lee, T. Pan (Prof. J. Kong)
Chip Design Flow
„
Specifications
„
Design (4-5 months)
†
†
†
Cadence
Verilog (Synopsys tools,
Astro…)
Spice
„
Layout (1-2 months)
„
Long Wait…(3-6 months, Prof.
asks you to start next design)
„
Chip comes back
†
†
†
„
Package
PCB (test board)
Test
Write paper (hopefully the
chip has worked)
Sub-Threshold ICs
[ISSCC05]
Adder
[ISLPED06]
Sub-VT Library
Test Chip and FIR
(65nm CMOS)
[ISSCC07]
DC-DC
Converter &
Energy
Minimizing
Loop ( 65nm)
32kb Block
U-DVS [90nm]
[ISSCC06]
256kb SRAM
Array 65nm
[ISSCC07]
256kb 8-T SRAM
65nm
with Redundancy
[ICASSP06 and ISSCC07]
Highly Parallel
UWB
Baseband
(90nm)
[VLSI Symposium 06]
500MS/s
Ch.
6 Ch. 5 ADC
Ch. 4
For UWB
Using 6-way
Ch.Interleaving
1 Ch. 2 Ch. 3
(65nm)
[PESC07]
500Ms/s ADC
Switched
Capacitor
DC-DC
Converter
(0.18µm)
Using 36-parallel
Channels
(65nm)
Helpful Classes
„
Circuits – 6.002, 6.301, 6.374, 6.376, 6.775, 6.776, 6.334
„
Devices – 6.012, 6.728, 6.730, 6.774
„
Control Theory – 6.302, 6.331
„
Signal/Image Processing – 6.003, 6.341, 6.344
„
Communication – 6.450, 6.451
Groups at MIT
„
Circuit Design
†
Prof. Anantha Chandrakasan
†
Prof. Joel Dawson
†
Prof. Hae-Seung Lee
†
Prof. David Perreault
†
Prof. Michael Perrott
†
Prof. Rahul Sarpeshkar
†
Prof. Charles Sodini
†
Prof. Vladimir Stojanovic
A Sample of Microelectronics Companies
„
Intel
„
Texas Instruments
„
IBM
„
Analog Devices
„
National Semiconductor
„
Infineon
„
Philips
„
ST Microelectronics
Conclusions
„ Low
Power Operation is crucial for
continued success of portable electronics
„ Lots
of new circuit design challenges
ahead
„ Energy
scavenged electronics has a huge
potential
„ Exciting
field to work on, direct relevance
to industry