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Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-CMOS.ppt http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT Vin Vout DEVICE G S n+ 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 D n+ 2 Budapest University of Technology and Economics Department of Electron Devices The CMOS inverter – recall VDD VDD VDD p OUT IN IN=1 OUT=0 IN=0 OUT=1 n GND GND GND In steady-state only on transistor is "on", the other one is always "off" 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 3 Budapest University of Technology and Economics Department of Electron Devices Characteristic of the CMOS inverter nMOS is "on" pMOS is "on" pMOS is "on" nMOS is "on" 2 basic cases, depending on the supply voltage and threshold voltages of the transistors VTp VTn 0 U V DD VTn IN 0 VTp UIN V DD 1. small supply voltage: VDD< VTn+ |VTp| 2. larger supply voltage VDD> VTn+ |VTp| only one transistor is "on" at a time when switching over, both transistors are "on" at the same time 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 4 Budapest University of Technology and Economics Department of Electron Devices Characteristic of the CMOS inverter small supply voltage: VDD< VTn+ |VTp| if ..........................U IN < V DD - VTp VDD the characteristics: U OUT= if ....VTn < U IN < V DD - VTp indefinit 0 if .........................U IN < VTn U OUT The middle part of the transfer characteristic is very steep, this the specific advantage of CMOS inverters. VDD UOUT VDD Indefinit ► 1. U IN VTn VDD VDD -VTp 16-11-2009 U IN VTn CMOS circuits © András Poppe, BME-EET 2008 VDD -VTp VDD 5 Budapest University of Technology and Economics Department of Electron Devices Characteristic of the CMOS inverter ► 2. large supply voltage: VDD> VTn+ |VTp| Switching over? - "mutual conduction" ► Constructing 16-11-2009 the characteristic: CMOS circuits © András Poppe, BME-EET 2008 6 Budapest University of Technology and Economics Department of Electron Devices The CMOS inverter Design for symmetrical operation: If UIN=Uinv logic threshold voltage, both transistors have equal current: 2 2 K n (U inv - VTn ) K p (U DD - U inv - VTp ) U inv U DD - VTp + VTn K n / K p 1+ Kn / K p UGSn=UK UGSp=VDD-UK W X Cox KX L X 2 The inverter logic threshold voltage depends on the ratio of the current constants of the transistors. To have Uinv at VDD/2 and VTn=|VTp|, then Kn=Kp has to be set. W W 2 .. 2 . 5 since hole mobility is 2 ... 2.5 times less L P L n The logic threshold voltage can be set by the W/L ratios 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 7 Budapest University of Technology and Economics Department of Electron Devices The CMOS inverter / dynamic char. ► Calculation of the switching times What do they depend on? • the current driving capability of the output • the capacitive load on the output out out ► If the characteristics of the two transistors are exactly complementary (Kn=Kp and VTn=|VTp|), rising and falling times will be equal 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 8 Budapest University of Technology and Economics Department of Electron Devices The capacitnces ► ► ► Intrinsic capacitances of the driving stage Input capacitance of the loading stage (next gate) – extrinsic or fanout capacitances wiring (interconnect) capacitance M2 Vin CG4 M4 CDB2 Vout1 CGD12 M1 Vout2 Cw CDB1 CG3 M3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 9 Budapest University of Technology and Economics Department of Electron Devices The capacitnces ► The intrinsic capacitances: S-G G-D overlap capacitances the MOS capacitance of the channel capacitances of pn junctions ► The wiring capacitance depends on the interconnect geometry (width, length) with the advance of manufacturing processes this capacitance tends to increase See later 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 10 Budapest University of Technology and Economics Department of Electron Devices The CMOS inverter / dynamic char. ► Calculation of switching times out identical times, integration for the extreme values of the voltage of the load capacitance: VLM If then 16-11-2009 out CL tl dU I VDD D I D K (VDD - VT ) 2 CL (VDD - VLM ) tl 2 K (VDD - VT ) CMOS circuits © András Poppe, BME-EET 2008 VLM – minimal voltage of the load capacitance Can be reduced by increasing the supply voltage or the W/L ratio 11 Budapest University of Technology and Economics Department of Electron Devices Power consumption of CMOS inv.: ► There is no static consumption since there is no static current ► There is dynamic consumption during switching which consists of 2 parts: Mutual conduction: • During the rise of the input voltage both transistors are "on" VTn<UIN<VDD-VTp Charge pumping: • At switching over the output to 1 the CL loading capacitor is charged to the supply voltage through the p transistor, then it is discharged towards the ground through the n transistor. Charge is pumped from VDD to GND. 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 12 Budapest University of Technology and Economics Department of Electron Devices Power consumption of CMOS inv.: ► Mutual conduction ("short power"): I MAX K VDD / 2 - VT 2 I [10uA], U [V] • During a certain period of the rise of the input signal both transistors are "on" if VTn<UIN<VDD-VTp this is called mutual conduction I Vin Vout 7.0 6.0 4.0 2.0 0.0 0.0n 10.0n 20.0n 30.0n 40.0n time [sec] • charge flowing through: Q btUD I MAX , where tUD is the time while current is flowing, b is a constant depending on the signal shape. b0.1-0.2 P fQVDD fVDDbtUD K (VDD / 2 - VT ) 2 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 P ~ f VDD3 13 Budapest University of Technology and Economics Department of Electron Devices Power consumption of CMOS inv.: ► Charge pumping: • At switching the CL load capacitance is charged to VDD through the p-channel device when the output changes to 1, later, when switching the output to 0, it is discharged towards GND through the n-channel device. QL CLVDD Pcp=f CLVDD2 • The power consumption due to charge pumping is proportional to the frequency and the square of the supply voltage. ► Total consumption: sum of the two components (if there is mutual conduction), directly proportional to the frequency and the 2nd and 3rd power of the supply voltage. 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 14 Budapest University of Technology and Economics Department of Electron Devices Components of the consumption of CMOS circuits ► Dynamic components – at every switching event mutual conduction, charge pumping proportional to the the event density • clock frequency • circuit activity ► Further components due to parasitics: subthreshold currents leakage currents of pn junctions – nowadays already significant leakage (tunneling) through the a gate dielectric 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 15 Budapest University of Technology and Economics Department of Electron Devices Construction ► ► ► 16-11-2009 Constructing CMOS gates Technology (overview of the poly-Si gate process) Layout CMOS circuits © András Poppe, BME-EET 2008 16 Budapest University of Technology and Economics Department of Electron Devices CMOS gates ► Create an nMOS switching curcuit (pull down network): series path: NAND function paralel path: NOR function combination of these: complex gate ► switches: nMOS transistors ► Load: the dual circuit of the nMOS network: pMOS network 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 17 Budapest University of Technology and Economics Department of Electron Devices CMOS gates ► In a CMOS inverter both transistors are actively controlled ► In case of gates there will be a PUN (pull up network: pMOS circuit) and a PDN (pull down network: nMOS circuit). The number of transistors both in PUN and PDN is equal to the number of inputs of the gate For input combinations where the output is 0, the PDN realizes a short towards GND and the PUN is an open circuit; if the output function is equal to 1, the PDN will be an open circuit and the PUN realizes a short towards VDD. Circuits with dual topology should be realized from n and p channel transistors ► Gates of transistors receiving the same signal are connected 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 18 Budapest University of Technology and Economics Department of Electron Devices CMOS gates ► NOR ► NAND gate gate out out For an n input CMOS gate 2n transistors are needed (passive load gates need only n+1 transistors) 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 19 Budapest University of Technology and Economics Department of Electron Devices Construction complex CMOS gates ► ► ► ► dual topology (loop cut, cut loop) dual components: nMOS replaced by pMOS transistor gates corresponding to the same signal must be connected proper sizing of the W/L ratios (e/h mobility mismatch) UDD F A + BC A Uout B C 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 20 Budapest University of Technology and Economics Department of Electron Devices The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT Vin Vout DEVICE G S n+ 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 D n+ 21 Budapest University of Technology and Economics Department of Electron Devices Metal gate MOS transistor In-depth structure: Source doping Layout view: Gate Drain doping Thin oxide Source Problems: • metal gate – large VT • requires accurate mask alignment 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 Drain contact 22 Budapest University of Technology and Economics Department of Electron Devices Poly-Si gate MOS transistor In-depth structure: Source doping Layout view: Gate Drain doping thin oxide Source Advantages • smaller VT • self alignment 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 Drain contact 23 Budapest University of Technology and Economics Department of Electron Devices A poli-Si gate-es nMOS technológia ► Start with: p type substrate (Si wafer) • cleaing, • grow thick SiO2 – this is called field oxide 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 24 Budapest University of Technology and Economics Department of Electron Devices The poli-Si gate nMOS process ► Create the active zone with photolithography • • • • coat with resist, expose to UV light through a mask, development, removal of exposed resists etching of SiO2 removal of the resist M1: active zone 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 25 Budapest University of Technology and Economics Department of Electron Devices The poli-Si gate nMOS process ► Create the gate structure: • • • • growth of thin oxide deposit poly-Si pattern poly-Si with photolithography etch poly-Si, etch thin oxide (resist, exposure, develop) M2: poly-Si pattern 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 26 Budapest University of Technology and Economics Department of Electron Devices The poli-Si gate nMOS process ► S/D doping (implantation) • the exide (thin, thick) masks the dopants • this way the self-alignment of the gate is assured ► Passivation: deposit PSG 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 27 Budapest University of Technology and Economics Department of Electron Devices The poli-Si gate nMOS process ► Open contact windows through PSG • photolithography (resist, expose pattern, • etching (copy the pattern) • cleaning develop) M3: contact window pattern 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 28 Budapest University of Technology and Economics Department of Electron Devices The poli-Si gate nMOS process ► Metallization • Deposit Al • photolithography, etching, cleaning M4: metallization pattern ► ► The recepy of the process is given, the in-depth structure is determined by the sequence of the masks One needs to specify the shapes on the masks The set of shapes on subsequent masks is called layout 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 29 Budapest University of Technology and Economics Department of Electron Devices Layout of a depletion mode inverter ► ► S G D S G Layout == set of 2D shapes on subsequent masks Masks are color coded: ► active zone: red poly-Si: green contact windows: black metal: blue Mask == layout layer D Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 30 Budapest University of Technology and Economics Department of Electron Devices Layout primitives: simple shapes Active zone (window opening through the oxide) Gate (mask of poly-Si pattern) Contacts (window opening mask through oxide/PSG) S/D lines (mask of metallization pattern) 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 31 Budapest University of Technology and Economics Department of Electron Devices Layout macros – from primitives layout of an nMOS transistor: layout primitives on actual layers corresponding to real masks nMOS transistor layout + outline + pins G D nMOS S nMOS transistor macro: outline, pins, scripts: pszeudo layers G 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 32 Budapest University of Technology and Economics Department of Electron Devices Simplified layout: stick diagram Vdd active 2/2 Out poly Out metal In contact 2/2 In GND W/L ratios are given 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 33 Budapest University of Technology and Economics Department of Electron Devices CMOS structure (inverter) n+ n+ p+ p+ n well p-Si substrate 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 34 Budapest University of Technology and Economics Department of Electron Devices Layout of a CMOS inverter UDD + p n well D - n p-MOS S + n + Uout n p well - p S + p n-MOS D GND Uin 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 poli 35 Budapest University of Technology and Economics Department of Electron Devices Layout macros – from macros and primitives G G D nMOS S D G pMOS S G Gate level layout 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 36 Budapest University of Technology and Economics Department of Electron Devices CMOS structures ► Further masks: n-well (or p-well, depending on the substrate) p doping (or n doping, depending on the substrate) ► Multiple metal layer CMOS: each metallization needs own mask, conatct windows, vias ► There could be multiple poly-Si layers (analog CMOS) ► Typically: 15..20 masks ► Certain rules need to be kept for manufacturability: design rules come from the process, given by Si-foundry 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 37 Budapest University of Technology and Economics Department of Electron Devices Details of a CMOS circuit 2 metal layers only INV NAND3 Layout extraction: checking, real delays 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 38 Budapest University of Technology and Economics Department of Electron Devices Modern metallization 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 39 Budapest University of Technology and Economics Department of Electron Devices Intel 0.25 µm process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 40 Budapest University of Technology and Economics Department of Electron Devices Si-compilers ► ► ► ► Logic schematic / netlist / high level description Transistor level schematic with W/L information Stick diagram layout Actual layout 1. 2. Automatic conversion between these representations HARDWARE SYNTHESIS From behavioural description structural description Implementation of the structural description with a given realization mode / manufacturing process: technology mapping • • We have seen basics of the realization of an application specific integrated circuit (ASIC) Designs can also be mapped to an FPGA 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 41 Budapest University of Technology and Economics Department of Electron Devices Interconnect capacitances Interconnect - substrate: parallel plate capacitance Current flow dir. L Electrical field W H dielectric (SiO2) tdi substrate Dielectric constant (SiO2 => 3.9) 16-11-2009 Cpp = (di/tdi) WL CMOS circuits © András Poppe, BME-EET 2008 42 Budapest University of Technology and Economics Department of Electron Devices Interconnect capacitances Cwire = Cpp + Cfringe + Cinterwire = (di/tdi)WL + (2di)/log(tdi/H) + (di/tdi)HL fringe interwire paralell plate 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 H 43 Budapest University of Technology and Economics Department of Electron Devices Other issues of interconnects ► Series resistance ► Distributed parameter RC line (see transmission lines) Sort of a representation of the diffusion equation 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 44