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0.13 m CMOS Technologies
for Analog Front-end Circuits in LHC
Detector Upgrades
M. Manghisoni, L. Ratti, V. Re, V. Speziali, G. Traversi
Università di Pavia
Dipartimento di Elettronica
Università di Bergamo
Dipartimento di Ingegneria Industriale
INFN
Sezione di Pavia
11th Workshop on Electronics for LHC
and future Experiments
12-16 September 2005, Heidelberg, Germany
2
Outline
 Deep submicron CMOS technologies for detector readout
 Investigated Technology: 0.13 µm CMOS process by STM
 Experimental results from noise characterization
 Channel thermal noise
 1/f noise
 Low noise preamplifier design criteria
 Radiation hardness characterization
 Conclusions
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
3
Deep submicron CMOS for detector readout

High functional density, low power, high speed, low noise  widely used for
readout of high granularity detectors (microstrip, pixel)

High performance mixed signal systems were fabricated in 0.25 m CMOS
processes

0.13 m processes for the new generation of strip and pixel detector
readout systems (LHC upgrades, Linear Collider, Super B-Factory)

Thinning of the gate oxide associated to device scaling reduces the sensitivity to
ionizing radiation

Design of preamplifier input device: behavior of noise parameters with gate
length and width, drain current, oxide thickness
 The impact of technology scaling on the analog and noise performances (white
and 1/f noise at low current density) must be monitored
 Data obtained from the measurements provide a powerful tool to model noise
parameters and establish design criteria in a 0.13 m CMOS process for
detector front-ends
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Investigated Technology
•
Technology Features
–
–
–
–
–
•
0.13 m generation CMOS technology
STMicroelectronics HCMOS9 process
VDD = 1.2 V
oxide thickness: 2.4 nm
gate capacitance per unit area: COX=15 fF/ m2
Test Devices
–
Standard PMOS and NMOS devices
–
W = 200, 600, 1000 m
–
L = 0.13 - 1 m
–
Standard open structure layout
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Device operating region
 In mixed-signal detector readout systems, power dissipation constraints set an upper
limit on the drain current ID in the preamplifier input device
 Devices were characterized at drain currents from 100 A to 1 mA
 At such drain currents deep submicron devices are biased in weak or moderate
inversion
 A key parameter for the signal and noise performances of a CMOS device is the
transconductance whose behavior depends on the operating region
Weak inversion
•
•

gm 
ID
nVT
VT=kT/q thermal voltage
n coefficient proportional to the inverse of the subthreshold slope of ID = f (VGS)
 In weak inversion the transconductance is independent of gate geometry and
device polarity
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
6
Noise in CMOS transistors
The noise performances of a MOS device can be characterized in terms of the gatereferred noise voltage spectrum
White noise:
1/f noise:
• Channel thermal noise
(dominant at low current
density)
• Kf = intrinsic process
parameter
• COX = OX/tOX
(tOX=oxide thickness)
• f = 1/f noise slope

S  4kT
gm
2
W
• Noise in parasitic
resistors
NMOS
1/2
Kf
1
COX WL f αf
Noise Voltage Spectrum [nV/Hz ]
S2e (f)  S2W 
100
1/f Slope for  =1
10
f
PMOS
1
W/L=1000/0.2
I =1 mA, |V |=0.6 V
D
0.1
10
3
DS
10
4
10
5
10
6
10
7
10
8
Frequency [Hz]
 The analysis of the experimental results includes the comparison of white and
1/f noise components of PMOS and NMOS devices with different geometries and
characterized at different drain currents
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Noise vs channel length and drain current
100
NMOS
L=0.13 m
L=0.35 m
L=1.00 m
10
W=1000 m
Id=250 A
|V |=600 mV
1
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
100
Id=0.10 mA
Id=0.25 mA
Id=1.00 mA
10
W/L=1000/0.35
|V |=600 mV
DS
1
DS
3
10
4
10
5
10
6
10
7
10
Frequency [Hz]
 White Noise not sizably affected
by L variations
 1/f Noise increases when L
decreases
12-16 Sept 2005, Heidelberg
8
10
3
10
4
10
5
10
6
10
7
10
8
10
Frequency [Hz]
 White Noise decreases with the
increase of ID due to the increase
in transconductance
 1/f Noise in NMOS not sizably
affected by ID variations
11th Workshop on Electronics for LHC and future Experiments
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Channel thermal Noise
The following relationship can be used in all inversion regions:
S2W  4kT

gm
   W n
  ranges from 1/2 in weak inversion to 2/3 in strong inversion
 n coefficient inversely proportional to the slope of the subthreshold region in the ID=f(VGS)
 W = excess noise factor ( 1), may increase due to short channel effects
5
5
White Noise Voltage [nV /Hz]
PMOS
DS
3
4
n=1.25
Slope for =1/2
and  =1
W
2
L=0.13
L=0.20
L=0.35
L=0.50
L=.070
L=1.00
1
Slope for
=2/3 and  =1
m
m
m
m
m
m
Slope for =1/2
and  =1
W=1000 m
|V |=600 mV
2
W=1000 m
|V |=600 mV
2
White Noise Voltage [nV /Hz]
NMOS
4
W
DS
3
n=1.25
2
1
Slope for
=2/3 and  =1
W
0
50
100
150
200
1/g [A/V]
m
12-16 Sept 2005, Heidelberg
250
300
350
400
m
m
m
m
m
m
W
0
0
L=0.13
L=0.20
L=0.35
L=0.50
L=.070
L=1.00
0
50
100
150
200
250
300
350
400
1/g [A/V]
m
11th Workshop on Electronics for LHC and future Experiments
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Channel Thermal Noise vs Drain Current
5
5
W=1000 m
|V |=600 mV
2
DS
1
0
PMOS
3
W=1000 m
|V |=600 mV
2
DS
1
0.2
0.4
0.6
0.8
Drain Current [mA]
1
1.2
W/L=1000/0.35
|V |=600 mV
3
DS
2
1
0
0
0
NMOS
PMOS
4
2
4
White Noise Voltage [nV /Hz]
NMOS
3
L=0.13 m
L=0.35 m
L=1.00 m
2
4
White Noise Voltage [nV /Hz]
L=0.13 m
L=0.35 m
L=1.00 m
2
White Noise Voltage [nV /Hz]
5
0
0.2
0.4
0.6
0.8
Drain Current [mA]
1
1.2
0
0.2
0.4
0.6
0.8
1
1.2
Drain Current [mA]
 For both the polarity channel thermal noise decreases with the increase of the ID due
to the increase of gm
 White noise decreases for short channel devices except for the NMOS device with
the minimum channel length allowed by the technology (L=0.13 m) which exhibits a
larger thermal noise due to short channel effects
 PMOS exhibits a slightly larger white noise due to the smaller transconductance
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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1/f noise slope
 The slope of the low frequency component of the spectrum differs from the case f=1
 Values of f  1 were found for the PMOS, while f  1 for the NMOS
2
2
PMOS
1.5
f
1


f
1.5
PMOS
1
NMOS
0.5
0.5
NMOS
Id=0.10 mA
Id=0.25 mA
Id=0.50 mA
Id=0.75 mA
Id=1.00 mA
1000/0.13
1000/0.20
1000/0.35
0
1000/0.50
1000/0.70
1000/1.00
0
0
0.2
0.4
0.6
0.8
Channel Length [m]
1
1.2
0
0.2
0.4
0.6
0.8
1
1.2
Drain Current [mA]
 In the examined region, the parameter  f does not exhibit any clear dependence on
the channel length L nor on the drain current ID
 Typical values of the slope coefficient of the low frequency noise component are
f = 1.2 for the PMOS and f = 0.85 for the NMOS
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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1/f noise parameter Kf for NMOS
35
40
30
J Hz
-25
15
10
20
15
f
f
25
K [10
-25
J Hz
20
K [10
1000/0.13
1000/0.35
1000/0.7
1000/1.00
35
]
]
(1-alpha_f)
25
mA
mA
mA
mA
mA
(1-alpha_f)
Id=0.10
Id=0.25
Id=0.50
Id=0.75
Id=1.00
30
5
W=1000 m, |V |=600 mV
10
5
W=1000 m, |V |=600 mV
DS
DS
0
0
0.2
0.4
0.6
0.8
Channel Length [m]
1
1.2
0
0
0.2
0.4
0.6
0.8
1
1.2
Drain Current [mA]
 Coefficient Kf extracted from measurements on NMOS with L<0.35 m is larger
than for devices with longer channels
 Avoid minimum channel length for NMOS devices implementing low-noise functions
 In the examined region Kf does not exhibit any clear dependence on the drain
current ID
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
12
1/f noise parameter Kf for PMOS
mA
mA
mA
mA
(1-alpha_f)
]
100
K [10
DS
0.2
0.4
0.6
0.8
Channel Length [m]
1
40
W=1000 m
|V |=600 mV
DS
DS
0
0
60
20
W=1000 m
|V |=600 mV
20
0
1.2
m
m
m
m
m
f
40
f
W=1000 m
|V |=600 mV
20
80
J Hz
60
-25
K [10
40
f
K [10
-25
60
L=0.13
L=0.35
L=0.50
L=0.70
L=1.00
100
80
J Hz
80
m
m
m
m
m
-25
]
(1-alpha_f)
L=0.20
L=0.35
L=0.50
L=0.70
L=1.00
]
Id=0.10
Id=0.25
Id=0.50
Id=1.00
100
J Hz
120
120
(1-alpha_f)
120
0
0.2
0.4
0.6
0.8
Drain Current [mA]
1
1.2
0
-0.1
-0.05
0
0.05
0.1
0.15
Overdrive Voltage [V]
 A sizable increase of Kf both with the channel length L and the drain current ID is
detected
 In p-channel devices Kf increases with the overdrive voltage (VGS-VT)
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Design of preamplifier input device

White and 1/f noise parameters extracted from measurements can be used to
optimize the input device (gate dimensions, drain current) in detector applications

Equivalent Noise Charge in an analog processing channel
A1
Kf
2 2A 2 ( α f )
ENC  S C

CT
t P COX WL
t1Pα f
2
2
W
2
T
white noise
1/f noise
 CT total capacitance at the preamplifier input, including the detector capacitance, the
preamplifier input and feedback capacitance and strays
 tP signal peaking time
 A1 and A2 coefficients depending on the signal shaping
 On the basis of this equation it is possible to estimate the noise limits of the 0.13 m
CMOS technology. The ENC is calculated assuming A1=1 and A2=0.5 which are
close to the typical values for a good unipolar semigaussian shaper
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Capacitive Matching
Equivalent Noise Charge as a function of the Ci/CD ratio (Ci is the preamplifier input
capacitance, CD is the detector capacitance)
1400
L=0.35 m
C =10 pF
NMOS
PMOS
D
P =0.25 mW
D
1200
t =20 ns
ENC [e rms]
P
1000
800
600
0.1
1
C /C
I
D
 Minimum value attained for Ci/CD  0.15 for the NMOS and Ci/CD  0.2 for the
PMOS  smaller than 1/3 (found for devices operating in strong inversion)
 NMOS achieves a smaller ENC at a smaller Ci/CD since it operates closer to weak
inversion with a larger transconductance gm
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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ENC and power consumption
Equivalent Noise Charge as a function of the power dissipation
1400
NMOS
PMOS
Optimum ENC [e rms]
1200
L=0.35 m
C =10 pF
1000
D
t =20 ns
P
800
600
400
0.1
1
Power Consumption [mW]
 At short processing times ENC can be reduced by increasing the power dissipation
 If the power dissipation is increased, the optimum capacitive matching conditions
are also changed, and the input capacitance Ci has to be adjusted by acting on the
gate width
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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ENC and peaking time
Equivalent Noise Charge as a function of the peaking time
1600
Optimum ENC [e rms]
1400
NMOS
PMOS
1200
L=0.35 m
C =20 pF
1000
D
P =1 mW
D
800
600
400
200
0
10
100
1000
Peaking Time [ns]
 At peaking times beyond 80 ns the PMOS provides smaller ENC values
 If peaking times exceeding 100 ns are compatible with the experimental constraints
a PMOS-input preamplifier should be used to get better noise performances
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Scaling impact on ENC
2000
Optimum ENC [e rms]
NMOS
1500
TSMC 0.25 m process ()
L=0.35 m
C =20 pF
D
P =1 mW
D
1000
500
ST 0.13 m process
0
10
100
1000
Peaking Time [ns]
() Obtained from data presented by G. De Geronimo et al in "MOSFET Optimization in Deep Submicron Technology for
Charge Amplifiers" (2004 IEEE NSS Conference Record)
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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60Co
-rays effects on device performances
10
-2
10
-4
PMOS
Drain Current [A]
Drain Current [A]
 Investigated devices were irradiated up to 10 MRad(SiO2) total dose with -rays 60Co
source. The MOSFETs were biased during irradiation in the worst-case condition (PMOS:
all terminals grounded, NMOS: 1.2 V on the gate relative to source, drain and body)
NMOS
10
-2
10
-3
W/L=1000/0.2
10
-6
W/L=1000/1
before irradiation
10
10
-4
10 Mrad
-8
before irradiation
10 Mrad
10
-10
-1.2
10
-0.8
-0.4
0
0.4
0.8
1.2
Gate-to-Source Voltage [V]
-5
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Gate-to-Source Voltage [V]

Characteristics unaffected for VGS  VT (very small threshold voltage shift)

Radiation-induced changes are apparent in the constant leakage current zone for both
devices

increase in the subthreshold region in NMOS (edge effects due to radiation-induced
charge at the STI oxide). Effect larger in devices with a shorter channel
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
19
60Co
-rays effects on noise
100
D
|V |=600 mV
DS
10
1
PMOS
before irradiation
10 MRad
0.1
3
10
4
10
5
10
6
10
Frequency [Hz]
7
10
8
10
W/L=1000/0.35
I =0.1 mA
NMOS
1/2
NMOS
Noise Voltage Spectrum [nV/Hz ]
W/L=1000/0.35
I =1 mA
1/2
Noise Voltage Spectrum [nV/Hz ]
100
D
|V |=600 mV
DS
10
1
PMOS
before irradiation
10 MRad
0.1
3
10
4
10
5
10
6
10
7
10
8
10
Frequency [Hz]

Channel thermal noise is affected to a very limited extent by ionizing radiation

Increase of 1/f noise is also very small for PMOS device and NMOS with a relatively
long channel (L>0.5 m)

In short-channel NMOS devices at low ID (around 100 A) 1/f noise increases by a
much larger extent than at higher drain currents

This may be correlated with the ID increase in the subthreshold region  STI oxide
contributes in determining the 1/f noise properties of irradiated open-structure devices
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Conclusions
 This work presented a noise characterization of devices in a 0.13 m CMOS
technology
 Parameters extracted from measurements are used to derive optimization
criteria for the preamplifier input device in a detector analog readout channel
 Technology exhibits a large degree of tolerance to ionizing radiation and it is
suitable to the design of rad-hard analog circuits. Limitations concerning shortchannel NMOS may arise at low drain current  low-noise NMOS should be
implemented with an enclosed structure
 Work is currently in progress to extend the experimental analysis to 0.13 m
devices from different foundries, with the goal of defining a more complete
overview of the noise performances achievable with this CMOS generation
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
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Backup slides
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
22
1/f noise energy parameter
 If f = 1, Kf is a measure of 1/f noise “energy” in joules
 If f ≠ 1, as it is often found in deep submicron devices, 1/f noise energy is
dependent on frequency and can be defined by the parameter E1/f(f):
E1/f (f)  K f f
1α f
1000
W=1000 m
E1/f(f) at f = 10 kHz
The 1/f noise contribution appears to
be larger in NMOS by about a factor
of 10 for devices with the minimum
channel length while a lower
difference appears for longer
channels
-25
[10 J]
100
E
1/f
10
1
NMOS L=0.13 m
NMOS L=1.00 m
PMOS L=0.13 m
PMOS L=1.00 m
0.1
0
0.2
0.4
0.6
0.8
1
1.2
Drain Current [mA]
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments
23
Noise Measurement System
Low-noise
transimpedance
amplifier
gate/drain
bias circuit
Gain
stage
Network/
Spectrum
Anlyzer
S
DUT
Bulk/Well
bias circuit
en_DUT (f) 
12-16 Sept 2005, Heidelberg
2
2
VOUT
(f)  VGND
(f)
G(f)
2
11th Workshop on Electronics for LHC and future Experiments