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EE 1105: Introduction to EE
Freshman Seminar
Lecture 11
Integrated Circuit Fabrication
Electronics, Digital Circuits
Dan O. Popa, Intro to EE, Spring 2015
Nonlinear Circuit Elements- Diode
Semiconductors (Si, Ge) can be
doped with impurities
Dan O. Popa, Intro to EE, Spring 2015
Image Sources: Internet
Si Wafer Ingot
Dan O. Popa, Intro to EE, Spring 2015
Crystallographic Orientation of Si Wafers
Dan O. Popa, Intro to EE, Spring 2015
Fabrication: Wafer/Die
Wafer
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1”-3” – for early development in
MEMS
4”, 6” – typical of MEMS today
8”, 12” – typical of semiconductors
Dan O. Popa, Intro to EE, Spring 2015
Die
Typical sizes: 15mm x 15 mm, 1cm x 1cm
0.5cm x 0.5cm, min ~1mm x 1mm
Number of Dies on Wafer
Wafer _ Area Wafer _ circumference D 2 D
N

 2 
Die _ Area
Die _ Diagonal
d
d 2
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Formula is approximate
Edge exclusion is used, so effective
diameter D is smaller
For d=1cm,
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D=100mm (4”), N=56 (exact 55)
D=150mm (6”), N=143
D=200mm (8”), N=269
D=300mm (12”), N=640 (exact 626)
For d=1mm
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–
–
–
D=100mm (4”), N=7631
D=150mm (6”), N=17338
D=200mm (8”), N=30972
D=300mm (12”), N=70019 (exact 7064)
Die
Typical sizes: 15mm x 15 mm, 1cm x 1cm
0.5cm x 0.5cm, min ~1mm x 1mm
Dan O. Popa, Intro to EE, Spring 2015
Wafer
Example: Electronic Package
• Dual in-line package
(DIP)
• Pin grid array
• Ball grid array
Electrical
• Quad package
Interconnects
• Thin package
• Lead on chip
• Chip on board
Silicon Die
Dan O. Popa, Intro to EE, Spring 2015
Manufacturing Process (example)
Process
Example of outcome
Micromachining
Silicon wafer
Dicing
Silicon die
Molding etc.
Metal / plastic house
Packaging
System
Testing
High Yield
Systems integration Product
Die accounts for only ~ 10-70% of system cost
Concurrent development required
Dan O. Popa, Intro to EE, Spring 2015
Dan O. Popa, Intro to EE, Spring 2015
Scaling Effects
• Changes in physics of evolution as parts scale down in size.
• Some effects common in nature: quick cooling of Al foil, formation of
small droplets of water, electrostatic sticking of hair or small particles,
suspension of snow flakes or dust in air.
• Volumetric effects (e.g. mass, gravity), replaced by surface effects
(e.g. electrostatic attraction, van-der-Waals force).
• Describe physics as a function of dimensional scale length (L or D).
• Sphere of radius r – surface vs. volume:
4 3
V  r
3
Dan O. Popa, Intro to EE, Spring 2015
S  4r
2
V r
 , r  1  V  S
S 3
Dominant forces
Dan O. Popa, Intro to EE, Spring 2015
Continuum Mechanics
•
•
Continuum hypothesis: Variables such as temperature, displacement, force
are continuous functions of time (t), position vector (xR³), and outside
stimulus (u).
This hypothesis breaks down as physical dimension decreases. Example:
density/structure of material:
Solid block
m, cm, mm
Crystal structure
10 µm, 1µm
Molecules, Atoms
10nm 1nm 1Å
matom
4 3
M (r ) N (r ) * matom
V  r ,  (r ) 

,  (r )  const , if
 1
3
V (r )
V (r )
r3
Dan O. Popa, Intro to EE, Spring 2015
IC Fab
•
•
Si was first used to make IC semiconductors, but it
can also be used for MEMS. First MEMS devices
were thin structures constructed using IC fab
technlogy in the early 1980’s.
Thin films are grown on these substrates and are
used to build active components, passive
components, and interconnections between circuits:
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–
–
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(1) epitaxial Si
(2) SiO2
(3) silicon nitride (Si3N4)
(4) polycrystalline Si (polysilicon)
(5) metal films.
Si is a semiconductor. To change it’s conduction
properties locally (for instance to create n or p
junctions, or to decrease the resistance of MEMS
structures) doping is used using atoms like boron or
phosphorus. Doping includes thermal diffusion (in an
annealing furnace) or ion implantation (FIB).
Lithography is used to transfer a pattern from a mask
to a film via a photosensitive chemical called a
photoresist. The film is then selectively etched away,
leaving the desired pattern in the film. This cycle is
repeated until fabrication is complete.
Dan O. Popa, Intro to EE, Spring 2015
Resists
•
Photoresists can be categorized as:
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Positive (Exposure to UV weakens links - PMMA, DQN), or negative
(photo cross-links strenghtens the polymers – two component rubber
resists).
Thin (0.5-2.5µm) or thick (10 – 750 µm, Su-8, Polymide, DiaPlate)
It is sensitive to UV light, usually 150-450nm, 10-100mJ/cm2.
Resists are also exposed to X-Rays (in LIGA for instance), or to Ebeam energy.
Film thickness T is set by spinning at high RPM, usually 1500-8000
RPM, where C is the polymer concentration, µ is the viscosity, and ω
is the RPM. An alternative to spinning is resist spray coating.
Prior to spinning, wafers should be cleaned using wet chemistry
(RCA, Piranha), or by supercritical CO2, to remove organics,
particles, metals, etc.
They should have 0.5% uniform thickness across the wafer, and high
glass transition temperature Tg (above which is it no longer a rubber
and can’t be easily removed).
Resist contains solvents that need to be removed. Stress is relieved
and adhesion is improved by postbaking (after spinning.
Resist is remove by wet stripping (in acetone for instance), or by dry
stripping using oxygen plasma (ashing).
Dan O. Popa, Intro to EE, Spring 2015
T
KC   

Photolithography
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Contact lithography can create features finer
than 1µm, but is not suited for mass
production.
Proximity lithography – no wear of mask, but
Fresnel diffraction on a 20-50 µm gap adds
a few µm to minimum feature sizes.
Projection lithography has the best
resolution (0.5 µm). 5:1 or 10:1 reduction
lenses are used. Stepping over the whole
wafer with the mask is necessary.
Photomasks can be hard (made of UV
transparent glass or Quartz), or soft
(transparency film).
VLSI uses hard masks. Soft transparency
films are used for quick prototyping and
when the feature sizes are above 1µm (as in
the case of MEMS).
E-beam lithography can be used to make
masks.
Contact lithography is also called “shadow
masking”, and can also be used in
sputtering/evaporation.
Structures have aspect ratio 1:1 or 2:1. Grey
tone lithography can be used to make
tapered microstructures.
Dan O. Popa, Intro to EE, Spring 2015
Theoretical resolutions (min dimension):
3
T
Contact and Proximity – s is gap
R
 (s  )
between mask and wafer, T is PR
2
2
thickness.
Increasing Resolution
•
•
Extreme UV lithography – down to λ=10nm – can print with R below 100nm,
at 0.5 µm DoF. Sources are Laser plasmas, or synchrotrons (EUV=soft Xray). Special optics, masks and vacuum needed.
X-Ray Lithography – wavelengths around 1nm. No optics are used
(proximity printing). With a proximity gap of 25µm, 150nm features can be
resolved. But since no image reduction is possible, masks are very
expensive (can use E-beam to make them).
– LIGA – uses a synchrotron (accelerated electrons to create X-rays).
– Use a synchrotron to resolve the “blurring” problem, R=sd/D, s – mask wafer
gap, d – source diameter, D – source to substrate distance. To reduce R,
increase D, thus decreasing the incident energy or decrease d – both possible
with a synchrotron, but not feasible with a e-beam slammed into a target.
•
•
Electron beam Lithography – use a an electron source to expose resist, but
requires vacuum, slow speed (hours), high cost, but 10nm resolutions are
possible.
Nano/Micro imprint (or “soft” Lithography) – based on contact molding of
resist, completely different technology, but has promise to replace
conventional lithography.
Dan O. Popa, Intro to EE, Spring 2015
Dry Etching
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Dry etching has been traditionally introduced
in Si MEMS as a result of thin film
Semiconductor IC fab processes.
See table 2.1 Madou for a classification of
all subtractive removal processes.
Thin-film dry etching is plasma or ion-beam
assisted. Ion-milling induces sputter etching.
Plasmas (discharges) are created in low
pressure chambers using DC electric field
(Avalanche breakdown in low vacuum
(10mTorr)– see Pachen’s law V=f(Pd)), RF
field (RF coupled vibration energy at
40mTorr, 13.56 MHz, kW).
Electron densities control the etch rates.
Selectivity of etch is defined as the ratio
between mask etch rate and substrate etch
rate.
Plasma dissociates molecules of gas
present, turning them into radicals. These
radicals then etch material – “Reactive Ion
Etching” – RIE. This effect can also be used
for deposition (PECVD).
Etchants: CF4, O2, SF6, C2F6, BCl3, etc.
F/C ratio (fluorine to carbon) ratio controls
etching and polymerization.
Dan O. Popa, Intro to EE, Spring 2015
New inductively coupled plasma sources achieve
much higher electron densities (1012/cm3).
Using flourine gasses, Si etches much faster 6µm/min,
150:1 etch selectivity Si:SiO2, aspect ratios 10:1,
and 250 µm depths (Deep reactive Ion Etch – DRIE).
Thin-film deposition
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There are several main methods to
deposit thin layers of materials:
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Examples of uses:
LPCVD for growth of polysilicon:
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Spinning (sol-gel, resist, etc).
CVD – chemical vapor deposition, with
many variants (LPCVD, PECVD, ebeam,
PLD, etc.)
Sputtering deposition
Thermal deposition (for instance SiO2).
Other: screen printing, electroplating
Polycrystalline silicon is deposited from
silane (SiH4). This reaction is usually
performed in LPCVD systems, with either
pure silane feedstock, or a solution of
silane with 70-80% nitrogen.
Temperatures between 600 and 650 °C
and pressures between 25 and 150 Pa
yield a growth rate between 10 and 20 nm
per minute.
Sputtering or evaporation of metals using
targets and crucibles.
Dan O. Popa, Intro to EE, Spring 2015
Deposition and Lift-off
Dan O. Popa, Intro to EE, Spring 2015
Wet Chemical Etching
Dan O. Popa, Intro to EE, Spring 2015
Nonlinear Circuit Elements- Diode
Dan O. Popa, Intro to EE, Spring 2015
Image Sources: Internet
Nonlinear Circuit Elements- Transistor
Dan O. Popa, Intro to EE, Spring 2015
Image Sources: Textbook
Transistor use: Digital Inverter
Dan O. Popa, Intro to EE, Spring 2015
Image Sources: Textbook
Solar cells - PN Junction using PV effect
• Sunlight strikes the cell, photons with energy above
the semiconductor bandgap impart enough energy to
create electron-hole pairs.
A typical silicon PV cell is composed of
a thin wafer consisting of an ultra-thin
layer of phosphorus-doped (N-type)
silicon on top of a thicker layer of borondoped (P-type) silicon.
• This separation induces a fixed electric current and
voltage in the device. The electricity is collected and
transported by metallic contacts on the top and bottom
surfaces of the cell.
When sunlight strikes the surface of a
PV cell, this electrical field provides
momentum and direction to lightstimulated electrons, resulting in a flow
of current when the solar cell is
connected to an electrical load
Dan O. Popa, Intro to EE, Spring 2015
Source: MIT Solar Decathlon
Solar cells – material and efficiency
•silicon (Si),
•gallium arsenide
(GaAs),
•cadmium
telluride (CdTe),
•copper indium
diselenide (CIS),
•hydrogenated
amorphous
silicon.
Dan O. Popa, Intro to EE, Spring 2015
Source: MIT Solar Decathlon
PV Cells, Modules, Arrays
In the case of a single-junction device, the
efficiency of the solar cell, the ratio of the
power produced, and the incident light
power are limited.
Photons with energies below the bandgap of
the material produce only heat. Excess
energy above that needed to generate
electron-hole pairs also produces heat.
Power – [W]
Efficiency= Electrical Power/Sun Power
Power density – W/m2 – Irradiance (Flux)
Energy – Wh
Photovoltaic cells are connected electrically in series and/or parallel
circuits to produce higher voltages, currents and power levels.
Photovoltaic modules consist of PV cell circuits sealed in an
environmentally protective laminate, and are the fundamental
building block of PV systems.
Photovoltaic panels include one or more PV modules assembled
as a pre-wired, field-installable unit. A photovoltaic array is the
complete power-generating unit, consisting of any number of PV
modules and panels.
Dan O. Popa, Intro to EE, Spring 2015
Source: MIT Solar Decathlon
PV Power
Sun Power – [W]
Power density – W/m2
– Irradiance (Flux)
Image Sources: http://www.nrel.gov/gis/solar.html, Wikipedia
Dan O. Popa, Intro to EE, Spring 2015
PV Systems
Subsystems:
DC-AC power inverter,
battery bank,
system and battery controller,
auxiliary energy sources
specified electrical load (appliances).
Direct Coupled PV System
Dan O. Popa, Intro to EE, Spring 2015
Source: MIT Solar Decathlon
The Operational Amplifier
The op amp is built using VLSI techniques. The circuit
diagram of an LM 741 from TI is
shown below.
Vp(+)
Taken from TI
data sheet as
shown on the
web.
Vn(-)
Vcc+
Vo
VccDan O. Popa, Intro to EE, Spring 2015
D/A and A/D conversion
Dan O. Popa, Intro to EE, Spring 2015
Digital to Analog Converter (DAC)
n=4, G=-0.5
Dan O. Popa, Intro to EE, Spring 2015
Digital to Analog Converter (DAC)
and the Process of Sampling
Dan O. Popa, Intro to EE, Spring 2015
Analog to Digital Converter using a DAC
Dan O. Popa, Intro to EE, Spring 2015
Analog to Digital Converter (ADC)
Sample and Hold Circuit
Dan O. Popa, Intro to EE, Spring 2015
Texas Instruments MSP430 LaunchPad
•
The LaunchPad development
board features:
– 14-/20-pin DIP (N) socket
– Built-in flash emulation for
debugging and programming
– 2 programmable LEDs
– 1 power LED
– 1 programmable button
– 1 reset button
•
•
Includes one mini USB cable to
interface with a PC.
MSP430G2553IN20 – 16kB
Flash, 512B RAM, interruptible
GPIOs (capacitive sensecapable), 16-bit timers, 8ch 10bit ADC, Comparator, Serial
Communication (USCI – I2C,
SPI & UART) & more
Dan O. Popa, Intro to EE, Spring 2015
Programming Constructs
Data Types
- Primitives (Integer, Float, etc)
- Const, Var, Pointer
- Complex (Lists, arrays, etc.)
- Register values (tied to hardware)
- Timer (clocks, tied to hardware)
Operations on data
- +, - , =, etc.
Control Statements
- If, case (conditional)
- While, For (loops)
Function calls
- User defined
- Main ()
- MSP 430 specific: ex. ConfigureADC
35
Microcontroller Programming in C
(Labs 10,11,12)
while(1)
{
ADC10CTL0 |= ENC + ADC10SC;
__delay_cycles(10000);
adcval = ADC10MEM;
// Enable conversion and start conversion
// Delay 10000 clock cycle to allow ADC to settle
// Store ADC sampled value
if (adcval < 380) // Based on sensor input to ADC, determine which pin to turn on. These values were determined
{
// by calibrating the sensor prior to the lab. P1.0 = force < 1/2 lb, P1.1 = 1/2 lb. < force < 1 lb.
if (adcval < 205)
// P1.2 = force > 1 lb.
{
P1OUT = 0x01;
}
else
{
P1OUT = 0x02;
}
}
else
{
P1OUT = 0x04;
}
}
Dan O. Popa, Intro to EE, Spring 2015
Next Time: Op Amps
Dan O. Popa, Intro to EE, Spring 2015
37