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Transcript
Static CMOS Logic 1 CMOS Circuit Styles Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path high noise margins - full rail to rail swing - VOH and VOL are at VDD and GND, respectively low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 2 Static Complementary CMOS Pull-up network (PUN) and pull-down network (PDN) VDD PMOS transistors only In1 In2 PUN InN In1 In2 InN pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1 F(In1,In2,…InN) PDN pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0 NMOS transistors only PUN and PDN are dual logic networks 3 Threshold Drops VDD PUN VDD S D VDD D 0 VDD VGS S CL VDD 0 PDN D VDD S CL 0 VDD - VTn CL VGS VDD |VTp| S CL D 5 Construction of PDN NMOS devices in series implement a NAND function A•B A B NMOS devices in parallel implement a NOR function A+B A B 6 Dual PUN and PDN PUN and PDN are dual networks DeMorgan’s theorems A+B=A•B [!(A + B) = !A • !B or !(A | B) = !A & !B] A•B=A+B [!(A • B) = !A + !B or !(A & B) = !A | !B] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) Number of transistors for an N-input logic gate is 2N 7 CMOS NAND A A B F 0 0 1 0 1 1 1 0 1 1 1 0 B A•B A B A B 8 CMOS NOR B A A+B A A B F 0 0 1 0 1 0 1 0 0 1 1 0 B A B 9 Complex CMOS Gate B A C D OUT = !(D + A • (B + C)) A D B C 11 Standard Cell Layout Methodology Routing channel VDD signals GND What logic function is this? 12 OAI21 Logic Graph X A j C C B X = !(C • (A + B)) C A PUN i i X B VDD j B A B C GND A PDN 13 Two Stick Layouts of !(C • (A + B)) A C B A B C VDD VDD X X GND GND uninterrupted diffusion strip 14 Consistent Euler Path An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i X B VDD j GND A A B C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) 16 OAI22 Logic Graph A C B D X D X = !((A+B)•(C+D)) C D A B C VDD X B A B C D PUN A GND PDN 17 OAI22 Layout A B D C VDD X GND Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!) 18 XNOR/XOR Implementation XNOR XOR A A AB B A B B AB A B AB How many transistors in each? Can you create the stick transistor layout for the lower left circuit? AB 19 VTC is Data-Dependent 0.5/0.25 NMOS 0.75 /0.25 PMOS 3 A M3 B M4 2 A,B: 0 -> 1 B=1, A:0 -> 1 A=1, B:0->1 F= A • B D A S D B M1 VGS1 = VB 1 M2 VGS2 = VA –VDS1 S weaker PUN Cint 0 0 1 2 The threshold voltage of M2 is higher than M1 due to the body effect () VTn1 = VTn0 VTn2 = VTn0 + ((|2F| + Vint) - |2F|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint 20 Static CMOS Full Adder Circuit !Cout = !Cin & (!A | !B) | (!A & !B) !Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin) B A B B A Cin A B Cin Cin !Cout !Sum A A B B A Cin A B Cin A B Cout = Cin & (A | B) | (A & B) Sum = !Cout & (A | B | Cin) | (A & B & Cin) 22