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Introduction to CMOS VLSI Design Lecture 1: History & Layout Salman Zaffar Iqra University, Karachi Campus Spring 2012 Slides from D. Harris, Harvey Mudd College USA A Brief History 1958: First integrated circuit – Flip-flop using two transistors – Built by Jack Kilby at Texas Instruments 2003 – Intel Pentium 4 mprocessor (55 million transistors) – 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years – No other technology has grown so fast so long Driven by miniaturization of transistors – Smaller is cheaper, faster, lower in power! – Revolutionary effects on society Lecture 1 CMOS VLSI Design Slide 2 Annual Sales 1018 transistors manufactured in 2003 – 100 million for every human on the planet Global Semiconductor Billings (Billions of US$) 200 150 100 50 0 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 Year Lecture 1 CMOS VLSI Design Slide 3 Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor – John Bardeen and Walter Brattain at Bell Labs – Read Crystal Fire by Riordan, Hoddeson Lecture 1 CMOS VLSI Design Slide 4 Transistor Types Bipolar transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors – nMOS and pMOS MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration Lecture 1 CMOS VLSI Design Slide 5 MOS Integrated Circuits 1970’s processes usually had only nMOS transistors – Inexpensive, but consume power while idle Intel 1101 256-bit SRAM Intel 4004 4-bit mProc 1980s-present: CMOS processes for low idle power Lecture 1 CMOS VLSI Design Slide 6 Moore’s Law 1965: Gordon Moore plotted transistor on each chip – Fit straight line on semilog scale – Transistor counts have doubled every 26 months 1,000,000,000 Integration Levels 100,000,000 10,000,000 Transistors Intel486 1,000,000 Pentium 4 Pentium III Pentium II Pentium Pro Pentium Intel386 10 gates MSI: 1000 gates 80286 100,000 SSI: 8086 10,000 8080 LSI: 8008 4004 1,000 1970 1975 1980 1985 1990 1995 2000 10,000 gates VLSI: > 10k gates Year Lecture 1 CMOS VLSI Design Slide 7 Corollaries Many other factors grow exponentially – Ex: clock frequency, processor performance 10,000 4004 1,000 8008 Clock Speed (MHz) 8080 8086 100 80286 Intel386 Intel486 10 Pentium Pentium Pro/II/III Pentium 4 1 1970 1975 1980 1985 1990 1995 2000 2005 Year Lecture 1 CMOS VLSI Design Slide 8 Fabrication Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication Rest of the course: How to build a good CMOS chip Lecture 1 CMOS VLSI Design Slide 9 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Lecture 1 Si Si Si Si Si Si Si Si Si CMOS VLSI Design Slide 10 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Lecture 1 Si Si Si Si Si Si As Si Si B Si Si Si Si Si - + + - CMOS VLSI Design Si Si Si Slide 11 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction Lecture 1 p-type n-type anode cathode CMOS VLSI Design Slide 12 nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor Source Gate Drain Polysilicon – Even though gate is SiO2 no longer made of metal n+ n+ p Lecture 1 CMOS VLSI Design bulk Si Slide 13 nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF Source Gate Drain Polysilicon SiO2 0 n+ n+ S p Lecture 1 D bulk Si CMOS VLSI Design Slide 14 nMOS Operation Cont. When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO2 1 n+ n+ S p 0: Introduction D bulk Si CMOS VLSI Design Slide 15 pMOS Transistor Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO2 p+ p+ n Lecture 1 CMOS VLSI Design bulk Si Slide 16 Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … Lecture 1 CMOS VLSI Design Slide 17 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain d nMOS pMOS g=1 d d OFF g ON s s s d d d g OFF ON s Lecture 1 g=0 s CMOS VLSI Design s Slide 18 CMOS Inverter A VDD Y 0 1 A A Y Y GND Lecture 1 CMOS VLSI Design Slide 19 CMOS Inverter A VDD Y 0 1 OFF 0 A=1 Y=0 ON A Y GND Lecture 1 CMOS VLSI Design Slide 20 CMOS Inverter A Y 0 1 1 0 VDD ON A=0 Y=1 OFF A Y GND Lecture 1 CMOS VLSI Design Slide 21 CMOS NAND Gate A B 0 0 0 1 1 0 1 1 Y Y A B Lecture 1 CMOS VLSI Design Slide 22 CMOS NAND Gate A B Y 0 0 1 0 1 1 0 1 1 Lecture 1 ON ON Y=1 A=0 B=0 CMOS VLSI Design OFF OFF Slide 23 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 Lecture 1 OFF ON Y=1 A=0 B=1 CMOS VLSI Design OFF ON Slide 24 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 Lecture 1 ON A=1 B=0 CMOS VLSI Design OFF Y=1 ON OFF Slide 25 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 Lecture 1 OFF A=1 B=1 CMOS VLSI Design OFF Y=0 ON ON Slide 26 CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Lecture 1 A B Y CMOS VLSI Design Slide 27 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 Lecture 1 CMOS VLSI Design Slide 28 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 Y A B C Lecture 1 CMOS VLSI Design Slide 29 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Lecture 1 CMOS VLSI Design Slide 30 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors A GND VDD Y SiO2 n+ diffusion n+ n+ p+ p+ n well p substrate nMOS transistor Lecture 1 p+ diffusion polysilicon metal1 pMOS transistor CMOS VLSI Design Slide 31 Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND VDD Y p+ n+ n+ p+ p+ n+ n well p substrate substrate tap Lecture 1 well tap CMOS VLSI Design Slide 32 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND VDD nMOS transistor pMOS transistor well tap substrate tap Lecture 1 CMOS VLSI Design Slide 33 Detailed Mask Views Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal Lecture 1 CMOS VLSI Design Slide 34 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 35 Oxidation Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 36 Photoresist Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light Photoresist SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 37 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 38 Etch Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 39 Strip Photoresist Strip off remaining photoresist – Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step SiO2 p substrate Lecture 1 CMOS VLSI Design Slide 40 n-well n-well is formed with diffusion or ion implantation Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si SiO2 n well Lecture 1 CMOS VLSI Design Slide 41 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps n well p substrate Lecture 1 CMOS VLSI Design Slide 42 Polysilicon Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Polysilicon Thin gate oxide n well p substrate Lecture 1 CMOS VLSI Design Slide 43 Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide n well p substrate Lecture 1 CMOS VLSI Design Slide 44 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact n well p substrate Lecture 1 CMOS VLSI Design Slide 45 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing n+ Diffusion n well p substrate Lecture 1 CMOS VLSI Design Slide 46 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ n well p substrate 0: Introduction CMOS VLSI Design Slide 47 N-diffusion cont. Strip off oxide to complete patterning step n+ n+ n+ n well p substrate Lecture 1 CMOS VLSI Design Slide 48 P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ n well p substrate Lecture 1 CMOS VLSI Design Slide 49 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate Lecture 1 CMOS VLSI Design Slide 50 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal Metal Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate Lecture 1 CMOS VLSI Design Slide 51 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain – Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 – E.g. l = 0.3 mm in 0.6 mm process Lecture 1 CMOS VLSI Design Slide 52 Simplified Design Rules Conservative rules to get you started Lecture 1 CMOS VLSI Design Slide 53 Inverter Layout Transistor dimensions specified as Width / Length – Minimum size is 4l / 2l, sometimes called 1 unit – In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long Lecture 1 CMOS VLSI Design Slide 54 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! Lecture 1 CMOS VLSI Design Slide 55