Download DIGITAL CONTROL OF VOLTAGE REGULATORS FOR FAST

DIGITAL CONTROL OF VOLTAGE REGULATORS FOR FAST
TRANSIENT RESPONSE IN COMPUTER APPLICATIONS
by
WENNAN GUO
A thesis submitted to the Department of Electrical and Computer Engineering
In conformity with the requirements for
the degree of Doctor of Philosophy
Queen’s University
Kingston, Ontario, Canada
(April, 2010)
Copyright © Wennan Guo, 2010
ABSTRACT
In this thesis, three techniques are proposed to enhance the transient performance of
voltage regulators (VR) for computer applications.
Voltage mode control with load line positioning and phase current balancing
technique is first introduced to maximize the transient response of the VR and to balance
the phase current for multiphase VR under high frequency dynamic load conditions. The
VR and its control method is modeled and analyzed in depth for its targeting applications.
Secondly, a predictive non-linear voltage mode control method is digitally
implemented to further enhance the transient response of the VR. The proposed control
method enables the VR to operate at a lower switching frequency in the 250KHz range for
higher efficiency during steady state operation but to respond quickly accordingly to
transient events when necessary. This control technique allows the use of simple VR
topologies and can reduce the number of bulk capacitors.
Thirdly, a VR with Transient Circuit and digitally implemented non-linear control
is introduced to greatly enhance the transient response of the VR. The proposed control
method allows the VR to operate at a lower switching frequency in the 250KHz range for
higher efficiency under static load condition, but to respond even quickly with the aid of
the Transient Circuit upon large load steps. This method allows the use of simple VR
topologies and can potentially remove all the bulk capacitors.
In the thesis, theoretical analysis, simulations, and experiments are given to
describe and verify the proposed techniques.
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ACKNOWLEDGEMENT
I wish to express my deep gratitude to my supervisor Dr. Praveen K. Jain for his
invaluable guidance, advice and financial support throughout the course of this work.
I would like to thank all my colleagues of ePOWER (Centre for Energy and Power
Electronics Research Laboratory) at Queen’s University for their support and friendship.
I would also like to express my thanks to CHiL Semiconductor Inc. to support
experimental work presented in this thesis during my employment between September,
2005 and August, 2007.
I would also greatly appreciate Canada Graduate Scholarships (CGS D) program
by Natural Sciences and Engineering Research Council (NSERC) of Canada, Ontario
Graduate Scholarship (OGS) program, and Queen’s University Queen’s Graduate Award
(QGA) program for their financial support, which greatly inspired and encouraged me to
challenge the difficulties in engineering world.
Finally, I would like to express my thanks to my wife Xin Zhang and our parents
for their love, support and sacrifices during these years.
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TABLE OF CONTENTS
ABSTRACT ....................................................................................................................................... i ACKNOWLEDGEMENT .....................................................................................................................ii TABLE OF CONTENTS .................................................................................................................... iii LIST OF FIGURES ............................................................................................................................ vi LIST OF TABLES ............................................................................................................................ xv LIST OF ACRONYMS ..................................................................................................................... xvi LIST OF PRINCIPAL SYMBOLS ...................................................................................................... xix CHAPTER 1 GENERAL INTRODUCTION .................................................................. 1 1.1 BACKGROUND ........................................................................................................................... 1 1.1.1 Brief Introduction to Voltage Regulator ........................................................................... 1 1.1.2 Challenges in Powering the Future Microprocessors....................................................... 3 1.2 TECHNICAL REVIEW OF EXISTING SOLUTIONS ......................................................................... 6 1.2.1 Output Capacitors of Voltage Regulator........................................................................... 6 1.2.2 Output Inductors of Voltage Regulator ............................................................................. 7 1.2.3 Multiphase Interleaved Topology ...................................................................................... 8 1.2.4 Switching at Higher Frequency ......................................................................................... 9 1.2.5 Intermediate Stage Linear Regulation............................................................................. 12 1.2.6 Current Mode Control and Voltage Mode Control ......................................................... 14 1.2.7 Load Current Feed-Forward Control ............................................................................. 16 1.2.8 V2 Control and Its Enhanced Version ............................................................................. 17 1.2.9 Non-Linear Hysteresis Control ....................................................................................... 18 1.2.10 Coupled Inductor Approach .......................................................................................... 18 1.3 OBJECTIVES OF THE THESIS .................................................................................................... 20 1.4 OUTLINE OF THE THESIS ......................................................................................................... 21 CHAPTER 2 MODELING AND ANALYSIS OF MULTIPHASE VOLTAGE
REGULATOR FOR HIGH FREQUENCY DYNAMIC LOAD .................................. 23 2.1 INTRODUCTION ....................................................................................................................... 23 2.2 GENERAL REQUIREMENT ON VR’S TRANSIENT RESPONSE .................................................... 25 2.3 DESCRIPTION OF THE MULTIPHASE VOLTAGE MODE CONTROLLED VR............................... 28 2.4 MODELING OF THE MULTIPHASE VR...................................................................................... 31 2.4.1 State Space Description of the Multiphase VR ................................................................ 31 2.4.2 Small Signal Model of the VR.......................................................................................... 32 iii
2.4.3 Average Modeling of VR ................................................................................................. 34 2.5 CLOSED LOOP TRANSFER FUNCTIONS .................................................................................... 35 2.5.1 Closed Loop Transfer Function of Output Voltage ......................................................... 35 2.5.2 Closed Loop Transfer Function of Phase Current .......................................................... 35 2.5.3 Closed Loop Transfer Function of Output Impedance .................................................... 36 2.5.4 Closed Loop Transfer Function of Line Rejection .......................................................... 36 2.5.5 Closed Loop Transfer Function of Noise Rejection ........................................................ 36 2.6 DESIGN FOR HIGH FREQUENCY DYNAMIC LOADS ................................................................. 37 2.6.1 Output Voltage Regulation .............................................................................................. 37 2.6.2 Phase Current Balancing ................................................................................................ 37 2.6.3 Minimizing Beat Frequency Effect .................................................................................. 39 2.6.4 Load Line Positioning ..................................................................................................... 43 2.7 LOOP DESIGN APPROACHES AND ITS VALIDATION ................................................................ 45 2.7.1 Voltage Control Loop ...................................................................................................... 46 2.7.2 Phase Current Balancing Loop ....................................................................................... 49 2.7.3 Output Impedance and Load Line ................................................................................... 50 2.7.4 Line Rejection .................................................................................................................. 52 2.7.5 Noise Rejection ................................................................................................................ 52 2.8 EFFECT OF LOAD MODEL........................................................................................................ 53 2.9 SIMULATION RESULTS ............................................................................................................ 55 2.10 SUMMARY ............................................................................................................................. 61 CHAPTER 3 VOLTAGE REGULATOR WITH DIGITALLY IMPLEMENTED
NON-LINEAR VOLTAGE MODE CONTROL ........................................................... 62 3.1 INTRODUCTION ....................................................................................................................... 62 3.2 PREDICTIVE NON-LINEAR VOLTAGE MODE CONTROL .......................................................... 63 3.2.1 Operation of the Non-Linear Voltage Mode Control ...................................................... 63 3.2.1.1 Normal Steady State Mode ............................................................................................. 68 3.2.1.2 Transient-Up Mode ......................................................................................................... 69 3.2.1.3 Transient-Down Mode .................................................................................................... 71 3.2.2 Prediction for Non-Linear Operation ............................................................................. 72 3.2.2.1 Frequency Domain Model of the VR for Prediction ....................................................... 74 3.2.2.2 Theoretical Calculation for Prediction ............................................................................ 75 3.2.3 Non-Linear Control and Switching Frequency ............................................................... 78 3.3 DIGITAL IMPLEMENTATION OF THE CONTROL ....................................................................... 81 3.3.1 Architecture of the Digital Controller ............................................................................. 81 iv
3.3.2 Digital Compensation for Normal Steady State Mode .................................................... 83 3.3.3 Control Algorithm for Transient Modes .......................................................................... 88 3.3.4 Control Algorithm for Light Load Mode ......................................................................... 90 3.4 OUTPUT OVERSHOOT ANALYSIS ............................................................................................ 91 3.5 POWER LOSS ANALYSIS OF LINEAR AND NON-LINEAR OPERATION ...................................... 98 3.5.1 Power Loss Analysis under Static Load Condition ......................................................... 98 3.5.2 Power Loss Analysis under High Frequency Dynamic Load Condition ....................... 102 3.6 SIMULATION RESULTS .......................................................................................................... 104 3.6.1 Single Load Step Simulation Results ............................................................................. 104 3.6.2 Load Oscillation Simulation Results ............................................................................. 110 3.7 EXPERIMENTAL RESULTS ..................................................................................................... 116 3.8 SUMMARY ............................................................................................................................. 119 CHAPTER 4 VOLTAGE REGULATOR WITH TRANSIENT CIRCUIT AND
DIGITAL CONTROLLER ............................................................................................ 120 4.1 INTRODUCTION ..................................................................................................................... 120 4.2 TOPOLOGY OF THE VR AND TRANSIENT CIRCUIT ................................................................ 122 4.3 OPERATION MODES OF THE VR WITH TRANSIENT CIRCUIT ................................................. 123 4.3.1 Normal Steady State Mode ............................................................................................ 123 4.3.2 Transient-Up Mode ....................................................................................................... 123 4.3.3 Transient-Down Mode................................................................................................... 129 4.4 DIGITAL IMPLEMENTATION OF THE CONTROLLER ............................................................... 132 4.4.1 Architecture of the Digital Controller ........................................................................... 132 4.4.2 Control Algorithm for Transient Modes ........................................................................ 134 4.5 OUTPUT OVERSHOOT ANALYSIS .......................................................................................... 135 4.6 POWER LOSS ANALYSIS ........................................................................................................ 141 4.7 SIMULATION RESULTS .......................................................................................................... 145 4.7.1 Single Load Step Simulation Results ............................................................................. 145 4.7.2 Load Oscillation Simulation Results ............................................................................. 151 4.8 EXPERIMENTAL RESULTS ..................................................................................................... 156 4.9 SUMMARY ............................................................................................................................. 160 CHAPTER 5 CONCLUSIONS AND SUMMARY ...................................................... 161 REFERENCES ................................................................................................................ 164 v
LIST OF FIGURES
Fig. 1-1 Synchronous Buck Converter for Voltage Regulation (VR) ................................................. 2 Fig. 1-2 Multiphase Interleaved buck converter ................................................................................. 2 Fig. 1-3 Physical image of an actual Voltage Regulator (VR) down on an Intel motherboard .......... 3 Fig. 1-4 Estimated required output capacitance as a function of load current .................................... 7 Fig. 1-5 Current ripple canceling effect .............................................................................................. 8 Fig. 1-6 Step responses of a VR switching at different frequency (1.5Vdc/25A output)................... 10 Fig. 1-7 Estimated efficiency versus switching frequency for CCM and DCM operation modes
(Based on 1.5Vdc/25A output condition) .............................................................................. 11 Fig. 1-8 Intermediate Linear Regulator solution ............................................................................... 13 Fig. 1-9 Block diagram of current mode control .............................................................................. 14 Fig. 1-10 100% load step responses of current mode and voltage mode control (1.5Vdc/25A) ........ 15 Fig. 1-11 Small signal block diagram of load current feed-forward control method........................ 16 Fig. 1-12 Small signal block diagram of enhanced V2 control method ............................................ 17 Fig. 1-13 Multiphase coupled inductor VR ...................................................................................... 19 Fig. 2-1 Time domain ideal waveform of voltage response under Intel’s load line operation ......... 25 Fig. 2-2 Intel’s frequency domain AC load line impedance ZLL ....................................................... 26 Fig. 2-3 Voltage mode controlled 4-phase VR with load line positioning and phase current
balancing............................................................................................................................... 29 Fig. 2-4 Intel’s LGA775 socket load line window for design consideration
(775_VR_CONFIG_04B) .................................................................................................... 30 Fig. 2-5 Complete small signal model with load line positioning and phase current balancing ....... 32 Fig. 2-6 Average model of the VR .................................................................................................... 34 Fig. 2-7 Waveforms of current without balancing ............................................................................ 37 Fig. 2-8 Waveforms of phase current balanced ................................................................................ 37 Fig. 2-9 Current balanced at static load of 20A and 120A respectively under low bandwidth design
at 1kHz.................................................................................................................................. 38 Fig. 2-10 Phase current balanced at static load of 20A but unbalanced at 20A-120A/100kHz load
oscillation due to low bandwidth design at 1kHz ................................................................. 38 vi
Fig. 2-11 High amplitude phase current oscillation due to beat frequency effect under low
bandwidth design at 1kHz (fsw=250kHz, fload=240kHz)........................................................ 39 Fig. 2-12 Frequency spectrum of phase current waveforms in Fig. 2-11 with high amplitude beat
frequency oscillation at 10kHz ............................................................................................. 40 Fig. 2-13 Schematic of a notch filter................................................................................................. 41 Fig. 2-14 Beat frequency effect of 1kHz bandwidth design reduced by adding notch filtering ....... 41 Fig. 2-15 Phase current balanced waveforms (fsw=250kHz, fload=240kHz, BW=50kHz) ................. 42 Fig. 2-16 Frequency spectrum of phase currents in Fig. 2-15 with beat frequency effect minimized
at 10kHz................................................................................................................................ 42 Fig. 2-17 Beat frequency effect further reduced with high bandwidth design and notch filtering
(fsw=250kHz, fload=240kHz, BW=50kHz) ............................................................................. 43 Fig. 2-18 Load line positioning waveforms: (a) ideal waveforms of VREF and VCC; (b) ideal
waveform of VREF and actual response of VCC; (c) waveforms of reshaped VREF and
improved response of VCC ..................................................................................................... 44 Fig. 2-19 Gain and phase plots of voltage loop ................................................................................ 47 Fig. 2-20 Gain and phase plots of closed loop transfer function of voltage loop ( v~CC / v~vid ) .......... 48 Fig. 2-21 Gain and phase plots of closed loop transfer function v~CC / v~ref when v~vid  0 .............. 48 Fig. 2-22 Gain and phase plots of current balancing loop ................................................................ 49 Fig. 2-23 Gain and phase plots of closed loop transfer functions of current balancing loop ............ 50 Fig. 2-24 Open loop and closed loop output impedance ................................................................... 51 Fig. 2-25 Comparison of closed loop output impedance for different load line resistance .............. 51 Fig. 2-26 Closed loop line rejection of the VR for RLL=0 and RLL=1mΩ ......................................... 52 Fig. 2-27 Closed loop noise rejection of the VR............................................................................... 52 Fig. 2-28 Equivalent circuits of CPU load and parasitic of the motherboard and Socket [42] ......... 53 Fig. 2-29 Output voltage ripple when phase 1-2 and phase 3-4 are grouped together...................... 54 Fig. 2-30 Output voltage ripple when phase 1-3 and phase 2-4 are grouped together...................... 54 Fig. 2-31 Small signal output impedance Zo_closed based on resistive load model ............................. 55 Fig. 2-32 Output voltage response upon load transients at 5A-120A/10kHz (VID=1.2Vdc) ............ 55 Fig. 2-33 Waveforms of balanced phase current upon 20A-120A/10kHz load steps ....................... 56 Fig. 2-34 Waveforms of balanced phase current upon 20A-120A/100kHz load steps ..................... 56 vii
Fig. 2-35 Zoomed-in waveforms of balanced phase current upon 20A-120A/100kHz load steps in
Fig. 2-34 ............................................................................................................................... 57 Fig. 2-36 Frequency spectrum of phase current given in Fig. 3-35 .................................................. 57 Fig. 2-37 Zoomed-in frequency spectrum in Fig. 3-36 ..................................................................... 58 Fig. 2-38 Waveforms of phase current under 120A static load current ............................................ 58 Fig. 2-39 Waveforms of balanced phase current upon 20A-120A/10kHz load steps [ICC: y-axis
5A/div, x-axis 50µs/div] ....................................................................................................... 59 Fig. 2-40 Waveforms of phase current under 120A load condition (Lo1=220nH, Lo3-Lo4=320nH)
[ICC: y-axis 5A/div, x-axis 2µs/div] ...................................................................................... 59 Fig. 2-41 Bode plots of control to output of voltage control loop .................................................... 60 Fig. 2-42 Bode plots of control to output of phase current balancing loop....................................... 60 Fig. 3-1 Transient response of conventional voltage mode control .................................................. 63 Fig. 3-2 Transient response of non-linear voltage mode control during load step up....................... 65 Fig. 3-3 Four-phase interleaved buck converter ............................................................................... 66 Fig. 3-4 Waveforms of the 4-phase VR during Normal Steady State Mode and Transient Modes .. 67 Fig. 3-5 Paths of current flow during Normal Steady State Mode: (a) high side MOSFET is
conducting; (b) low side MOSFET is conducting ................................................................ 69 Fig. 3-6 Paths of current flow during Transient-Up Mode ............................................................... 70 Fig. 3-7 Paths of current flow during Transient-Down Mode: (a) low side MOSFETs are turned on;
(b) low side MOSFETs are turned off .................................................................................. 72 Fig. 3-8 Measured total inductor current and load current................................................................ 73 Fig. 3-9 Brief block diagram of the VR system ................................................................................ 75 Fig. 3-10 Output voltage slope versus load current steps ................................................................. 77 Fig. 3-11 Simulated output voltage step responses of conventional and proposed control method
(fsw=250kHz) ......................................................................................................................... 79 Fig. 3-12 Simulated output voltage step responses of conventional and proposed non-linear control
method (fsw=250kHz and 5MHz) .......................................................................................... 80 Fig. 3-13 Brief block diagram of the proposed digital controller for voltage regulation .................. 81 Fig. 3-14 Architecture of the proposed digital controller IC ............................................................ 83 Fig. 3-15 Digital Compensator of the VR ........................................................................................ 84 viii
Fig. 3-16 Implementation of the Digital Compensator ..................................................................... 85 Fig. 3-17 Bode plots of control to output in continuous and discrete time domain .......................... 86 Fig. 3-18 Bode plots of closed loop of the VR ................................................................................. 86 Fig. 3-19 Root locus plot of control to output................................................................................... 87 Fig. 3-20 Nyquist plot of control to output ....................................................................................... 87 Fig. 3-21 Step response of the VR system ........................................................................................ 88 Fig. 3-22 Flow chart of the control algorithm during Normal Steady State Mode and Transient-Up
Mode ..................................................................................................................................... 89 Fig. 3-23 Flow chart of the control algorithm during Normal Steady State Mode and TransientDown Mode........................................................................................................................... 90 Fig. 3-24 Equivalent circuit of the VR during load release (low side MOSFETs are turned off) .... 91 Fig. 3-25 Output voltage overshoot as a function of time for various phase inductors when low side
MOSFETs are tuned off upon a load release (Co=6×560µF+18×22µF, ICC=100A,
VCC=0.9Vdc) .......................................................................................................................... 94 Fig. 3-26 Current through the body diode of the low side MOSFET as a function of time for
various phase inductance Lo upon load release (Co=6×560µF+18×22µF, ICC=100A,
VCC=0.9Vdc) .......................................................................................................................... 95 Fig. 3-27 Equivalent circuit of the VR during load release (low side MOSFETs are turned on) ..... 95 Fig. 3-28 Output voltage overshoot as a function of time for various phase inductors when low side
MOSFETs are turned on upon a load release (Co=6×560µF+18×22µF, ICC=100A,
VCC=0.9Vdc) .......................................................................................................................... 96 Fig. 3-29 Output voltage upon 100A-5A load current step-down, low side FETs are turned off
(VID=1.0Vdc) [ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis
10µs/div] ............................................................................................................................... 97 Fig. 3-30 Output voltage upon 100A-5A load current step-down, low side FETs are turned on
(VID=1.0Vdc) [ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis
10µs/div] ............................................................................................................................... 97 Fig. 3-31 Power loss composition in high side and low side MOSFETs (ICC=125A) .................... 100 Fig. 3-32 Total power loss distribution among power components (ICC=125A) ............................ 100 Fig. 3-33 Power loss as a function of load frequency ..................................................................... 103 ix
Fig. 3-34 Output voltage waveform upon 30A-125A load current step-up (VID=1.0Vdc) [ICC: y-axis
20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ................................... 105 Fig. 3-35 Output voltage waveform upon 125A-30A load current step-down (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ............................ 105 Fig. 3-36 Output voltage waveform upon 5A-100A load current step-up (VID=1.0Vdc) [ICC: y-axis
20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ................................... 106 Fig. 3-37 Output voltage waveform upon 100A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ............................ 106 Fig. 3-38 Output voltage waveform upon 25A-75A load current step-up (VID=1.0Vdc) [ICC: y-axis
10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] ................................... 107 Fig. 3-39 Output voltage waveform upon 75A-25A load current step-down (VID=1.0Vdc) [ICC: yaxis 10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] ............................ 107 Fig. 3-40 Output voltage waveform upon 5A-55A load current step-up (VID=1.0Vdc) [ICC: y-axis
10A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ................................... 108 Fig. 3-41 Output voltage waveform upon 55A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 10A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ................................ 108 Fig. 3-42 Output voltage waveform upon 5A-10A load current step-up (VID=1.0Vdc) [ICC: y-axis
5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] ..................................... 109 Fig. 3-43 Output voltage waveform upon 10A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] .............................. 109 Fig. 3-44 Output voltage waveform upon 5A-100A/10kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 50µs/div; VCC: y-axis 50mV/div, x-axis 50µs/div] ............................ 110 Fig. 3-45 Output voltage waveform upon 5A-55A/10kHz load oscillation (VID=1.0Vdc) [ICC: y-axis
10A/div, x-axis 100µs/div; VCC: y-axis 50mV/div, x-axis 100µs/div] ............................... 111 Fig. 3-46 Output voltage waveform upon 5A-10A/10kHz load oscillation (VID=1.0Vdc) [ICC: y-axis
5A/div, x-axis 50µs/div; VCC: y-axis 10mV/div, x-axis 50µs/div] ..................................... 111 Fig. 3-47 Output voltage waveform upon 30A-125A/10kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 100µs/div; VCC: y-axis 50mV/div, x-axis 100µs/div] ........................ 112 Fig. 3-48 Output voltage waveform upon 30A-125A/50kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 50µs/div; VCC: y-axis 20mV/div, x-axis 50µs/div] ............................ 112 Fig. 3-49 Output voltage waveform upon 30A-125A/100kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 50µs/div; VCC: y-axis 20mV/div, x-axis 50µs/div] ............................ 113 x
Fig. 3-50 Output voltage waveform upon 30A-125A/250kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div] ................................ 113 Fig. 3-51 Output voltage waveform upon 30A-125A/500kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div] ................................ 114 Fig. 3-52 Output voltage waveform upon 30A-125A/800kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 2µs/div; VCC: y-axis 20mV/div, x-axis 2µs/div] ................................ 114 Fig. 3-53 Output voltage waveform upon 30A-125A/1MHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div] ................................ 115 Fig. 3-54 Prototype board of the VR............................................................................................... 116 Fig. 3-55 Measured step response under 95A/1kHz load condition [VCC: y-axis 50mV/div, x-axis
400µs/div] ........................................................................................................................... 117 Fig. 3-56 Measured output voltage ripple (8mVpp) at 5A load current [VCC: y-axis 10mV/div, x-axis
400µs/div] ........................................................................................................................... 117 Fig. 3-57 Measured output voltage ripple (9mVpp) at 100A load current [VCC: y-axis 10mV/div, xaxis 20µs/div] ..................................................................................................................... 118 Fig. 3-58 Measured efficiency of the prototype .............................................................................. 118 Fig. 4-1 Four-phase VR and transient circuit .................................................................................. 122 Fig. 4-2 Gate patterns of the VR during load step up ..................................................................... 124 Fig. 4-3 Equivalent circuit of the VR with Transient Circuit ......................................................... 125 Fig. 4-4 Current path during Interval I in Transient-Up Mode ....................................................... 126 Fig. 4-5 Current path during Interval II in Transient-Up Mode ...................................................... 126 Fig. 4-6 Current path during Interval III in Transient-Up Mode .................................................... 126 Fig. 4-7 Waveforms of transient circuit and main power circuit in Transient-Up Mode (CCM) ... 127 Fig. 4-8 Waveforms of transient circuit and main power circuit in Transient-Up Mode (DCM) ... 127 Fig. 4-9 Improvement of transient response of a single phase VR at load step-up ......................... 128 Fig. 4-10 Simulated output voltage at 95A load step up ................................................................. 128 Fig. 4-11 Current waveform of transient inductor Lt during Transient-Down Mode ...................... 129 Fig. 4-12 Current path during of Interval I in Transient-Down Mode ............................................ 130 Fig. 4-13 Current path during Interval II in Transient-Down Mode ............................................... 130 Fig. 4-14 Current path during Interval III in Transient-Down Mode .............................................. 130 xi
Fig. 4-15 Simulated output voltage at 95A load step-down............................................................ 131 Fig. 4-16 Brief block diagram of the digital controller with Transient Circuit control .................. 132 Fig. 4-17 Architecture of the digital controller with Transient Circuit control .............................. 133 Fig. 4-18 Flow chart of the control algorithm ................................................................................. 134 Fig. 4-19 Equivalent circuit of the VR during load release ............................................................ 135 Fig. 4-20 Output voltage minus its initial value as a function of Transient Circuit inductance Lt at
load release (Lo=320nH, Co=528µF, ICC=100A, VCC=0.9Vdc) .......................................... 138 Fig. 4-21 Current through transient inductor Lt at load release for various inductance values
(Lo=320nH, Co=528µF, ICC=100A, VCC=0.9Vdc) .............................................................. 138 Fig. 4-22 Current through output capacitor Co at load release for various Lt values (Lo=320nH,
Co=528µF, ICC=100A, VCC=0.9Vdc).................................................................................. 139 Fig. 4-23 Current through the body diode of low side MOSFET in each phase of the main power
circuit at load release for various Lt values (Lo=320nH, Co=528µF, ICC=100A,
VCC=0.9Vdc) ........................................................................................................................ 140 Fig. 4-24 Output voltage maximum overshoot at load step-down (ICC=100A) ............................ 140 Fig. 4-25 Power loss composition in each high side and low side MOSFETs of Transient Circuit
during load oscillation at 5A-100A/40kHz......................................................................... 143 Fig. 4-26 Power loss distribution among power components during load oscillation at 5A100A/40kHz........................................................................................................................ 143 Fig. 4-27 Measured power loss as a function of load frequency (ICC=95A)................................. 144 Fig. 4-28 Output voltage waveform upon 30A-125A load current step-up (VID=1.0Vdc) [ICC: y-axis
20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ....................................... 146 Fig. 4-29 Output voltage waveform upon 125A-30A load current step-down (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ................................ 146 Fig. 4-30 Output voltage waveform upon 5A-100A load current step-up (VID=1.0Vdc) [ICC: y-axis
20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ....................................... 147 Fig. 4-31 Output voltage waveform upon 100A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ............................ 147 Fig. 4-32 Output voltage waveform upon 25A-75A load current step-up (VID=1.0Vdc) [ICC: y-axis
10A/div, x-axis 5µs/div; VCC: y-axis 10mV/div, x-axis 5µs/div] ....................................... 148 xii
Fig. 4-33 Output voltage waveform upon 75A-25A load current step-down (VID=1.0Vdc) [ICC: yaxis 10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] ............................ 148 Fig. 4-34 Output voltage waveform upon 5A-55A load current step-up (VID=1.0Vdc) [ICC: y-axis
10A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ................................... 149 Fig. 4-35 Output voltage waveform upon 55A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 10A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ................................ 149 Fig. 4-36 Output voltage waveform upon 5A-10A load current step-up (VID=1.0Vdc) [ICC: y-axis
5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] ..................................... 150 Fig. 4-37 Output voltage waveform upon 10A-5A load current step-down (VID=1.0Vdc) [ICC: yaxis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div] .............................. 150 Fig. 4-38 Output voltage waveform upon 30A-125A/10kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div] ............................ 152 Fig. 4-39 Output voltage waveform upon 30A-125A/50kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div] ............................ 152 Fig. 4-40 Output voltage waveform upon 30A-125A/100kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div] ............................ 153 Fig. 4-41 Output voltage waveform upon 30A-125A/250kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div] ................................ 153 Fig. 4-42 Output voltage waveform upon 30A-125A/500kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 2µs/div; VCC: y-axis 50mV/div, x-axis 2µs/div] ................................ 154 Fig. 4-43 Output voltage waveform upon 30A-125A/800kHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 2µs/div; VCC: y-axis 50mV/div, x-axis 2µs/div] ................................ 154 Fig. 4-44 Output voltage waveform upon 30A-125A/1MHz load oscillation (VID=1.0Vdc) [ICC: yaxis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div] ............................ 155 Fig. 4-45 Prototype of the VR with Transient Circuit .................................................................... 156 Fig. 4-46 Waveforms of measured output voltage at 95A load step-up (VID=1.0Vdc) [VCC: y-axis
50mV/div, x-axis 4µs/div] .................................................................................................. 157 Fig. 4-47 Waveforms of measured output voltage at 95A load steps (VID=1.0Vdc) [VCC: y-axis
50mV/div, x-axis 4µs/div] .................................................................................................. 157 Fig. 4-48 Measured output voltage at 95A/1kHz load oscillation (VID=1.0Vdc) [VCC: y-axis
50mV/div, x-axis 400µs/div] .............................................................................................. 158 xiii
Fig. 4-49 Measured output voltage at 95A/250kHz load oscillation (VID=1.0Vdc) [VCC: y-axis
50mV/div, x-axis 4µs/div] .................................................................................................. 158 Fig. 4-50 Calculated and measured VR efficiency ......................................................................... 159 xiv
LIST OF TABLES
TABLE 2-1 VR design specifications and parameters ..................................................................... 45 TABLE 3-1 Summary of calculated power loss under steady state load condition ........................ 101 TABLE 3-2 VR design specifications and parameters ................................................................... 104 TABLE 4-1 Design specifications and parameters of proposed VR with Transient Circuit .......... 145 TABLE 4-2 Summary of single step load line compliance simulation results ............................... 151 TABLE 4-3 Summary of AC load line compliance simulation results........................................... 155 xv
LIST OF ACRONYMS
ADC
Analog to Digital Converter
AVP
Active Voltage Positioning
CAD
Computer Aided Design
CCM
Continuous Conduction Mode
CMOS
Complementary Metal–Oxide–Semiconductor
COMP
Comparator
CPU
Central Processing Unit
DA
Differential Amplifier
DAC
Digital to Analog Converter
DCM
Discontinuous Conduction Mode
DCR
Direct Current Resistor
DSP
Digital Signal Processing
Dynamic VID
Dynamic Voltage Identification Code
ESL
Equivalent Serial Inductance
ESR
Equivalent Serial Resistance
I2 C
Inter-Integrated Circuit
IC
Integrated Circuit
xvi
LL
Load Line
MATLAB
Matrix Laboratory (Numeric CAD tool by MathWorks Inc.)
MLCC
Multi-Layer Ceramic Capacitor
MOSFET
Metal–Oxide–Semiconductor Field-Effect Transistor
NVM
Non-Volatile Memory
OPAMP
Operation Amplifier
OSCON
Aluminum
solid
capacitor
with
Organic
Semi-Conductive
electrolyte (OSCON) developed by Sanyo
PCB
Printed Circuit Board
PI
Proportional-Integral
PID
Proportional-Integral-Derivative
PSI
Power State Indicator
PSIM
Power Simulation (Power Electronics CAD tool by Powersim Inc.)
PSPICE
Personal Simulation Program with Integrated Circuit Emphasis
SIMULINK
Simulation Link (Simulation CAD tool by MathWorks Inc.)
TOB
Tolerance of Band
VID
Voltage Identification Code
VR
Voltage Regulator
VRD
Voltage Regulator Down
xvii
VRM
Voltage Regulator Module
VTT
Voltage Transient Test
ZCS
Zero Current Switching
ZVS
Zero Voltage Switching
xviii
LIST OF PRINCIPAL SYMBOLS

Efficiency (%)
ICC
Load current change (A)
Cbulk
Capacitance of output bulk capacitors (F)
Ccer
Capacitance of output MLCC capacitors (F)
Co
Output Capacitance (F)
D
Steady State Duty cycle
d
Duty cycle including Steady State and Small Perturbation
e(n)
Error voltage at nth sampling interval
en
Error voltage at nth sampling interval
fc_load
Critical load oscillation frequency (Hz)
fload
Load oscillation frequency (Hz)
fSAMP_ADC
Sampling frequency of the output voltage ADC Converter (Hz)
fSAMP_COMP
Sampling frequency of the Digital Compensator (Hz)
fsw
Switching frequency of Voltage Regulator (Hz)
Iavg_main_LS
Average current through Transient Circuit low die body diode (A)
Iavg_tran_HS_diode
Average current through Transient Circuit high side body diode (A)
iC
Output capacitor current (A)
xix
iC_max
Maximum current through output capacitor current (A)
ICC
DC load current (A)
ICC_max
Maximum DC load current (A)
ICC_min
Minimum DC load current (A)
iD
Current through low side MOSFET body diode during load release
iL
Phase inductor current (A)
iLe
Equivalent phase inductor current (A)
Imax_down_tran_HS_n
nth maximum current of Transient Circuit high side MOSFET at
load step-down (A)
Imax_down_tran_LS_n
nth maximum current of Transient Circuit low side MOSFET at
load step-down (A)
Imax_up_tran_LS_n
nth maximum current of Transient Circuit low side MOSFET at
load step-up (A)
Imin_up_tran_LS_n
nth minimum current of Transient Circuit low side MOSFET at load
step-up (A)
Iph_max
Maximum point of phase current (A)
Iph_min
Minimum point of phase current (A)
Ireg_avg_tran_HS
Average current regenerated via Transient Circuit high side
MOSFET (A)
Irms_HS
RMS current of high side MOSFET (A)
xx
Irms_LS
RMS current of low side MOSFET (A)
Irms_tran_HS
RMS current of Transient Circuit high side MOSFET (A)
Irms_tran_LS
RMS current of Transient Circuit low side MOSFET (A)
Le
Equivalent Output Inductance of the multiphase VR (H)
Lo
Inductor value in each phase of the VR (H)
N
Number of phases of the VR
nHS
Number of high side power MOSFETs per phase of the VR
nLS
Number of low side power MOSFETs per phase of the VR
Ntran_down_pulse
Number of transient pulses at load step-down
Ntran_up_pulse
Number of transient pulses at load step-up
Pc_HS
Conduction loss of main power circuit high side MOSFET (W)
Pc_L
Copper loss of main power circuit phase inductor (W)
Pc_LS
Conduction loss of main power circuit low side MOSFET (W)
Pc_main_LS
Loss of main power circuit low side MOSFET at load release (W)
Pc_tran_HS
Conduction loss of Transient Circuit high side MOSFET (W)
Pc_tran_LS
Conduction loss of Transient Circuit low side MOSFET (W)
Pc_tran_Lt
Conduction loss of Transient Circuit inductor (W)
Pdiode
Power loss of the body diode (W)
Pg_HS
Gate loss of main power circuit high side MOSFET (W)
xxi
Pg_tran_HS
Gate loss of Transient Circuit high side MOSFET (W)
Preg_tran_HS
Regenerated power by Transient Circuit during load release (W)
Ps_HS
Switching loss of main power circuit high side MOSFET (W)
Ps_L
Core loss of main power circuit phase inductor (W)
Ps_LS
Switching loss of main power circuit low side MOSFET (W)
Ps_tran_HS
Switching loss of Transient Circuit high side MOSFET (W)
Ps_tran_LS
Switching loss of Transient Circuit low side MOSFET (W)
PTOT_tran_HS
Total power loss of Transient Circuit high side MOSFET (W)
PTOT_tran_LS
Total power loss of Transient Circuit low side MOSFET (W)
Qg_TOT_tran_HS
Total gate charge of Transient Circuit high side MOSFET (C)
Qg_TOT_tran_LS
Total gate charge of Transient Circuit low side MOSFET (C)
rbulk
ESR of output bulk capacitors (Ω)
rC
ESR of output capacitor (Ω)
rcer
ESR of output MLCC capacitors (Ω)
Rd
Equivalent load resistance (Ω)
rL
ESR of the phase inductor (Ω)
RLL
DC load line resistance (Ω)
Ron
On resistance of MOSFET (Ω)
Ron_tran_HS
Transient Circuit high side MOSFET on resistance (Ω)
xxii
Ron_tran_LS
Transient Circuit low side MOSFET on resistance (Ω)
tdead_tran
Deadtime between transient high side and low side gate signals
tf_HS
Fall time of high side MOSFET (Second)
tf_LS
Fall time of low side MOSFET (Second)
tf_tran_HS
Fall time of Transient Circuit high side MOSFET (Second)
tf_tran_LS
Fall time of Transient Circuit low side MOSFET (Second)
tr_HS
Rise time of the high side MOSFET (Second)
tr_LS
Rise time of the low side MOSFET (Second)
vc
Output capacitor voltage (V)
VCC
DC output voltage of Voltage Regulator (V)
vCC
Output voltage of Voltage Regulator (V), including DC and AC
VD
MOSFET body diode forward voltage (V)
VDR
Output voltage of gate drive (V)
Vin
DC input voltage of Voltage Regulator (V)
Vref(n)
Digitized reference voltage at nth sampling interval
Vsense(n)
Digitized sensed output voltage at nth sampling interval
y(n)
Output of Digital Compensator at nth sampling interval
Zo
Open Loop Output Impedance
Zo_closed
Closed Loop Output Impedance
xxiii
CHAPTER 1
GENERAL INTRODUCTION
1.1 BACKGROUND
1.1.1 Brief Introduction to Voltage Regulator
A Voltage Regulator (VR) is a dc-dc power converter installed on a motherboard to
regulate the voltage fed to the microprocessor [1-3]. Nearly all motherboards have either a
built-in Voltage Regulator Down (VRD) [2] or a replaceable Voltage Regulator Module
(VRM) [4]. Typically the input to the VR is 12Vdc. The output voltage can be 5Vdc, 3.3Vdc,
1.5Vdc, or even lower. Targeting for different end applications, VRs can be classified as
VR for server computers, workstations, desktop computers, and notebook computers [5].
For different applications, the output voltage and load current will be different. For desktop
and server computers, the maximum current that a VR should deliver is about 135A, and
for notebook computers the current should be in the range of 20A-50A. The efficiency,
cost, and reliability requirements of a VR are different for different applications. Thus the
design criteria and complexity of the VR vary.
Various topologies and their possible combinations are investigated for VR
applications [6-10]. Among them is the conventional synchronous buck converter shown in
Fig. 1-1, which is a voltage step-down converter. It is simple with minimum component
usage, and therefore is currently widely adopted topology for VR applications. This single
phase configuration can deliver current up to 30A with low cost, and thus it is a frequent
candidate for notebook VR applications.
1
For larger current applications, two or more phases of synchronous buck converters
in Fig. 1-1 can be paralleled to deliver more current. Fig. 1-2 gives the topology of such a
multiphase interleaved buck converter. Typically, a two-phase VR can deliver about 60A
economically for notebook applications and a four-phase VR can deliver about 130A for
desktop or server computers.
S1
Vd
Lo
S2
Co
Controller
RL
Fig. 1-1 Synchronous Buck Converter for Voltage Regulation (VR)
Fig. 1-2 Multiphase Interleaved buck converter
Fig. 1-3 gives the physical image of such a multiphase VRD on an Intel
motherboard. This VR has four phases to deliver 125A for a desktop computer. The four
phases are located to the north and east of the LGA775 Socket for the CPU on the
2
motherboard. They are identified as North Phase 1, North Phase 2, East Phase 1, and East
Phase 2 respectively. Corresponding to the schematic in Fig. 1-2, the output filter inductor
in each phase is marked out in Fig. 1-3. The output filter capacitors are made up of bulk
OSCON capacitors marked as C1 and C3, and MLCC capacitors in the center cavity of the
CPU socket marked as C2 in Fig. 1-3.
L_East_2
C3
C2
L_East_1
C1
C1
L_North_1
L_North_2
Fig. 1-3 Physical image of an actual Voltage Regulator (VR) down on an Intel motherboard
1.1.2 Challenges in Powering the Future Microprocessors
As Moore’s law is still counting [11], microprocessors are requiring lower and
lower supplying voltages, targeting 0.5Vdc in the near future, and demanding larger and
larger current up to 150A or more. The CPU of a personal computer currently operates at
about 3GHz and will target 10GHz in the future. The slew rate of the load current at power
up can be as high as 2000A/s currently and 5000A/s in the future. The voltage supplied
to the microprocessor is required to have regulation of about 8% currently and 2% in the
future microprocessors. The absolute value of the voltage regulation is currently 100mVdc
3
and 30mVdc in the future. Such a tight voltage regulation specification is mandatory to
keep the normal logic operation of the CMOS transistors in the microprocessor under all
conditions. If the microprocessor wakes up from its sleep mode to its full operating mode,
then the step of the output current can be as high as 100A to 200A, with a slew rate (di/dt)
of 1000A/s or higher. At the mean time, the output voltage should not drop too much,
50mV for instance. Otherwise the logic operation of the CMOS in the CPU may function
abnormally. However, the voltage droop of VRs based on conventional solutions can be so
large that the output voltage limitation can be exceeded tremendously very easily if the
number of output capacitors is limited.
The major challenge in developing a VR for the next generation microprocessor
therefore lies in designing a very tight and stable output voltage that is immune from the
influence of the increased power consumption, aggressively decreased output voltage, and
dramatically increased load current slew rate. This requires the VR have very fast transient
response particularly to large load steps.
However, the challenges for VR are not limited to the requirement of tight output
voltage regulation. For commercial products, cost is an important factor. Reducing the
number of output capacitors can greatly reduce the cost of VR. On the other hand, reducing
the total amount of output capacitance will make voltage regulation more challenging.
In addition to cost, reliability is also an important factor for VR design. For
example, the output bulk capacitors are known for their frequent failures as the root cause
putting VRs out of order. To increase VR reliability, the number of bulk capacitors should
be minimized or removed completely. However, it is not an easy task considering the
challenge of tight voltage regulation.
4
Efficiency of power converters has become more important recently due to global
awareness of the importance of efficient use. Higher efficiency of VR is not only desired in
server applications, but also in desktop and laptop applications. Increasing VR efficiency
can also help increase its reliability. However, obtaining higher efficiency implies more
challenges in cost reduction and tight voltage regulation.
There are also practical engineering problems currently encountered in industry
that need to be addressed and solved. One problem is that given a multiphase VR, it is
difficult to balance the current in each phase of the VR under high frequency dynamic load
conditions. This current imbalance will lower the efficiency of the VR and may damage
the components if the current unbalance exceeds certain limits. Another problem is related
to multiphase operation and caused by high frequency dynamic load oscillation. It is called
the beat frequency effect, which will lead to high amplitude current oscillation in each
phase of the VR. This high amplitude current can easily exceed the maximum allowed by
the power semiconductors in each phase and create damages.
All these major challenges in powering microprocessors must be addressed and
solved while designing a VR. We will therefore review how existing solutions addressing
these major challenges in Section 1.2.
5
1.2 TECHNICAL REVIEW OF EXISTING SOLUTIONS
Various voltage regulator (VR) topologies, analog or digital control methods to
improve power converters transient response have been proposed [6-8, 10, 12-34], trying
to satisfy the requirements of transient response of microprocessors. However, their
working mechanism determines that it will be even more difficult for them to satisfy the
harsher transient requirements of the next generation of microprocessors. The performance
and limitations of those existing solutions will be reviewed and discussed in detail in the
following sections.
1.2.1 Output Capacitors of Voltage Regulator
It is obvious that increasing the output capacitance can not only reduce the output
voltage ripple, but also help maintain the output voltage during a sudden load change.
However, for a single phase 1.5Vdc/25A VR for instance, a conventional design that can
meet the dynamic response specification typically requires at least 3000µF output
capacitance. The filtering capacitors are bulky and expensive. Thus it would be very
impractical to keep paralleling capacitors at the output, because we can estimate that for a
future VR of 0.5Vdc/100A, the required capacitance could be more than 10000µF. Fig. 1-4
demonstrates such a relationship between the required output capacitance and the load
current for conventional VRs. Although multiphase topology will help reduce the output
capacitance and is used for the estimation where the load current exceeds 50A in Fig. 1-4,
the required capacitance is still tremendous for a large load current.
In addition, bulk capacitors are known for their low reliability as has been
mentioned in Section 1.1.2. Adding more bulk capacitors to increase the output
6
capacitance to meet the voltage regulation requirement will not only increase the cost of
the VR but also reduce its reliability.
15000
13500
Capacitance (uF)
12000
10500
9000
7500
6000
4500
3000
1500
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Load Current (Amper)
Fig. 1-4 Estimated required output capacitance as a function of load current
1.2.2 Output Inductors of Voltage Regulator
Rather than keeping increasing the output capacitance, the output filter inductance
of the buck converter can also be reduced to improve the dynamic responses.
Unfortunately, the inductance cannot be reduced unbounded, otherwise the output voltage
ripple can be easily increased to exceed the ripple requirements, 10mV for instance by
Intel’s VR11.0 specification [2]. The increased voltage ripple will in turn reduce the room
for the output voltage droop or overshoot during transients. In addition, a larger ripple
current through the filter inductor also implies larger current swings through the power
switches, which will degrade the overall efficiency of the VR under steady state operation.
Moreover, even though the inductance can be reduced for faster transient response, it is
7
still not enough to provide adequate response speed for the future microprocessors if the
output capacitance is required to be small for cost and size considerations.
1.2.3 Multiphase Interleaved Topology
Multiphase interleaved VR topology puts two or more buck converters in parallel
and shares the same output capacitors, as has been illustrated in Fig. 1-2. As mentioned
earlier, paralleling more phases is done to increase the current delivery capability to the
load. In addition to that, the output filter inductor in each phase is allowed to be smaller
than that of a single phase VR. With the reduced inductance in each phase, the VR can
achieve faster transient response. The large output current ripple in each phase due to the
reduced inductance per phase can be flattened out by the current ripple of other phases, as
illustrated in Fig. 1-5. The more phases are in parallel, the smaller the ripple will be.
iL1
Io/2
2I o
Ts
iL2
Ts/2
t
Io/2
2I o
t
io
Io
I o
t
Fig. 1-5 Current ripple canceling effect
International Rectifier’s XPHASE [17, 35] solution is an example of such an
approach, which adopts six phases to achieve the required load current and transient
8
response, to reduce the output voltage ripple due to the small 100nH inductor in each phase,
and to minimize the output capacitance. Obviously multiphase topology can enhance the
current carrying capability. However, if the load current can be handled by a single phase
VR or a VR with fewer phases, then adopting multiphase or paralleling more phases solely
for the purpose of reducing the output voltage ripple is not very economical in terms of
component cost and PCB board space. More importantly, it is still very difficult for
conventionally controlled multiphase VR to achieve the required transient response
without a large amount of capacitance at the output or aggressively increasing the
switching frequency.
The information from XPHASE [17, 35] verified the above opinion and analysis.
The implementation requires six phases in parallel. Although it does not use bulk
capacitors, it uses 44 more ceramic capacitors at the output and 2 more phases than the
basic needed number of phases. It must switch at a high frequency of 800kHz to reduce
the voltage ripple due to the very small 100nH inductor. The increased switching
frequency will reduce the efficiency of the VR as will be analyzed in Section 1.2.4.
1.2.4 Switching at Higher Frequency
Increasing the switching frequency of the switch mode power converter has many
advantages. Firstly, it can reduce the components’ values, such as the output capacitance
and inductance, thus reducing the number and volume of the components. The increased
frequency will also result in a faster system response speed. Given a higher switching
frequency, the value of the output inductor for the same amount of ripple voltage can be
reduced. This will also enhance the response of a VR to sudden load changes. Fig. 1-6
shows the step load response of a VR switching at 250kHz, 500kHz, 1MHz, 5MHz, and
9
10MHz respectively. It illustrates that higher switching frequency will result in smaller
voltage droop and faster response.
1.60V
1.55V
1.50V
10MHz
1.45V
5MHz
1.40V
1MHz
1.35V
500kHz
1.30V
1.25V
1.20V
50us
250kHz
75us
V(Vo)
100us
125us
150us
175us
200us
225us
250us
Time
Fig. 1-6 Step responses of a VR switching at different frequency (1.5Vdc/25A output)
A synchronous buck converter for VR can either operate under Continuous
Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM). DCM operation
will result in a larger peak current through the power switches, and hence larger
conduction loss. CCM operation has lower peak current and hence lowers conducting loss.
However, CCM has a higher switching loss because the current through the switches does
not start from zero at turn-on. DCM operation on the other hand can achieve Zero Voltage
Switching (ZVS) at turn on and turn off for both switches of a synchronous buck converter.
The power loss of a VR is made up of conducting loss and switching loss. At a lower
switching frequency, below 1MHz for instance, the power loss is mainly determined by the
conducting loss. In this frequency range CCM has a higher efficiency. However at a higher
frequency, 3MHz for instance, the switching loss proportional to the switching frequency
will dominant. Therefore DCM operation turns out to have a higher efficiency over CCM
operation although its conducting loss is still higher. Fig. 1-7 gives the plot of the
10
estimated efficiency of a VR operating under CCM and DCM versus different switching
frequency, which illustrates the above points.
100
90
Efficiency (%)
80
70
60
50
40
DCM
30
CCM
20
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Switching Frequency (MHz)
8.0
9.0
10.0
Fig. 1-7 Estimated efficiency versus switching frequency for CCM and DCM operation modes
(Based on 1.5Vdc/25A output condition)
Operating the main power circuit at a very high frequency will improve the
dynamic response of the VR given the requirement of very small output capacitance.
However, the overall design of such a VR operating at such a high frequency, above 3MHz
for instance, will be very difficult. First of all, a power MOSFET capable of handling a
larger current will have larger input capacitance, which will increase the turn on and turn
off time of the device, hence limiting the maximum switching frequency. It will also make
the gate loss of power MOSFETs significant, further reducing the efficiency of the VR. If a
higher switching frequency is achieved, then the current carrying capability of the
MOSFET will be decreased. It is a dilemma to design a power MOSFET capable of both
operating at very high frequency and carrying a very large current. Right now
11
commercially available MOSFETs for VR applications can handle about 30A RMS current
and operate at a frequency below 1MHz. Designing a VR beyond the capability of
commercially available MOSFETs would be very challenging. As the switching frequency
increases, the design of the printed circuit board also becomes difficult. Most importantly,
the efficiency of the VR would fall to an unacceptable or unsatisfactory level as the
frequency increases.
In general, increasing the switching frequency of the VR solely for the purpose of
improving the transient response is limited by its feasibility and other performance
specifications. It is not an optimum solution for VRs for future microprocessors. New
control methods and topologies thus need to be explored. Based on the proposed solution
in this thesis, the VR is required to operate at frequency between 200kHz to 600kHz for
higher efficiency and simpler overall system design.
1.2.5 Intermediate Stage Linear Regulation
An intermediate linear regulator array between the VR as the first stage and the IC
load as the last stage was proposed in [13], as shown in Fig. 1-8. It requires the input
voltage of the linear regulator to be higher than the output voltage, 400mVdc for instance.
This voltage difference is preferred to be the maximum as long as the linear regulator can
be regulated, so that when a sudden load step happens, the output voltage droop of the VR
will have much larger room, 400mVdc for instance, which is greater than the 100mVdc
room for instance for conventional single stage VR solution. This extra room greatly
lessens the requirement of the output voltage regulation of the VR in the first stage, thus
making design of the VR easier.
12
Fig. 1-8 Intermediate Linear Regulator solution
However, during normal steady state operation at full load for example, the large
voltage droop across the linear regulator together with the dc current through it will create
power loss. The power loss may not be a problem when the IC consumes only a small
amount of current and this solution can possibly provide the required dynamic response.
However, integrated circuit such as microprocessors demand a large amount of load
current, and thus the linear regulator will dissipate power excessively during normal steady
state operation. Even though the voltage droop on the linear regulator could be designed to
be smaller after certain compromises, the power loss will still be excessive, hence resulting
in rather low efficiency, which would then create thermal problems that are difficult to
solve.
In addition, this solution requires partitioning the CPU into different power zones
to make the linear regulation feasible, because a single transistor is not capable of
delivering current as high as 100A and at the same time as dissipating the heat effectively
resulting from the large power loss. It would also be impossible for the microprocessor
manufacturers to partition the CPU into different power zones and provide the interface
accordingly only for the sake of easier VR design, especially when other potential
13
solutions exist. Therefore, this linear regulator solution is impractical for the application of
powering microprocessors.
1.2.6 Current Mode Control and Voltage Mode Control
Currently the most widely used power conversion topology for VR is a buck
converter, either single phase or multiphase interleaved. Their control methods can be
categorized into two categories: current mode control [36] and voltage mode control.
When a small perturbation is introduced, current mode control has a faster dynamic
response than that of conventional voltage mode control. However, its dynamic
performance is not superior to that of voltage mode control when a large perturbation
happens. This is because the response to a large signal is primarily determined by the
slowest control loop of the system. In current mode control the crossover frequency of its
slower outer voltage loop is limited by the crossover frequency of its faster inner current
loop. Fig. 1-9 gives the block diagram of the current mode control and shows the current
loop and voltage loop. However, in voltage mode control, the crossover frequency of the
voltage loop, which is also the only control loop, can be the same as that of the current
loop of current mode control.
~
iL ,ref ( s )
v~o ,ref ( s )

+
-
Gv (s )
~
d ( s)

+
Gi (s )
-
~
iL ( s )
G pi (s )
v~o ( s )
G pv (s )
Current Loop
Voltage Loop
Fig. 1-9 Block diagram of current mode control
Fig. 1-10 gives the simulation results of these two control methods, which shows
that if the voltage loop of the current mode control and that of the voltage mode control
14
have the same crossover frequency, then these two control modes will have similar output
voltage droop given the same step load, although the current mode control demonstrates a
shorter settling time. Given the same switching frequency, if the crossover frequency of the
inner current loop of current mode control is the same as the crossover frequency of the
voltage mode control, then the outer voltage loop of the current mode control is normally
designed to have a crossover frequency of about 5-10 times lower than that of the inner
current loop, which is the same as the crossover frequency of the voltage mode control. In
this case, the current mode control will demonstrate larger undershoot or overshoot, and
longer settling time compared to voltage mode control.
2.0V
1.9V
1.8V
1.7V
1.6V
1.5V
1.4V
1.3V
1.2V
1.1V
1.0V
0.9V
0.8V
0.7V
0.6V
0.5V
0s
Voltage Mode Control
Current Mode Control
V(Vo)
100us
200us
300us
400us
Time
Fig. 1-10 100% load step responses of current mode and voltage mode control (1.5Vdc/25A)
More importantly, voltage mode control can potentially eliminate current sense
circuit since its use for current loop regulation is no longer needed. For certain single phase
VR applications, for instance, the elimination of the current sense circuit can further reduce
the complexity and cost of the VR.
15
1.2.7 Load Current Feed-Forward Control
The load current feed-forward control approach reported in [19, 37] intend to
enhance the transient response of the voltage mode controlled converter. Its small signal
block diagram is shown in Fig. 1-11.
~
iCC
Power Stage
Zopen
v~CC
Gpv
Controller
v~c
Zref
Feedforward
Wff
v~cv
Cff
Feedback
Wfb
Cfb
v~ref
Fig. 1-11 Small signal block diagram of load current feed-forward control method
The load current feed-forward control method includes the sensed load current
information into the voltage control loop, so as to accelerate the speed of the compensator.
This control method provides a good solution to enhance the transient response of dc-dc
converters that only supply slow slew rate loads. For microprocessors, the slew rate of load
current can be as high as 2000A/µs, so the real time sensed current lags the actual load
current significantly. It will be too late when the controller starts to react to the sensed load
current. Therefore, the load current feed-forward control method is a limited improvement
over the load transient response for VR that is powering microprocessor loads.
16
1.2.8 V2 Control and Its Enhanced Version
V2 control method [29, 38] or its enhanced version with peak current feedback [14,
31] utilizes two voltage feedbacks or add peak current feedback to enhance VR’s transient
response. Fig. 1-12 gives the small signal block diagram of the enhanced V2 control.
~
iL ( s )
v~CC
v~in
Fig. 1-12 Small signal block diagram of enhanced V2 control method
V2 control uses the information of the output voltage at two different stages in the
control loop. It is substantially based on voltage mode control, but with enhanced speed
brought by the two voltage information. The limitation of this method is that if the load
current changes quickly, then it is impossible for the compensator to react quickly enough
since the change of the output voltage lags the load current significantly. An enhanced V2
control method is therefore proposed, which adds the sensed peak current information to
the control loop to improve the response speed of the compensator. However, similar to
load current feed-forward control, the sensed current lags the high slew rate load current
17
significantly, and thus the peak current information has limited effect on the transient
response.
1.2.9 Non-Linear Hysteresis Control
A non-linear control method can overcome the transient response limit due to the
fixed gate pulse intervals determined by the fixed switching frequency. Non-linear control
based on hysteresis thresholds comparison [16, 39] is straightforward and relatively easy to
implement. However, this method cannot accurately determine the duration of non-linear
operation at transients and the output voltage is subject to being bounced back and forth
between the thresholds, and thus will result in long settling time especially at load step up.
This approach did not show satisfactory VR performance that complies with the design
specifications.
1.2.10 Coupled Inductor Approach
The coupled inductor method [23, 40, 41] with small output inductance greatly
reduces the output capacitance, but it also requires higher switching frequency so as to
balance the voltage regulation and voltage ripple requirements. Moreover, the custom
designed coupled inductors are more complicated and expensive compared to standard offthe-shelf inductors widely available in the market.
The major merit of the coupled inductor solution is that it can further reduce the
size of the phase inductors by integrating them in one magnetic enclosure. The ESR of the
inductor can be potentially reduced and thus it can reduce the power loss. However, the
reduced copper losses by a coupled inductor are not very significant when compared to
other power losses such as those in MOSFETs. On the other hand, the slop of the ripple
current through the phase inductor is high due to its very small inductance. The required
18
switching frequency therefore must be high to keep the peak to peak current at the level to
satisfy the ripple voltage requirement. As a result of the increased switching frequency, the
core loss of the coupled inductor is also increased.
Fig. 1-13 Multiphase coupled inductor VR
The slope of the current through the inductor in each phase is constant in
conventional multiphase VR. For the multiphase VR using coupled inductors, the slope of
the current is different in different time segments during one switching cycle. The overall
peak to peak amplitude of the phase current is smaller than that of a standard inductor of
the same value. Thus, the coupled inductor approach shows a lower steady state output
voltage ripple. However, given the same inductance value, the coupled inductor approach
does not show a gain in transient response compared to the standard inductor approach.
This is because in one segment of time, the slope of the current through the coupled
inductor is larger, but it is smaller in the next time segment. Considering the inductors in
all phase as one equivalent inductor, the transient response of the coupled inductor is
indeed unchanged.
19
1.3 OBJECTIVES OF THE THESIS
As has been explained in Section 1.1.2, powering future microprocessors is a
challenging task and several practical problems in industry remain to be solved. Existing
approaches and solutions for VRs to power microprocessors have been reviewed in Section
1.2. However, they are still not satisfactory to meet all the requirements. The work of this
thesis thus intends to provide solutions for VR to power microprocessors to meet the
requirements. The major objectives of the thesis are to:
(1)
Provide techniques to enhance VR’s transient response;
(2)
Provide control techniques to minimize the number of output bulk capacitors without
modifying the existing simple VR topology so as to reduce the cost;
(3)
Provide a new control technique for conventional VR topology with a proposed
active Transient Circuit, so as to potentially remove all the passive output bulk
capacitors and to only use MLCC capacitors to increase VR’s reliability;
(4)
Solve the phase current imbalance problem of multiphase VRs under high frequency
dynamic load conditions;
(5)
Solve the phase current high amplitude oscillation problem due to beat frequency
effect under high frequency dynamic load conditions;
(6)
Provide a cost effective and energy efficient solution for VR, which includes a
solution for high efficiency under steady state and a solution for high efficiency
under light load conditions; and
(7)
Propose digital controllers to implement the proposed control strategy and other key
power management functionalities desired by the VR and CPU manufacturers.
20
1.4 OUTLINE OF THE THESIS
The thesis consists of five chapters. Their contents are outlined below.
Chapter 1 introduces the thesis work. Background on the Voltage Regulator (VR)
and its applications is briefly introduced. Challenges in providing VR solutions to power
future microprocessors are also described in this chapter. Existing solutions to address the
challenges are reviewed. Their merits and limitations are analyzed in detail, to provide the
backdrop for introducing the high performance VR solutions proposed in later chapters of
this thesis.
Chapter 2 further analyzes the high frequency dynamic load operation requirements
for VR and the practical problems encountered in industry, such as phase current balancing
and beat frequency oscillation problems. A voltage mode with phase current balancing
control method is therefore introduced in this chapter for multiphase VR. It provides a
solution for fast output voltage regulation, phase current sharing under steady state, and
phase current balancing under high frequency dynamic load conditions. In order to
understand the proposed solution and give the design approach, small signal analysis of the
VR is given in detail in Chapter 2. A small signal model of the VR is proposed. Various
transfer functions are derived for the VR model. The relationship between DC output
resistance, small signal output impedance, and large signal output impedance are clarified
to aid the design of the VR. The effect of parasitic inductance and resistance on the
motherboard is also clarified for design. Simulation results are given in Chapter 2 to verify
the analysis and model of the proposed multiphase VR control method. A summary is
given at the end of this chapter.
21
Chapter 3 proposes a predictive non-linear voltage mode control method to enhance
the transient performance of a VR and to reduce the number of bulk capacitors at the
output. The method allows the VR to operate at a moderate switching frequency around
250kHz to achieve high efficiency easily. Operation of the VR is described in detail in this
chapter. Theoretical analysis is given to predict the load current change. The output voltage
and its slope are detected to determine the non-linear operation of the VR during load
transients. The proposed control method is implemented digitally. The architecture of the
digital controller is given. The control algorithm is described. Simulation and experimental
results are given in this chapter to verify the performance of the proposed non-linear
control method. A summary is presented at the end of this chapter.
Chapter 4 proposes a VR with transient circuit to further enhance the transient
response of the VR. The proposed topology and control method can potentially remove all
the bulk capacitors of the VR. The VR operates at a frequency around 250kHz so as to
achieve high efficiency with less expensive power components. The operation of the VR is
described in this chapter. Theoretical analysis is given. The control is implemented
digitally. The architecture and control algorithm are described. The power loss analysis of
the VR is also presented. Simulation and experimental results are given in detail to verify
the performance of the proposed VR topology and the control method. Finally a summary
is given in the end of this chapter.
Chapter 5 presents the conclusions of this thesis work and pointing out areas for
future work.
22
CHAPTER 2
MODELING AND ANALYSIS OF MULTIPHASE VOLTAGE
REGULATOR FOR HIGH FREQUENCY DYNAMIC LOAD
2.1 INTRODUCTION
Voltage mode and current mode control are the two major control methods applied to
VR regulation. Compared to current mode control, voltage mode control has less limitation
on the loop bandwidth as has been analyzed in Chapter 1. Thus there is a motivation to
adopt voltage mode control for new control techniques that can greatly improve the
converter’s transient performance. Secondly, to satisfy Intel’s VR requirements, the VR
should be able to operate with load line positioning (or voltage droop) to reduce the
processor’s power loss and to give more headroom for the output voltage of the VR [5, 42].
Thirdly, for microprocessors demanding load current of about 25A or more, a multiphase
interleaved buck converter is currently necessary and is a widely adopted topology, which
however requires that each phase of the VR share the load current for thermal and thus
efficiency considerations under static load conditions. Finally, Intel and AMD’s VR
specifications require the VR to be designed and tested for high frequency dynamic loads
up to 1MHz [42]. Under such conditions the VR is required to maintain its voltage
regulation and to keep its phase current balanced without high amplitude oscillation.
All these above mentioned issues require thorough small signal analysis and
modeling of the system to help understand the nature of the VR and to improve its
transient performance. This is especially important when the design is at the stage where
precise optimization is the key or at the last step to enable the VR’s performance to satisfy
23
specifications for a given circuit configuration and cost budget. Such effective and
quantified analysis becomes important and sometimes is the last step solution to noncomplied transient responses.
Many publications have addressed small signal analysis and modeling of current
mode control [43-45], or current sharing control with load line positioning based on
current mode control [40, 46, 47]. However, none has given thorough analysis of VR with
phase current balancing and load line positioning based on voltage mode control. Other
phase current sharing techniques for paralleled dc-dc converters such as the ones presented
in [48-50] are however based on low bandwidth design. A low bandwidth design for
current sharing loop is sufficient to stabilize the phase current at static load or at very low
frequency load changes such as at 100Hz. It however will not be able to balance the phase
current for high frequency dynamic loads specified by Intel and AMD [3, 42]. The analysis
and results of current balancing under high frequency dynamic loads are not reported in the
above literatures, and nor are the associated solutions.
There is therefore strong motivation to give a thorough analysis and in depth
validation of the model of the VR to guide the design to address the above mentioned
challenges and unsolved problems. The analysis and modeling of voltage mode controlled
multiphase VR presented in this chapter helps improve voltage regulation and current
balancing under high frequency dynamic load conditions. The model and design approach
will change the impression that it is difficult or complicated to implement current
balancing in voltage mode control. The relationship between the DC output impedance,
small signal output impedance, and the large signal output impedance of the VR are also
clarified in this chapter.
24
2.2 GENERAL REQUIREMENT ON VR’S TRANSIENT RESPONSE
AMD’s microprocessor requires the VR operate with flat load line, or zero DC load
line resistance [3]. The design goal for VR’s transient performance is to minimize
undershoot, overshoot and settling time of the output voltage as much as possible upon
load steps. Ideally, the output voltage should be a flat line during load transients.
Intel’s microprocessor however requires the VR operate with voltage positioning at
given load line resistance [42]. In time domain, the VR’s output voltage should not
demonstrate excessive undershoot or overshoot. Moreover, it is ideal if the output voltage
follows the load line precisely to avoid possible out of specification undershoot or
overshoot upon load oscillations at certain unknown frequencies. The waveforms of such a
repetitive load current and corresponding ideal output voltage are plotted in Fig. 2-1. The
DC load line resistance or slope RLL is defined in (2-1), in which VCC and ICC are the output
voltage and load current of the VR respectively.
 I CC
VCC
Fig. 2-1 Time domain ideal waveform of voltage response under Intel’s load line operation
25
R LL  VCC / I CC
(2-1)
This time domain transient performance requirement is also described and defined in
the frequency domain by Intel as AC load line impedance ZLL [51, 52], which is given in
(2-2). The AC load line impedance is obtained when the VR is operating under large
repetitive load steps. The measured time domain output voltage is then transferred to the
frequency domain to calculate the impedance as a function of load frequency. Such an
impedance curve is plotted in Fig. 2-2. Ideally the value of ZLL is desired to be the same as
the DC load line resistance RLL at all load oscillation frequencies.
Z LL  f  
FFT VCC t 
FFT I CC t 
(2-2)
4
Load Line Impedance (mOhm)
3.5
3
2.5
2
1.5
1
0.5
0
1
10
100
1000
10000
Frequency (Hz)
Fig. 2-2 Intel’s frequency domain AC load line impedance ZLL
26
100000
The frequency domain AC load line impedance ZLL defined in (2-2) and illustrated in
Fig. 2-2 intends to help predict the VR’s output voltage transient response in time domain.
Although it is in frequency domain, it could be a good indication of the undershoot and
overshoot of the output voltage. A non compliance of the impedance in frequency domain
will lead to non compliance in time domain if the VR is linearly regulated. This AC load
line impedance is substantially the VR’s large signal output impedance, which can be
approximated by the VR’s small signal output impedance to predict how the VR’s voltage
response will be in time domain upon load oscillations. The small signal output impedance
Zo_closed is defined in (2-3). It could be used to predict the voltage response of a linear
system, but such application may not be valid if the system is a non-linear system.
v~
Z o _ closed ( s )  ~CC
iCC
(2-3)
For multiphase VRs, it is preferable for the current in each phase to be identical for
the purpose of even thermal distribution among phases. However, if the component values
in each phase are not identical, for instance, then the phase current will not be identical as a
result. Such asymmetrical distribution of component values under static load current
conditions requires the VR have the ability to share load current evenly among phases. In
addition to phase current sharing under static load conditions, the current in each phase
should also be balanced quickly upon dynamic load transitions. This phase current
balancing requirement indeed echoes the load current oscillation requirement. That is to
say the VR should have the phase current balanced as quickly as possible to avoid
asymmetrical thermal distribution among phases so as to have optimized efficiency under
dynamic load conditions up to 1MHz.
27
2.3 DESCRIPTION OF THE MULTIPHASE VOLTAGE MODE CONTROLLED VR
Fig. 2-3 gives the brief schematic of a voltage mode controlled VR with load line
positioning and phase current balancing, in which the power circuit is a four-phase
interleaved buck converter. The load of the VR is Intel’s load model given in [42]. The
control circuit shown in Fig. 2-3 is analog implemented serving as an example for the
control method and the corresponding system modeling. The controller can be digitally
implemented as well.
In Fig. 2-3, the output voltage VCC is differentially sensed and compared with the
reference voltage given in (2-4). The reference voltage is determined by the voltage
identification code (VID), the static load line slope (or DC load line resistance) RLL, the
load current ICC, and the Tolerance of Band (TOB) voltage VTOB which is 19mV specified
by Intel. The VID is specified by AMD or Intel’s VR design guide and the signal is sent to
the controller from the microprocessor. The DC load line resistance RLL is defined in (2-1).
VREF  VVID  VTOB  I CC  RLL
(2-4)
Such a load line slope and Tolerance of Band (TOB) windows are plotted in Fig. 2-4.
Detailed specifications of Intel’s DC load line operation can be found in Intel’s document
in [42]. For AMD’s flat load operation, RLL can be set by the control circuit to be zero.
Both AMD’s flat load line operation and Intel’s load line operation will be discussed and
compared in small signal analysis given in Section 2.7.
28
Fig. 2-3 Voltage mode controlled 4-phase VR with load line positioning and phase current balancing
29
0
20
40
60
80
100
120
0
Vmax Load Line
-0.02
Vtyp_Load Line
-0.04
Vmin Load Line
-0.06
-0.08
-0.1
-0.12
-0.14
-0.16
-0.18
Fig. 2-4 Intel’s LGA775 socket load line window for design consideration (775_VR_CONFIG_04B)
The output error voltage is compensated by a compensator, whose output will be
finally sent to generate the control voltage to the comparators to generate the gate pulses.
The phase current can be sensed using Ron of MOSFET [53] or using Direct Current
Resistor (DCR) method given in [20]. The sensed current is summed and filtered, and then
sent for DC load line resistance scaling to generate the reference voltage defined in (2-4).
The unfiltered total current ICC_TOT is scaled down by a number of phases to obtain
the average current ICC_AVG, which is then compared with the sensed current of each phase
for phase current balancing loop regulation. The compensated error voltage and error
current of each phase is summed to form the final control voltage of each phase Vci1-Vci4.
These control voltages are then compared with the triangular carrier to generate the gate
pulses, so as to regulate the output voltage and to keep the phase currents equal to one
another. The differentially sensed output voltage will also be sent to a non-linear control
block, which will generate the gate pulse to accelerate the VR’s voltage response during
load transients. The non-linear control will not be addressed in this chapter but in later
chapters.
30
2.4 MODELING OF THE MULTIPHASE VR
2.4.1 State Space Description of the Multiphase VR
The state space equations [54-58] of a multiphase VR are given from (2-5) to (2-10),
in which iL is the phase inductor current, vc is the output capacitor voltage, Vin is the input
voltage, Co is the output capacitance, Le is the equivalent inductance of the phase inductors,
Rd is the load resistance, rL is the ESR of the phase inductor, and rc is the ESR of the
output capacitor.

        Vin
 Rd  rc  Rd  rL  rc  rL

Le  ( Rd  rc )

Rd


C o  ( Rd  rc )
Rd

Le  ( Rd  rc ) 

1


C o  ( Rd  rc ) 
(2-5)

(2-6)
1
   Le 
 
0
(2-7)
i L 
 
v c 
(2-8)
The transfer function of the power converter is given in (2-9), in which E is given in
(2-10).
T p ( s )    s  I  1        Vin     
 R r
 d c
 Rd  rc
Rd 

Rd  rc 
31
(2-9)
(2-10)
2.4.2 Small Signal Model of the VR
Fig. 2-5 gives the complete small signal model of the multiphase VR described in
Section 2.2. The proposed small signal model reflects the control method implemented in
the schematic given in Fig. 2-3. The control loops and blocks of the model are described
below.
~
iavg
~
ierr 1
v~ci1
~
d i1
~
iLo 1
~
iavg
~
ierr2
v~ci 2
~
d i2
~
iLo 2
~
itotal
~
iavg
~
ierr 3
v~ci 3
~
di3
~
iLo 3
~
iavg
~
ierr4
v~ci4
~
di4
~
iLo 4
~
iCC
v~in
v~vid
v~ref
v~err
~
dv
v~cv
v~CC
v~noise
Fig. 2-5 Complete small signal model with load line positioning and phase current balancing
32
In Fig. 2-5, Gpv is the small signal transfer function of the power stage of the VR in
voltage mode control and is expressed in (2-11).
G pv ( s) 
VCC  rc / D  Le   s  VCC / D  Le  Co 
s 2  1 / Rd  Co   rc / Le   s  1 / Le  Co 
(2-11)
Gm is the gain of the modulator. Hsv is the transfer function of the output voltage
sensor. RLL is the DC load line slope. Gfi is the transfer function of the filter for load line
positioning. Gpi is the transfer function of the power stage of the current loop.
Gcv is the transfer function of the voltage loop compensator, whose format is
determined by the system loop characteristics. A double-zero double-pole compensator is
an example of such implementation. Its transfer function is given in (2-12). Other
applicable implementations include single-zero single-pole compensator and PID
compensator.
Gcv ( s ) 
k cv 1  s /  zv 2

s 1  s /  pv 2


(2-12)
Zo_open is the open loop small signal output impedance of the VR. Its transfer function
is given in (2-13).
Z o _ open ( s ) 
Le  C o  rc  s 2  Rd  rc  C o  Le   s  Rd
Le  C o  s 2  Rd  C o  rc  Co  Le / Rd   s  1
(2-13)
Ggv is the transfer function of open loop line rejection of the VR. Its transfer function
is given in (2-14).
G gv ( s ) 
Le  s
Le  Co  Le  Co  rc / Rd   s 2  Le / Rd  rc  Co   s  1
33
(2-14)
Gci is the transfer function of the phase current balancing loop compensator, whose
format is determined by the current loop characteristics. A single-zero single-pole transfer
function is an example of such a compensator and its transfer function is given in (2-15).
Other applicable formats of current loop compensation include a PI compensator.
Gci ( s ) 
k ci 1  s /  zi 

s 1  s /  pi


(2-15)
Hsi is the transfer function of the current sense circuit, which depends on how the
phase current is sensed. Gavg is the gain to scale the measured total phase current to
average phase current and to serve as the reference for phase current balancing. Hsi and
Gavg can be deemed as constant up to a certain high frequency, beyond which the exact
transfer function shall be used.
Gavg ( s ) 
1
N
(2-16)
2.4.3 Average Modeling of VR
The VR can also be modeled using an average approach shown in Fig. 2-6, in which
Vin is input voltage, VCC is output voltage, Co is output capacitor, Le is equivalent inductor,
and Rd is load resistance. However, this average approach is effective only when the VR is
linearly regulated. If non-linear control is applied, this model is no longer valid.
vs
iLe
ip
Fig. 2-6 Average model of the VR
34
2.5 CLOSED LOOP TRANSFER FUNCTIONS
2.5.1 Closed Loop Transfer Function of Output Voltage
Prior deriving the closed loop transfer function of the output voltage, the assumption
~
needs to be made, that is the phase current is balanced, so that the sensed currents of iLo _ 1
~
~
to iLo _ 4 are equal to the sensed average current iavg . Based on this assumption above, the
output voltage closed loop small signal transfer function can be written in (2-17), in which
Tvz(s), Tv(s), and Tz(s) are given in (2-18), (2-19), and (2-20) respectively.
Gcv ( s)  Gm ( s )  G pv ( s ) ~
G gv ( s)  1  Tz ( s ) ~
v~CC 
 vvid 
 vin
1  Tvz ( s)
1  Tvz ( s )

(2-17)
Z o _ open  1  Tz ( s ) ~
T ( s )  Tv ( s )  Tz ( s)  H sv ( s )  Tz ( s) ~
 iCC  v
 vnoise
1  Tvz ( s)
1  Tvz ( s )
Tvz ( s)  1  Tv ( s)  Tz ( s)  Tv ( s)  Tz ( s)  H sv ( s)  Tz ( s)
(2-18)
Tv ( s )  Gcv ( s)  Gm ( s )  G pv ( s )  H sv ( s )
(2-19)
Tz ( s )  Gcv ( s )  Gm ( s )  G pi ( s )  G fi ( s )  R LL  N
(2-20)
2.5.2 Closed Loop Transfer Function of Phase Current
The closed loop transfer function of the phase current balancing loop is expressed in
(2-21), in which Gpi is the transfer function of the power stage, Gci is the transfer function
of the compensator, and Gm is the gain of the modulator same as that of voltage regulation
loop. Ti is the transfer function of control to output of current loop and is given in (2-22).
~
iavg is given in (2-23). v~CC is given in (2-17).
35
Gci ( s )  Gm ( s )  G pi ( s )  G fi  RLL  N ~
Gm ( s )  G pi ( s ) ~
~
 vCC
 iavg 
iLo _ n 
1  Ti ( s )
1  Ti ( s )

(2-21)
Gm ( s )  G pi ( s ) ~
Gm ( s )  G pi ( s ) ~
 vvid 
 v noise
1  Ti ( s )
1  Ti ( s )
Ti ( s )  Gci ( s )  Gm ( s )  G pi ( s )  H si ( s )
(2-22)
1 N ~
~
iavg    iLo _ n
N n 1
(2-23)
2.5.3 Closed Loop Transfer Function of Output Impedance
The closed loop small signal output impedance Zo_closed is given in (2-24), in which
Tz(s) and Tvz(s) are given in (2-20) and (2-18) respectively.
Z o _ closed ( s )  
1  Tz ( s )
 Z o _ open ( s )
1  Tvz ( s )
(2-24)
2.5.4 Closed Loop Transfer Function of Line Rejection
The closed loop line rejection (Audio Susceptibility) of the VR is given in (2-25).
Ao _ closed ( s ) 
1  Tz ( s )
 G gv ( s )
1  Tvz ( s )
(2-25)
2.5.5 Closed Loop Transfer Function of Noise Rejection
The closed loop noise rejection of the VR is given in (2-25).
T ( s )  Tv ( s)  Tz ( s )  H sv ( s )  Tz ( s) ~
v~CC   v
 vnoise
1  Tvz ( s )
36
(2-26)
2.6 DESIGN FOR HIGH FREQUENCY DYNAMIC LOADS
2.6.1 Output Voltage Regulation
In order to have fast output voltage transient response and to minimize undershoot
and overshoot voltage at output, the bandwidth of the voltage control loop should be
maximized without driving the VR into an unstable state.
2.6.2 Phase Current Balancing
If no phase current balancing control is included in voltage mode control, the VR’s
phase current cannot be kept the same upon system changes. Fig. 2-7 gives the simulated
current waveforms in PSIM®, from which we can see that the current in each is the same at
20A static load condition, but is no longer the same after a 100A load step-up when current
balancing control is absent. If the current balancing loop is properly designed, the phase
current can still be identical after an abrupt load step as shown in Fig. 2-8.
Fig. 2-8 Waveforms of phase current balanced
Fig. 2-7 Waveforms of current without balancing
If the bandwidth of the current balancing loop is low, then the phase current can be
balanced before and after a load step, as demonstrated in Fig. 2-9, in which a 1kHz
bandwidth can balance the phase current at 20A and 120A static load. However, it will not
be able to keep the phase current balanced when the load starts to oscillate at high
37
frequency. Fig. 2-10 shows that when the load oscillates at 100kHz, the phase current is
no longer balanced due to low bandwidth design. In order to balance the phase current
under high frequency dynamic load conditions, the bandwidth of current loop should be
maximized.
140A
120A
100A
80A
60A
40A
20A
0A
I(INTEL_LOAD_MODEL.I_PWL)
50A
40A
30A
20A
10A
0A
SEL>>
-20A
200us
I(4Phase_Buck.Lo1)
250us
I(4Phase_Buck.Lo2)
300us
I(4PHASE_BUCK.Lo3)
Time
350us
400us
I(4PHASE_BUCK.Lo4)
Fig. 2-9 Current balanced at static load of 20A and 120A respectively under low bandwidth design at 1kHz
140A
120A
100A
80A
60A
40A
20A
0A
50A
I(INTEL_LOAD_MODEL.I_PWL)
40A
30A
20A
10A
0A
SEL>>
-20A
200us
I(4PHASE_BUCK.Lo1)
250us
I(4PHASE_BUCK.Lo2)
300us
I(4PHASE_BUCK.Lo3)
Time
350us
I(4PHASE_BUCK.Lo4)
400us
Fig. 2-10 Phase current balanced at static load of 20A but unbalanced at 20A-120A/100kHz load oscillation
due to low bandwidth design at 1kHz
38
2.6.3 Minimizing Beat Frequency Effect
Moreover, high frequency repetitive load step changes will generate beat frequency
oscillation in the phase current, as has been well reported in [59]. Such beat frequency
oscillation is not an issue for static or low frequency oscillating load, but will become
relevant in the event of high frequency dynamic load due to the consequence of excessive
high amplitude phase current oscillation. Fig. 2-11 demonstrates this phenomenon very
well, in which a 140A peak to peak phase current oscillation occurs at 10kHz. This 10kHz
component is due to beat frequency effect. It is the difference between the power supply
switching frequency at 250kHz and the load oscillation frequency at 240kHz, as given in
(2-27). Other sideband beat frequencies have much less impact on the high amplitude
oscillation, and thus can be ignored in the design for minimizing beat frequency effect.
140A
120A
100A
80A
60A
40A
20A
0A
120A
I(INTEL_LOAD_MODEL.I_PWL)
100A
80A
60A
40A
20A
0A
SEL>>
-40A
200us
300us
400us
I(4PHASE_BUCK.Lo1) I(4PHASE_BUCK.Lo2)
500us
600us
700us
800us
I(4PHASE_BUCK.Lo3) I(4PHASE_BUCK.Lo4)
Time
Fig. 2-11 High amplitude phase current oscillation due to beat frequency effect under low
bandwidth design at 1kHz (fsw=250kHz, fload=240kHz)
39
f beat  f sw  f load
(2-27)
The frequency spectrum of the phase current waveforms given in Fig. 2-11 is plotted
in Fig. 2-12, which also shows high amplitude current in each phase at 10kHz. Although
the current amplitude in each phase at different frequencies is identical, in other words, the
phase current is balanced, such a high amplitude phase current oscillation at 10kHz may
easily damage the power components of the converter or cause frequent shutdown of the
converter due to over current protection of which the engineers may not be aware.
80
10kHz
Phase Current (A)
70
60
I_Lo4
I_Lo3
I_Lo2
I_Lo1
50
40
30
20
250kHz
10
0
0
50
100
150
200
250
300
Frequency (kHz)
Fig. 2-12 Frequency spectrum of phase current waveforms in Fig. 2-11 with high amplitude beat
frequency oscillation at 10kHz
Notch filter with cutoff frequency around switching frequency can be used to
minimize the beat frequency effect. Fig. 2-13 gives an example circuit of an OPAMP
implemented notch filter. The amplitude reduction by notch filtering is significant for low
bandwidth design. Fig. 2-14 shows that with notch filtering added, the phase current
oscillation at beat frequency is greatly reduced for the same 1kHz bandwidth design.
40
3V3
FIL_IN
U1A
C0_1
+
V+
FIL_OUT
OUT
RQ_1
-
R0_1
6.3k
V-
RQ_2
0
C0_2
0
R0_2
0
R5
VOUT
V+
+
U2B
R6
3V3
Fig. 2-13 Schematic of a notch filter
140A
120A
100A
80A
60A
40A
SEL>>
0A
I(INTEL_LOAD_MODEL.I_PWL)
50A
40A
30A
20A
10A
0A
-10A
220us
240us
260us
280us
300us
I(4Phase_Buck.Lo1)
I(4Phase_Buck.Lo2)
320us
340us
I(4PHASE_BUCK.Lo3)
Time
360us
380us
400us
I(4PHASE_BUCK.Lo4)
420us
Fig. 2-14 Beat frequency effect of 1kHz bandwidth design reduced by adding notch filtering
Increasing the bandwidth of the current balancing loop will greatly suppress the beat
frequency oscillation. Fig. 2-15 shows that the phase current is balanced and the beat
frequency oscillation is minimized when the bandwidth of the current loop is increased to
50kHz, even without notching filtering.
41
140A
120A
100A
80A
60A
40A
20A
0A
I(INTEL_LOAD_MODEL.I_PWL)
40A
35A
30A
25A
20A
15A
10A
5A
0A
SEL>>
-10A
220us
240us
280us
I(4Phase_Buck.Lo1)
I(4Phase_Buck.Lo2)
320us
360us
400us 420us
I(4PHASE_BUCK.Lo3)
I(4PHASE_BUCK.Lo4)
Time
Fig. 2-15 Phase current balanced waveforms (fsw=250kHz, fload=240kHz, BW=50kHz)
Fig. 2-16 plots the frequency spectrum of the phase current waveforms shown in Fig.
2-15. It verifies that the phase current is balanced, since the current amplitude of each
phase at different frequencies is identical. The current amplitude at 10kHz beat frequency
is also reduced to a very acceptable level.
20
18
Phase Current (A)
16
14
I_Lo4
I_Lo3
I_Lo2
I_Lo1
12
10
8
10kHz
250kHz
6
4
2
0
0
50
100
150
200
250
300
Frequency (kHz)
Fig. 2-16 Frequency spectrum of phase currents in Fig. 2-15 with beat frequency effect minimized at 10kHz
42
After the bandwidth of the current balancing loop is increased to a higher bandwidth
at 50kHz, adding notch filtering can further reduce the beat frequency oscillation. The
simulation result of such implementation is shown in Fig. 2-17.
140A
120A
100A
80A
60A
40A
SEL>>
0A
I(INTEL_LOAD_MODEL.I_PWL)
40A
30A
20A
10A
0A
-10A
220us
240us
260us
280us
300us
I(4Phase_Buck.Lo1)
I(4Phase_Buck.Lo2)
320us
340us
I(4PHASE_BUCK.Lo3)
Time
360us
380us
400us
I(4PHASE_BUCK.Lo4)
420us
Fig. 2-17 Beat frequency effect further reduced with high bandwidth design and notch filtering (fsw=250kHz,
fload=240kHz, BW=50kHz)
2.6.4 Load Line Positioning
In order to comply with Intel’s DC load line requirement, the reference voltage VREF
of load line positioning loop is a linear function of load current change ICC as has been
defined in (2-4). Ideally the reference voltage VREF and output voltage VCC should look like
the waveforms given in Fig. 2-16 (a), so that the AC output impedance ZLL can ideally
equal the DC load line resistance RLL for all load frequencies, as has been explained in
Section 2.2. However, if an abrupt step-up is applied to load and consequently an abrupt
step-down is applied to the reference, it will be difficult for output voltage VCC of the VR
to maintain a square waveform. This indeed is a double-step applied to the VR control
43
system. The double steps have the same directional effect on the output voltage of the VR.
The actual VCC waveform is illustrated in Fig. 2-16 (b).
ICC
ICC
 I CC
t
VREF
t
VCC
t
VREF
t
VCC
t
(a)
ICC
 I CC
 I CC
t
VREF
t
VCC
t
(b)
t
(c)
Fig. 2-18 Load line positioning waveforms: (a) ideal waveforms of VREF and VCC; (b) ideal waveform of VREF
and actual response of VCC; (c) waveforms of reshaped VREF and improved response of VCC
In order to reduce undershoot and overshoot resulting from the double-step effect,
we may slow down one of the steps simultaneously applied to the VR control system. The
actual slope of CPU current ICC is fixed, so we can only slow down the reference voltage,
as has been shown in Fig. 2-16 (c). In this way, the double-step effect can be minimized to
reduce output undershoot and overshoot voltage.
This slow-down of reference voltage can be achieved by adding some filtering effect
to the load line positioning loop. At the mean time, the small signal output impedance
Zo_closed of the VR should also be examined in the frequency domain to make sure the
applied slow-down effect on the reference voltage is acceptable in terms of undershoot and
overshoot at other load oscillation frequencies.
44
2.7 LOOP DESIGN APPROACHES AND ITS VALIDATION
Based on the small signal model of the VR and the closed loop transfer function of
the output voltage and phase current given in previous sections, the loop design of this VR
system is given and the method is validated. This complete model can be divided into three
independent loops and this proposed design approach can be validated thoroughly via
analysis and simulation implemented in Matlab. The small signal model reveals that the
bandwidth of the voltage mode control loop for voltage regulation and the bandwidth of
the phase current balancing loop for current sharing are independent of one another, and
thus the bandwidth of the two independent loops can be equally maximized when
necessary until limited by the VR switching frequency and the Nyquist sampling theorem.
The design specifications and component parameters of the VR are given in TABLE
2-1, which will be used throughout this chapter.
TABLE 2-1 VR design specifications and parameters
Vin
Input voltage
12Vdc
VCC
Output voltage
1.2Vdc
ICC
Load current
125A
ICC
Maximum load current step
95A
N
Number of phases
4
fsw
Switching frequency
250kHz and 400kHz
Lo
Phase inductor
320nH / 1m ESR
Co
Output capacitor
6×560µF + 18×22µF MLCC
RLL
Load line impedance
1m and 0m flat load line
fcv
Crossover frequency of voltage loop
50kHz
v
Phase margin of voltage loop
45 and 60
fcc
Crossover frequency of phase current balancing loop
50kHz
c
Phase margin of phase current balancing loop
45 and 60
45
2.7.1 Voltage Control Loop
Equation (2-17) gives the closed loop transfer function of the output voltage, which
is based on the assumption that the phase current is balanced. If the phase current is
assumed not to be balanced then the equation for the output voltage would be even more
complicated, and thus not efficient or practical to start a design. We can further assume
~
that the line variation v~in , load variation iCC , and noise v~noise in (2-17) are all zero. Thus,
v~CC can be rewritten in (2-28), in which Tvz(z) is given in (2-18) and it includes the load
line positioning loop with a non zero DC load line resistance. We notice that the transfer
function of Tvz(z) is complicated too and thus is still not practical as a starting point for the
voltage control loop design.
Gcv ( s )  Gm ( s )  G pv ( s ) ~
v~CC 
 vvid
1  Tvz ( s )
(2-28)
We can however further simplify the transfer function of the output voltage by
starting with a zero DC load line resistance loop, in which RLL = 0, so v~CC can be rewritten again in (2-29), in which Tv(s) is given in (2-19), which is simple compared to Tvz(s)
given in (2-18). This equation is now practical to start theoretical calculation of loop
stability and transient response design.
Gcv ( s )  Gm ( s )  G pv ( s ) ~
v~CC 
 vref
1  Tv ( s )
(2-29)
Based on the simplified voltage loop transfer function given in (2-29) with zero load
line resistance, we can plot the gain and phase curves of the voltage loop in Fig. 2-19. The
crossover frequency is selected at 50kHz as has been specified in TABLE 2-1. The
compensated control to output phase margin is 45º.
46
80
60
Gain (dB)
40
20
0
Open Loop Power Stage
‐20
Compensator
‐40
Control to Output
‐60
‐80
0.01
0.1
1
30
10
100
1000
10000
100
1000
10000
Frequency (kHz)
Phase (Degree)
0
‐30
‐60
‐90
‐120
Open Loop Power Stage
‐150
Compensator
Control to Output
‐180
‐210
0.01
0.1
1
10
Frequency (kHz)
Fig. 2-19 Gain and phase plots of voltage loop
In order to verify the above assumption and simplification, we need to plot the closed
loop gain and phase characteristics of the voltage loop v~CC / v~vid for DC load line slope
RLL=0 and RLL=1m. The plotted results are given in Fig. 2-20. We can notice that based
on the above design approach, the closed loop bandwidth of v~CC / v~vid when RLL = 1m is
reduced slightly compared to that when RLL = 0. However, this minor reduction in
bandwidth is acceptable. It is because the closed loop bandwidth of v~CC / v~vid is only
meaningful under Dynamic VID (DVID) operation [42] and such reduced bandwidth from
RLL = 0m to 1m is still sufficient to satisfy the required transient response of DVID
operation. When v~vid variation is zero, the closed loop transfer function of v~CC / v~ref can be
plotted in Fig. 2-21.
47
10
0
Gain (dB)
‐10
‐20
Closed Loop (RLL=0)
‐30
Closed Loop (RLL=1m)
‐40
‐50
‐60
0.01
0.1
1
30
10
100
1000
10000
100
1000
10000
Frequency (kHz)
Phase (Degree)
0
‐30
‐60
‐90
Closed Loop (RLL=0)
Closed Loop (RLL=1m)
‐120
‐150
‐180
0.01
0.1
1
10
Frequency (kHz)
Fig. 2-20 Gain and phase plots of closed loop transfer function of voltage loop ( v~CC / v~vid )
10
0
Gain (dB)
‐10
‐20
‐30
‐40
‐50
‐60
‐70
0.01
0.1
1
210
10
100
1000
10000
100
1000
10000
Frequency (kHz)
Phase (Degree)
180
150
120
90
60
30
0
‐30
0.01
0.1
1
10
Frequency (kHz)
Fig. 2-21 Gain and phase plots of closed loop transfer function v~CC / v~ref when v~vid  0
48
2.7.2 Phase Current Balancing Loop
Fig. 2-22 gives the control to output gain and phase characteristics of current
balancing loop. As mentioned earlier, the current balancing loop and voltage control loop
can be deemed independently of one another. The crossover frequency of the current loop
is chosen at 50kHz as shown in Fig. 2-22.
100
‐90
Gain
Phase
80
‐105
‐120
Gain (dB)
40
50kHz
‐135
20
0
‐150
Phase (Degree)
60
50kHz
‐20
‐165
‐40
‐60
‐180
0.1
1
10
100
1000
Frequency (kHz)
Fig. 2-22 Gain and phase plots of current balancing loop
Fig. 2-23 gives the closed loop gain and phase characteristics of the phase current
balancing loop. We can use the phase current with respect to phase average current as the
closed loop transfer function of current loop. The bandwidth of such a defined closed loop
is around 50kHz, the same as the designed. Ultimately, we may want to know how the
current in one phase is responding to the current perturbation in another phase. This kind
of closed loop gain and phase characteristics are also plotted in Fig. 2-23, which shows a
slight difference between the two definitions of closed loop phase current.
49
20
Gain (dB)
0
‐20
‐40
Closed Loop (I_Lo/I_avg)
‐60
Closed Loop (I_Lo2/I_Lo1)
‐80
‐100
0.01
0.1
1
60
10
100
1000
10000
100
1000
10000
Frequency (kHz)
Phase (Degree)
0
‐60
‐120
‐180
Closed Loop (I_Lo/I_avg)
‐240
Closed Loop (I_Lo2/I_Lo1)
‐300
‐360
0.01
0.1
1
10
Frequency (kHz)
Fig. 2-23 Gain and phase plots of closed loop transfer functions of current balancing loop
2.7.3 Output Impedance and Load Line
The open loop and closed loop small signal output impedance of the VR are plotted
for comparison in Fig. 2-24. The open loop output impedance has a very large value at the
cutoff frequency of the VR’s output filter around 10kHz. The cutoff frequency fcutoff is
given in (2-30). This large open loop output impedance in frequency domain implies
excessive undershoot and overshoot output voltage upon load steps in time domain, since
the VR is not close loop regulated. Once the VR is close loop regulated, its voltage
response is greatly improved, which is reflected in frequency domain as greatly reduced
output impedance.
50
1
f cutoff 
(2-30)
2    Le  C o
22
Output Impedance (m)
20
18
Zo_open
16
Zo_closed (RLL = 0)
14
Zo_closed (RLL = 1m)
12
10
8
6
4
2
0
0.01
0.1
1
10
100
1000
10000
Frequency (kHz)
Fig. 2-24 Open loop and closed loop output impedance
The closed loop output impedance for Intel’s RLL=1mΩ load line operation and
AMD’s RLL=0Ω flat load line operation are compared in Fig. 2-25. We can see that around
the 50kHz bandwidth frequency, the closed loop impedance of the zero load line operation
Output Impedance (m)
has a much larger value than that of the 1mΩ load line operation.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Zo_closed (RLL = 0)
Zo_closed (RLL = 1m)
0.01
0.1
1
10
100
1000
10000
Frequency (kHz)
Fig. 2-25 Comparison of closed loop output impedance for different load line resistance
51
2.7.4 Line Rejection
The closed loop line rejection curves the for zero and 1mΩ load lines are plotted in
Fig. 2-26, from which we can see that the VR with 1m load line operation has better line
rejection around the 50kHz bandwidth frequency.
0
‐10
Line Rejection (RLL = 0)
Line Rejction (dB)
‐20
Line Rejection (RLL = 1m)
‐30
‐40
‐50
‐60
‐70
‐80
‐90
‐100
0.01
0.1
1
10
100
1000
10000
Frequency (kHz)
Fig. 2-26 Closed loop line rejection of the VR for RLL=0 and RLL=1mΩ
2.7.5 Noise Rejection
The closed loop noise rejection is given in Fig. 2-26, from which we can also verify
that the bandwidth of the system is approximately 50kHz.
10
0
Gain (dB)
‐10
‐20
‐30
‐40
‐50
‐60
‐70
‐80
0.1
1
10
100
1000
Frequency (kHz)
Fig. 2-27 Closed loop noise rejection of the VR
52
10000
2.8 EFFECT OF LOAD MODEL
The load of the VR can be modeled as shown in Fig. 2-28. In this Intel load model,
there are motherboard, LGA775 socket, and VTT (Voltage Transient Test) tool parasitic
resistance and inductance [42]. Based on the given values of the parasitic resistance and
inductance, this load network is an asymmetrical network, which is connected to the North
Phase and East Phase of the VR.
The gate signals of the 4 phases of the VR are evenly phase shifted from phase-1 to
phase-4. If phase 1-2 and phase 3-4 are grouped together to supply the North Phase or East
Phase, then the output voltage ripple will be larger than that of the phase 1-3 and phase 2-4
grouping pattern. This is because the distribution of parasitic resistance and inductance
from the North Phase and East Phase to the final microprocessor load is asymmetrical.
Fig. 2-29 and Fig. 2-30 give the output voltage ripple for the above two phase
grouping patterns. It shows that using the phase 1-3 and 2-4 grouping pattern can help
reduce the output voltage ripple by about 1mV.
MOTHERBOARD
Lo_North_1
Controller
N1
RMB1
LGA775 Socket
LMB1
N2
N2
RSK1
LSK1
Lo_North_2
CMB1
RMB2
C1
RMB1
North
Bulk
Capacitors
RMB3
N3
4-Phase VRM/VRD
Voltage Transient Test (VTT) Tool
LMB2
LMB1
LMB3
N4
N4
RSK2
LSK2
LVTT2
RVTT2
LVTT1
RVTT1
CMB2
C2
RMB4
High
Frequency
Filtering
Capacitors
LMB4
RMB2
Lo_East_1
LMB2
RS
N5
RMB5
LMB5
N6
N6
RSK3
LSK3
Lo_East_2
CMB3
C3
RMB3
East
Bulk
Capacitors
LMB3
Fig. 2-28 Equivalent circuits of CPU load and parasitic of the motherboard and Socket [42]
53
I_PWL
Fig. 2-29 Output voltage ripple when phase 1-2 and phase 3-4 are grouped together
Fig. 2-30 Output voltage ripple when phase 1-3 and phase 2-4 are grouped together
If a simple resistive load is used in the small signal output impedance modeling
instead of the load model given in Fig. 2-28, we will find that the small signal output
impedance Zo_closed is smaller than the actual 1mΩ DC load line resistance setting at low
frequency (see Fig. 2-31). This difference is determined by the characteristics of the closed
loop system. However this difference will be minimized if the load model given in Fig.
2-28 is used for the small signal modeling of the output impedance.
54
4
Load Line Impedance (mOhm)
3.5
3
2.5
2
1.5
1
0.5
0
1
10
100
1000
10000
100000
Frequency (Hz)
Fig. 2-31 Small signal output impedance Zo_closed based on resistive load model
2.9 SIMULATION RESULTS
Simulations in PSpice and Matlab are carried out based on the parameters given in
TABLE 2-1. Fig. 2-32 gives the output voltage response upon 5A-120A/10kHz load steps.
Fig. 2-33 gives the waveforms of phase current upon 20A-120A/10kHz load conditions,
showing that the phase current can be quickly balanced upon load transients.
120A
80A
40A
SEL>>
0A
I(INTEL_LOAD_MODEL.I_PWL)
1.28
1.24
1.20
1.16
1.12
1.08
1.04
200us
250us
300us
350us
400us
V(INTEL_LOAD_MODEL:VCCSENSE,INTEL_LOAD_MODEL:VSSSENSE)
V(4PHASE_CONTROLLER.VID:+)-I(INTEL_LOAD_MODEL.I_PWL)*1E-3
Time
450us
500us
Fig. 2-32 Output voltage response upon load transients at 5A-120A/10kHz (VID=1.2Vdc)
55
140A
120A
100A
80A
60A
40A
20A
0A
50A
I(INTEL_LOAD_MODEL.I_PWL)
40A
30A
20A
10A
SEL>>
-10A
200us
I(4Phase_Buck.Lo1)
I(4PHASE_BUCK.Lo4)
300us
I(4Phase_Buck.Lo2)
400us
I(4PHASE_BUCK.Lo3)
500us
Time
Fig. 2-33 Waveforms of balanced phase current upon 20A-120A/10kHz load steps
Fig. 2-34 gives the phase current waveforms upon 20A-120A/100kHz load steps,
which takes about 100µs to be balanced. Fig. 2-35 gives the zoomed-in waveforms.
140A
120A
100A
80A
60A
40A
20A
0A
I(INTEL_LOAD_MODEL.I_PWL)
60A
50A
40A
30A
20A
10A
0A
SEL>>
-20A
200us
I_Lo1
300us
I_Lo2
I_Lo3
400us
I_Lo4
500us
600us
700us
800us
Time
Fig. 2-34 Waveforms of balanced phase current upon 20A-120A/100kHz load steps
56
140A
120A
100A
80A
60A
40A
20A
0A
I(INTEL_LOAD_MODEL.I_PWL)
50A
40A
30A
20A
10A
0A
SEL>>
-10A
700us
I_Lo1
I_Lo2
720us
I_Lo3
740us
I_Lo4
760us
780us
800us
Time
Fig. 2-35 Zoomed-in waveforms of balanced phase current upon 20A-120A/100kHz load steps in Fig. 2-34
Fig. 2-36 gives the frequency spectrum of the phase current in Fig. 2-35. The current
amplitude of each phase at different frequencies is identical, except for at 50kHz.
25
Phase Current (A)
20
I_Lo4
I_Lo3
I_Lo2
I_Lo1
15
50kHz
10
100kHz
250kHz
5
0
0
50
100
150
200
250
300
Frequency (kHz)
Fig. 2-36 Frequency spectrum of phase current given in Fig. 3-35
57
Fig. 2-37 gives the zoomed-in spectrum around 50kHz in Fig. 2-36. It shows that the
current amplitude of phase 1 and phase 3 is slightly larger than that of phase 2 and phase 4.
However, this difference is not very significant, and thus we can still consider the phase
current is balanced under 100kHz load oscillation.
22
20
Phase Current (A)
18
16
I_Lo4
I_Lo3
14
I_Lo2
I_Lo1
12
10
8
6
4
2
0
0
50
100
Frequency (kHz)
Fig. 2-37 Zoomed-in frequency spectrum in Fig. 3-36
Fig. 2-38 gives the waveforms of phase current under 120A static load current,
showing that the phases are equally sharing the load current.
45A
40A
35A
30A
25A
20A
15A
480us
482us
484us
I(4Phase_Buck.ESR_Lo1) I(4Phase_Buck.ESR_Lo2)
486us
I(4Phase_Buck.ESR_Lo3)
Time
488us
490us
I(4Phase_Buck.ESR_Lo4)
Fig. 2-38 Waveforms of phase current under 120A static load current
58
Fig. 2-39 gives the simulation result in Matlab, showing that the phase current is
balanced at 10kHz load steps. The result in Fig. 2-40 verifies that with the design the load
current can be shared among phases even if the phase inductor values are not identical.
Fig. 2-39 Waveforms of balanced phase current upon 20A-120A/10kHz load steps
[ICC: y-axis 5A/div, x-axis 50µs/div]
Fig. 2-40 Waveforms of phase current under 120A load condition (Lo1=220nH, Lo3-Lo4=320nH)
[ICC: y-axis 5A/div, x-axis 2µs/div]
59
Fig. 2-41 gives the bode plots of control to output of voltage control loop simulated
in Matlab, from which we can see the bandwidth of the voltage loop is about 50kHz. Fig.
2-42 gives the bode plots of control to output of the current balancing loop, whose
bandwidth is also 50kHz.
60
40
Gain (dB)
20
0
-20
-40
Phase (Degree)
-60
1kHz
0
10kHz
100kHz
1MHz
100kHz
1MHz
-45
-90
-135
-180
-225
-270
1kHz
10kHz
Frequency (Hz)
Fig. 2-41 Bode plots of control to output of voltage control loop
Bode Plot of Control to Output
60
Gain (dB)
40
20
X: 5e+004
Y: 0.2488
0
-20
-40
1kHz
10kHz
100kHz
1MHz
100kHz
1MHz
Phase (Degree)
-90
-120
-150
-180
1kHz
10kHz
Frequency
Fig. 2-42 Bode plots of control to output of phase current balancing loop
60
2.10 SUMMARY
A voltage mode controlled phase current balancing technique is presented to power
high frequency dynamic load. Based on the analysis and the proposed small signal model,
the voltage control and the phase current balancing loop can be considered independent of
one another, and thus the bandwidth of each loop can be designed independently.
The bandwidth of the voltage control loop will be maximized and optimized for the
VR, so that the output voltage can respond quickly to high frequency dynamic load to
satisfy the AC output impedance requirement. The bandwidth of the phase current
balancing loop will also be maximized so that the phase current can respond quickly at
load steps and be balanced under high frequency oscillating load. In addition, the high
bandwidth design of the phase current balancing loop will help eliminate phase current
high amplitude oscillation due to the beat frequency effect.
The presented control method, its modeling and design approach provide the solution
to supply a high frequency dynamic load for VR applications. They can also be used to
parallel other AC-DC and DC-DC converters with similar high frequency dynamic loads.
61
CHAPTER 3
VOLTAGE REGULATOR WITH DIGITALLY IMPLEMENTED
NON-LINEAR VOLTAGE MODE CONTROL
3.1 INTRODUCTION
As has been analyzed in section 1.2.6, given the same bandwidth, the conventional
current mode control for switch mode power supplies does not provide superior transient
response in the term of the output voltage undershoot or overshoot upon large signal
stimulus, which is one of the most challenging conditions in VR designs. Another
motivation to implement voltage mode control is that for certain VRs such as simple single
phase VR, if the current control loop can be eliminated, then the required current sense
circuits for current mode control could be potentially simplified or eliminated, which will
further reduce the complexity and cost of the VR.
In this chapter, a VR with fast load transient response is introduced. Voltage mode
control is applied to the VR when the load current is static or in small variations. The VR
is however designed to operate in non-linear operation mode when certain load transient
occurs. A prediction method for load current change is introduced for the non-linear
operation. In order to implement the proposed non-linear control algorithm, a digital
control approach is adopted. The architecture and the control algorithm of the proposed
digital controller are given in this chapter. Other performances of concern such as the
overshoot and power losses of the non-linear VR are also analyzed in detail in this chapter.
Simulation and experimental results are given in the end of the chapter to verify the
performance of the proposed control method of the VR.
62
3.2 PREDICTIVE NON-LINEAR VOLTAGE MODE CONTROL
3.2.1 Operation of the Non-Linear Voltage Mode Control
The conventional voltage mode control method for switch mode power supply is
based on the linearized small signal model of the converter [55, 60]. No matter how wide
the bandwidth of the converter has been designed, with large signal changes such as large
load steps, the converter will reach its response limit. This is predetermined by the blank
interval between discrete gate signals, the inherent operation nature of switch mode power
supplies. For example, if a load step-up occurs in the blank interval between two gate
signals, nothing can be done by the linear control loop of the converter to react to the
stimulus during this interval, no matter how wide the VR’s small signal bandwidth is
designed to be. This is because the next gate pulse will always come after a delayed time
determined by the fixed switching frequency. Such a blank zone of response to large
signals will lead to excessive voltage droop. This phenomenon is well illustrated in Fig.
3-1.
Vo
Vo
t
Io
VGS_HS
I o
Ts
DTs
Ts
t
t
t
VGS_LS
t
Fig. 3-1 Transient response of conventional voltage mode control
63
Increasing the switching frequency of the switch mode power converter will reduce
the interval between two adjacent gate pulses, thus reducing the delay of the VR in
responding to large load transients. Fig. 1-6 gives the step load response of a VR switching
at 250kHz, 500kHz, 1MHz, 5MHz, and 10MHz respectively. It shows that higher
switching frequency enables faster response and less voltage droop upon a load step-up. As
explained in Section 1.2.4, switching at higher frequency will result in lower overall
system efficiency unless certain resonant techniques are applied to achieve ZVS or ZCS to
reduce the switching losses. The increased complexity of the circuit will increase the cost
of the VR accordingly.
It is therefore desirable to operate the VR at a lower switching frequency to obtain
higher efficiency and at the same time to enable the converter to respond to load transient
even during the interval of two gate pulses at a fixed switching frequency. This concept is
well illustrated in Fig. 3-2, in which VGS_HS and VGS_LS are the gate signals to the high side
and the low side MOSFETs of a single phase buck converter. During the Normal Steady
State Mode, the high side and low side MOSFETs are conducting complementary at a
fixed frequency fsw, and the time difference between the two consecutive gate pulses is Tsw.
Once the load current ICC steps up ICC and after a delay time td, the high side MOSFET
will be turned on, although according to the linear fixed switching frequency the high side
MOSFET should be turned on at a much later time at t4. This additional non-linearly
generated gate pulse will therefore result in a much earlier high side MOSFET turn-on to
provide additional conduction time for the VR, which is also sufficient to transfer the
needed current from the input power source to the load. The turn-on time of the nonlinearly generated gate pulse is defined as ta here. This gate pulse during load transient is
64
independent from other gate pulses in Normal Steady State Mode on the time line. Its pulse
width could be merged with its adjacent Normal Steady State Mode gate pulses or with a
certain gap between one another, which totally depends on the transient operating
condition of the converter. The duration of ta is defined as the duration of Transient Mode.
The low side MOSFET of the buck converter is conducting complementary to the high
side MOSFET either in Normal Steady State Mode or in Transient Mode as illustrated in
Fig. 3-2.
VCC
1.2V
 V CC
1.15V
t
ICC
 I CC
t
td
ILo
Tsw
Tsw
ta
D·Tsw
t
VGS_HS
Tsw
t
Normal Steady State Mode
t
Tsw
VGS_LS
Normal Steady State Mode
Transient
Mode
t1 t2
t3 t4
Fig. 3-2 Transient response of non-linear voltage mode control during load step up
The merit of such non-linear behavior enables the VR to operate at a relatively
lower switching frequency for higher efficiency and at the same time to be able to respond
fast to load transients, independent of the switching frequency.
65
The above introduction to the non-linear operation uses a single phase buck
converter as an example to illustrate the operation of the VR at load step-up. For
multiphase VR, the non-linear operation upon load current step-up and step-down is
similar to that of a single phase VR. Its operation is described in detail below. The
schematic of such a four-phase interleaved buck converter topology is given in Fig. 3-3.
Fig. 3-3 Four-phase interleaved buck converter
The waveforms of linear and non-linear operation of the four-phase VR given in
Fig. 3-3 is illustrated in Fig. 3-4, in which VGS1_HS to VGS4_HS and VGS1_LS to VGS4_LS are the
gate signals of the high side MOSFETs Q1_HS-Q4_HS and low side MOSFETs Q1_LS-Q4_LS in
each phase of the VR. VCC is the output voltage and ICC is the load current. ILo1 is the
current through the phase inductor Lo1 annotated in Fig. 3-3.
66
2000A / s
 I CC
2000A / s
 V CC
Fig. 3-4 Waveforms of the 4-phase VR during Normal Steady State Mode and Transient Modes
67
In general, the operation of the proposed non-linearly regulated VR can be divided
into three operation modes: (1) Normal Steady State Mode when the load current is static
or with little variation; (2) Transient-Up Mode for load step-up condition; and (3)
Transient-Down Mode for load step-down condition (load release).
3.2.1.1 Normal Steady State Mode
The following time segments t0t2, t3t6, and t8∞ shown in Fig. 3-4, are the
time duration when the VR is operating in Normal Steady State Mode. During Normal
Steady State Mode, the load current is static and can be considered as a constant current
source. The high side and low side MOSFETs in each phase of the VR are conducting
complementarily at a fixed frequency fsw. The time interval between two consecutive gate
pulses is (Tsw-D·Tsw). Fig. 3-5 gives the paths of current flow during Normal Steady State
Mode, in which Le is the equivalent inductance of the multiphase bulk converter given in
(3-1). QHS is the equivalent power switch of the high side MOSFETs in all the phases, and
QLS is the equivalent power switch of the low side MOSFETs in all the phases. Fig. 3-5 (a)
shows that the high side MOSFETs are conducting to deliver the power from the input
source to the load via phase inductors for duration of DTsw in one switching cycle Tsw. Fig.
3-5 (a) shows that in the rest of one switching cycle, the low side MOSFETs are
conducting to let phase inductors to have current flow path to keep supplying the load with
the stored energy for duration of (Tsw-D·Tsw).
Le 
Lo
N
68
(3-1)
(a)
(b)
Fig. 3-5 Paths of current flow during Normal Steady State Mode: (a) high side MOSFET is conducting; (b)
low side MOSFET is conducting
In this mode, the VR behaves no different from a conventional VR. Its steady state
design and control loop design is the same as that of conventional VR, except for the
determination of the output capacitance, which is now a ripple voltage oriented design
instead of an output voltage undershoot or overshoot oriented in conventional VR design.
Usually, the constraints brought by output voltage undershoot or overshoot requires more
output capacitance than by output voltage ripple. The proposed non-linear control requires
less output capacitance than that of the conventionally controlled VR.
3.2.1.2 Transient-Up Mode
Once the load current ICC steps up with a magnitude of ICC and after a delay time
td, the VR will exit its linear Normal Steady State Mode and enter its non-linear operation
mode: Transient-Up Mode, in which all the high side MOSFETs of the VR will be turned
on, even though according to the linear fixed switching frequency the high side MOSFETs
should be turned on at a much later time for instance, at t4 in Fig. 3-4.
Fig. 3-6 demonstrates the paths of current flow during Transient-Up Mode, which
corresponds to the time segment t2t3 in Fig. 3-4. In this duration, all the high side
MOSFETs QHS are conducting to deliver the power from the input source to the load via
the phase inductors, while all the low side MOSFETs are turned off. In Transient-Up Mode
69
the high side MOSFETs conduct for the duration of ta_up, which is different from the
duration DTsw defined in Normal Steady State Mode. Once the Transient-Up Mode is over,
the VR goes back to Normal Steady State Mode. Its gate signals and current paths are once
again the same as that described in Section 3.2.1.1.
QHS
Vin
Le
QLS
Co
ICC
Fig. 3-6 Paths of current flow during Transient-Up Mode
This additional non-linearly generated gate pulse in Transient-Up Mode will
therefore enable a much earlier high side MOSFET turn-on without switching the VR at
high frequency and provide sufficient conduction time for the energy to be transferred
from the input power source to the load upon a load step-up. The on time of the nonlinearly generated gate pulse is defined as ta_up. This gate pulse at transient is independent
of other gate pulses. Its pulse width can be merged with its adjacent Normal Steady State
Mode gate pulses before or after Transient-Up Mode, or with a certain gap, which totally
depends on the transient operation condition of the converter. For example, the transient
gate pulse between t2 and t3 in Fig. 3-3 is inserted between two gate pulses of phase 1 and
phase 2, but does not merge with any gate pulses generated from normal steady state
operation. This inserted transient pulse however merges with adjacent gate pulses of phase
3 and phase 4 generated by the Normal Steady State Mode operation.
70
The duration of ta_up is determined by the load current changes, which can be
predicted according to the slope of output voltage at load transient. The theoretical analysis
of the prediction will be given in Section 3.2.2. The low-side MOSFETs are always
conducting complementary to the high-side MOSFETs in Normal Steady State Mode or in
Transient-Up Mode as being illustrated in Fig. 3-4.
3.2.1.3 Transient-Down Mode
When the load current steps down at time t5 in Fig. 3-4, and after a delay time td2,
the VR enters Transient-Down Mode, in which all the high-side MOSFETs are turned off
at t6 for duration of ta_down. Thus no current will be injected from the input power source to
the load via the high side MOSFETs to further increase the overshoot voltage at the output
upon a load release. The duration ta_down of Transient-Down Mode at load current step
down can also be calculated, which will be given in Section 3.2.2. After time t8 in Fig. 3-4,
the VR ends Transient-Down Mode and resumes its Normal Steady State Mode operation.
The low-side MOSFETs of the VR are turned on and will be kept on during this
period of time. The output current will flow through the phase inductors, the output
capacitors, the low side MOSFETs and their body diodes. The current paths are illustrated
in Fig. 3-7 (a). In this way, the input power source is cut off from keeping supplying
unnecessary power to the already reduced load current demand. In this way the output
voltage overshoot can be reduced compared to conventional linear control method, which
enables the high side MOSFETs conduct because of the fixed switching frequency fsw even
upon a large load release.
Furthermore, the low side MOSFETs can also be turned off as has been shown by
the red lines in Fig. 3-4 from time t6 to t8, so as to let their body diode freewheel the output
71
current as shown in Fig. 3-7 (b). Since the body diode has a voltage drop once it forward
conducts, this forward voltage drop will be negatively applied to the phase inductor. Since
the forward voltage of the body diode is quite comparable to the output voltage of the VR,
the output voltage overshoot upon a load release can be further reduced by the negatively
applied forward voltage of the body diode. The equivalent circuits corresponding to the
circuits shown in Fig. 3-7 and the theoretical analysis of the output voltage overshoot in
Transient-Down Mode will be given in detail in Section 3.4.
(a)
(b)
Fig. 3-7 Paths of current flow during Transient-Down Mode: (a) low side MOSFETs are turned on; (b) low
side MOSFETs are turned off
3.2.2 Prediction for Non-Linear Operation
As described earlier in Section 3.2.1, from Normal Steady State Mode to Transient
Modes, one of the tasks of the proposed non-linear controller is to determine the duration
of the non-linear operation modes, which requires that the change of the load current ICC
be known in advance so as to determine the necessary duration for the transient mode
operation to enhance the transient performance of the VR. The conventional way to
measure the total current of the VR is to measure the current through the output inductor of
each phase. Unfortunately, this summed total current can only represent the load current in
a steady state. This is because the measured total inductor current always lags the change
72
of the actual load current significantly due to the impedance effect of the output inductor in
each phase and the fast slew rate of the load current, at 2000A/µs for instance. Thus the
measured total current of the VR cannot represent the real time load current during fast
load transients. This is illustrated clearly in Fig. 3-8 clearly, in which the red line is the
actual CUP load current with a very steep rise. The blue line is the measured inductor
current with a very slow rise.
Q
Fig. 3-8 Measured total inductor current and load current
From time t1 to t2 in Fig. 3-8, if the measured inductor current iLo(t) is used to
represent the actual CPU load current icpu(t), then there will be certain electric charges not
included in the consideration of the actual demand of the CPU load. Such a difference
between the measured current and the actual load current in the term of difference in
electric charge Q is given in (3-2). Due to the large difference of the slope of the inductor
current and the actual load current, the difference in electric charge Q will be significant,
which implies that using the measured inductor current to represent the CPU load current
during load transients is not practical.
73


Q   icpu t   i Lo t   dt
t2
t1
(3-2)
The CPU load current ICC cannot be effectively measured in real time during load
transients. We can, however, predict the load current change ICC according to the output
voltage slope dvCC/dt. Once the load current change is obtained, the duration of the nonlinear Transient Modes can also be determined.
In this section, a mathematical approach is taken to predict the load current change
and to determine the duration for non-linear operation of the VR. A small signal model of
the VR is presented to help understand the control system of the VR so as to theoretically
calculate the above required value.
3.2.2.1 Frequency Domain Model of the VR for Prediction
Chapter 2 presented the detailed small signal model of the VR. Since the controller
is virtually voltage mode controlled and the voltage control loop and the phase current
balancing loop are independent of one another, the small signal model of the VR can be
simplified as shown in Fig. 3-9, in which only the voltage control loop is included for
consideration. The current balancing loop is therefore removed from the model in the
following analysis, and such removal will not affect the validity of the analysis. This
simplified linear model is an equivalent model of the multiphase VR.
The small signal output voltage in the frequency domain can thus be expressed in
(3-3). Zo is the open loop output impedance of the VR given in (3-4). Gpv(s) in (3-5) gives
the transfer function of the power stage. Tv(s) in (3-6) gives the transfer function of the
control to output of the voltage mode controlled VR system.
74
~
iCC
v~in
v~ref
v~err
v~cv
~
dv
v~CC
v~noise
Fig. 3-9 Brief block diagram of the VR system
Gcv ( s )  Gm ( s )  G pv ( s ) ~
G gv ( s ) ~
v~CC 
 v ref 
 vin
1  Tv ( s )
1  Tv ( s )

Z o (s) 
(3-3)
Z o _ open ( s ) ~
T ( s) ~
 iCC  v
 vnoise
1  Tv ( s )
1  Tv ( s )
( Le  Co  r )  s 2  (Co  Rd  r  Le )  s  Rd
( Le  Co )  s 2  ( Rd  Co  r  Co  Le / Rd )  s  1
G pv ( s ) 
Vo  r /( D  Le )  s  Vo /( D  Le  Co )
2
s  (1 /( RL  Co )  r / Le )  s  1 /( Le  Co )
Tv ( s)  Gcv ( s)  Gm ( s)  G pv ( s)  H sv ( s )
(3-4)
(3-5)
(3-6)
3.2.2.2 Theoretical Calculation for Prediction
From (3-3) we can derive the expression of the output voltage in time domain,
which is given in (3-7). The slew rate dvCC/dt or the derivative of the output voltage at time
td can therefore be expressed in (3-8). By solving (3-8), dvCC/dt at the delayed time td can
be expressed as a function proportional to the change of the load current ICC, as has been
given in (3-9).
75
G gv ~ 
 Gcv  Gm  G pv ~

 vref 
 vin 
1  Tv
1  Tv

1  st 
vCC (t ) 
e 
  ds



Z o _ open ~
2
T
~
v


 1  T  iCC  1  T  vnoise 
v
v


dvCC (t )
dt td


d  1

dt  2


G gv ~  
 Gcv  Gm  G pv ~

 vref 
 vin  
1  Tv
1  Tv
 st 
 
  ds 
 e   Z o _ open ~
T
v
~


 1  T  iCC  1  T  vnoise  
v
v

  td
dvCC (t )
 f (I CC ) t
d
dt td
(3-7)
(3-8)
(3-9)
The detailed expression of dvCC/dt given in (3-9) can be obtained with the aid of
mathematic CAD software such as Matlab. The output voltage slope dvcc/dt at time td can
therefore be theoretically calculated. The theoretical calculation results are verified by
comparing them to PSpice circuit simulation results and Simulink system simulation
results plotted in Fig. 3-10, as a function of the load current change ICC in percentage
terms. The plotted results in Fig. 3-10 show that the calculation results are very close to
those of the simulation.
76
50
45
Io,max=25A, Vo=1.5V
dv/dt (-V/ms)
40
35
30
25
20
Theoretical
15
Simulink
10
PSpice
5
0
0
10
20
30
40
50
60
70
80
90
100
Load Current Step Up (%)
Fig. 3-10 Output voltage slope versus load current steps
The expression of the output voltage slope given in (3-9) is a general format to
calculate the slope at any time td after a load step occurs. Its detailed expression is however
complicated and requires a mathematics CAD tool to aid in the calculation. We can
simplify the expression by assuming the delay time is zero, i.e. td=0, based upon which the
output voltage slope can be approximately given in (3-10). In the expression, Cbulk and Ccer
are the capacitance of the bulk capacitors and MLCC capacitors of the VR respectively.
rbulk and rcer are the ESR of the buck capacitors and the MLCC capacitors respectively.
I CC
dvCC (t )


dt t 0 Cbulk  C cer
 Cbulk 3  Ccer  rbullk 2  Cbulk  Ccer 3  rcer 2  2Cbulk 2  Ccer 2  rbulk  rcer 
1 

Cbulk  Ccer  rbulk  Cbulk  Ccer  rcer 2


(3-10)
Once the derivative of the output voltage is obtained through circuit detection, the
change of the load current ICC can be predicted from (3-9) or (3-10), and is given in
(3-11).
77
 dv (t ) 
I CC  f  CC

 dt td 
(3-11)
The duration for the non-linear operation of the VR during Transient-Up Mode and
Transient-Down Mode can therefore be obtained once the load current change ICC is
predicted from the detected output voltage slope dvCC/dt. The duration of transient mode
operation ta_up and ta_down is given in (3-12) and (3-13) respectively, in which Le is the
equivalent inductance of a multiphase VR. The duration ta_up can range from 200ns to 1µs.
The duration ta_down can range from 1µs-4µs, depending on the circuit parameters and the
actual load current changes.
t a _ up 
Le  I CC
Le


Vin  VCC  Vin  VCC 
t a _ down 
 dv (t ) 
f  CC

 dt t 0 
 dv (t ) 
Le  I CC
L
 e  f  CC

VCC
VCC  dt t 0 
(3-12)
(3-13)
3.2.3 Non-Linear Control and Switching Frequency
The non-linear voltage mode control method described in previous sections can
accelerate the response of the VR during load transients. PSpice simulation results of
conventionally controlled VR and non-linearly controlled VR are compared in Fig. 3-11,
which shows that the output voltage undershoot of the proposed non-linear control method
is only half of that of the conventional method. In this comparison simulation, a single
phase VR is used and in both cases the switching frequency is 250kHz. The input and
output voltage of the single phase VR are 12Vdc and 1.5Vdc respectively. The rated output
load current is 25A and the load step-up is from 0.5A to 25A with a slew rate of 1000A/µs.
78
Fig. 3-11 Simulated output voltage step responses of conventional and proposed control method (fsw=250kHz)
The proposed non-linear control method makes it possible for the VR to switch at a
frequency below 500kHz for the purpose of high efficiency and at the same time to achieve
fast transient response with reduced output capacitance. Once the non-linear control is
applied, it is then not necessary to further increase the switching frequency of the VR,
because the further increased frequency will not further improve the transient response of
the VR.
This phenomenon is verified by the simulation of the same single phase VR. Fig.
3-12 gives the waveforms of the step response of the VR operating at 250kHz with the
proposed non-linear voltage mode control, operating at 5MHz with conventional control,
and operating at 5MHz with the proposed non-linear voltage mode control. As we can see
from the figure, the three approaches demonstrate very similar load transient responses,
especially in terms of voltage undershoot upon a load step-up. We can see from the
simulation results that, given the same circuit parameters, in order to achieve similar
transient response as that of non-linear voltage mode control, the conventional voltage
79
mode control needs to increase its switching frequency from 250kHz to approximate
5MHz. Although the circuit parameters can be optimized as the frequency increases, it still
requires the VR to switch at about 1-2MHz in practice to achieve similar transient
performance. On the other hand, if the proposed non-linear voltage mode control has been
applied, then increasing the switching frequency from 250kHz to 5MHz for instance will
not further improve the VR’s transient response.
1.55V
Conventional Control
(fsw=5MHz)
Non-Linear Control
(fsw=250kHz)
Non-Linear Control
(fsw=5MHz)
1.50V
1.45V
1.40V
0s
50us
V(Vo)
100us
150us
200us
250us
300us
350us
400us
Time
Fig. 3-12 Simulated output voltage step responses of conventional and proposed non-linear control method
(fsw=250kHz and 5MHz)
In conclusion, the relationship between the proposed non-linear control and the
switching frequency of the VR is that the proposed non-linear control method improves the
transient performance of the VR, thus enabling the VR to operate at a lower frequency for
higher efficiency. Once the non-linear control is applied, keeping on increasing the
switching frequency will not further improve the transient performance of the VR.
80
3.3 DIGITAL IMPLEMENTATION OF THE CONTROL
3.3.1 Architecture of the Digital Controller
Digital control is flexible in terms of realizing a customized control algorithm or
complicated control method which is difficult to realize by means of a conventional analog
control circuit. Digital control for system control has been introduced in many literatures
[18, 24, 25, 34, 45, 56, 61]. For the non-linear control method proposed in this chapter,
adopting digital signal processing (DSP) is a necessary approach in order to implement the
proposed control. Fig. 3-13 gives a brief block diagram of a four-phase digital controller,
which shows the voltage regulation portion of the digital IC for the four-phase VR given in
Fig. 3-3.
Digital IC Controller for Multiple-Phase VRM
Gate Drives
Multiple-Phase Gate Generator
Phase 1
Gate Drive
Phase 1
Sync-Gate
Phase 2
Gate Drive
Phase 2
Sync-Gate
Digital PWM
Phase Shift
Generator
Phase 3
Gate Drive
Phase 3
Sync-Gate
Phase 3
Gate Drive
Phase 4
Sync-Gate
DSP
Dynamic
Gating
Algorithm for
Dynamics
Synchronous
Gating
dV/dt
Steady State
Digital PWM
Digital (PID)
Compensator
ADC
VCC
Fig. 3-13 Brief block diagram of the proposed digital controller for voltage regulation
In Fig. 3-13, the sensed output voltage VCC is first sampled and analog to digital
converted by an internal analog-to-digital converter (ADC). The digitized output voltage is
sent to the Digital Compensator for the output voltage regulation in Normal Steady State
81
Mode. It is also sent to the Algorithm for Dynamics block to determine the transient
operations of the controller based on the sensed output voltage and its slope. Based on the
operating conditions of the VR, the output of the Digital Compensator and the Algorithm
for Dynamics block will be combined together to generate the gate signals of the high side
and low side MOSFETs of the VR. The Multiphase Gate Generator will make sure the
gate signal of each phase of the VR is equally phase shifted. The gate signals of each phase
will finally be sent out of the controller to the gate drives of the power MOSFETs. The
gate drives can be integrated in the controller IC or as separate devices outside of the chip,
which depends on the specific application of the VR.
The architecture of the proposed digital controller IC for a 4-phase VR is given in
the block diagram in Fig. 3-14, which includes the major functionalities required by the
VR to power Intel’s microprocessors. In this block diagram, LL[0:1] is the DC load line
configuration signal and VID[0:7] is the output voltage setting signal, both of which are
the signals from the microprocessor to configure the VR. A Non-Volatile Memory (NVM)
is used to store the parameters of the digitally implemented controller. There is an I2C Bus
block to program the NVM with the external address and data signal pins. The output
voltage and the phase current of the VR are sensed and converted to digital signals by two
separate ADC Converters. Other major functional blocks are the Digital PID Compensator,
the Digital PWM Generator, Dynamic Controller, and the Phase Current Balance for the
steady state and transient operation of the VR.
82
HIGH-PRECISION
REFERENCE
SCL
I2C Bus
SDA
NON-VOLATILE
MEMORY
RESET
OTHER CHIP
MANAGEMENT
OUTEN
LL1
LL0
PWR
VRPRES
PWRGD
LOAD
LINE
LOAD
INDICATOR
LDICATOR
VID7
OSCILLATOR
SOFT
START
VID6
VID5
VID4
VID [7:0]
VID3
DECODER
DIGITAL
REFERENCE
CONTROL
DIGITAL
PID
PH1
VID2
DAC
VID1
EN1
VID0
VSENSE
ADC
DA
VCC_SENSE
PH2
DYNAMIC
CONTROL
DIGITAL
EN2
PWM
VSS_SENSE
GENERATOR
VIN
LOW
VINSENSE
PH3
EN3
ISENP4
ISENN4
PH4
ISENP3
ISENN3
ISENP2
ISENN2
MUX
ISENSE
ADC
ICC/VIN/TEMP
DECODER
PHASE
CURRENT
BALANCE
EN4
ISENP1
ISENN1
TEMPSENSE
TEMPERATURE
VRHOT
GND
Fig. 3-14 Architecture of the proposed digital controller IC
3.3.2 Digital Compensation for Normal Steady State Mode
In Normal Steady State Mode, the VR is regulated via conventional voltage mode
control, which is also shown in the architecture of the digital controller given in Fig. 3-13.
The sensed output voltage VCC is first digitized by the ADC of the proposed digital
controller, then the digitized sensed voltage vsense(n) is compared with the digitized
83
reference voltage vref(n), as shown in Fig. 3-15, in which n denotes the nth sampling
interval. Their difference is the error voltage e(n), which is then processed by a Digital
Compensator. The output of the Digital Compensator is the discrete time domain control
voltage denoted as y(n) in Fig. 3-15, which corresponds to the control voltage vcv(s) in
continuous time domain.

Fig. 3-15 Digital Compensator of the VR
The switching frequency fsw of the VR is chosen around 250kHz. The actual
sampling frequency of the Digital Compensator fSAMP_COMP is chosen much higher than the
switching frequency fsw of the VR. The actual sampling frequency of the voltage ADC
fSAMP_ADC is chosen much higher than the switching frequency fsw of the VR. The
relationship between the sampling frequency fSAMP_ADC of the ADC, the sampling
frequency fSAMP_COMP of the Digital Compensator, and the switching frequency fsw of the
VR is given in (3-14). In this way the processing speed of the Digital Compensator can be
increased, so that the effect of real time delay due to the digital processing can be
minimized. Therefore, the disagreement between the digital compensation and analog
compensation in frequency domain can also be minimized, so that the control loop design
can be simplified.
f SAMP _ ADC  f SAMP _ COMP  f sw
84
(3-14)
The discrete control signal y(n) is given in (3-15) as a function of the error signal
e(n). In the expression, g0, g1, g2, h1, h2, and h3 are the coefficients of the Digital
Compensator.
yn   g 0  en  g1  en1  g 2  en2   h1  yn1  h2  yn2  h3  yn3 
(3-15)
The Digital Compensator therefore calculates the equation given in (3-15), and
such processing can be implemented by the brief building block given in Fig. 3-16.
Fig. 3-16 Implementation of the Digital Compensator
Fig. 3-17 gives the bode plots of control to output of the VR. Both the continuous
and discrete time bode plots are plotted in the same figure. The two pairs of gain and phase
curves show no significant difference. This is because the actual sampling frequency of the
Digital Compensator fSAMP_COMP and the actual sampling frequency of the ADC fSAMP_ADC is
much higher than the switching frequency fsw of the VR as has been given in (3-14).
85
Bode Diagram
60
Magnitude (dB)
40
20
0
-20
Phase (deg)
-40
-45
-90
-135
-180
3
10
4
5
10
6
10
10
Frequency (Hz)
Fig. 3-17 Bode plots of control to output in continuous and discrete time domain
Fig. 3-18 gives the closed loop bode plots of the VR in continuous and discrete
time domain. Fig. 3-19 and Fig. 3-20 give the root locus plot and Nyquist plot of the
control to output of the VR respectively. Fig. 3-21 gives the step response of the
compensated VR.
Bode Diagram
Magnitude (dB)
20
0
-20
-40
45
Phase (deg)
0
-45
-90
-135
-180
1
10
2
10
3
4
10
10
5
10
Frequency (Hz)
Fig. 3-18 Bode plots of closed loop of the VR
86
6
10
6
3
Root Locus
x 10
0.25
0.18
0.125
0.085 0.055 0.025
4e+005
3e+005
2 0.38
2e+005
Imaginary Axis
1 0.65
1e+005
0
1e+005
-1 0.65
2e+005
-2 0.38
-3
-8
3e+005
0.25
0.18
-7
-6
4e+005
0.085 0.055 0.025
0.125
-5
-4
-3
-2
-1
0
1
5
Real Axis
x 10
Fig. 3-19 Root locus plot of control to output
Nyquist Diagram
200
0 dB
150
Imaginary Axis
100
50
0
-50
-100
-150
-200
-20
-15
-10
-5
0
Real Axis
Fig. 3-20 Nyquist plot of control to output
87
5
Step Response
1.4
1.2
Amplitude
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
Time (sec)
6
7
-5
x 10
Fig. 3-21 Step response of the VR system
3.3.3 Control Algorithm for Transient Modes
Once large load transients occur, the digital controller enters Transient Modes. The
flow chart for load step-up is given in Fig. 3-22. If the derivative of the output voltage is
negative and exceeds a certain threshold value, implying the load current step-up change
exceeds a certain percentage, the control circuit will activate the Transient-Up Mode. The
length of time ta_up for the response acceleration is determined by the detected output
voltage slew rate and the circuit parameters.
88
Vcc
dv/dt
Filter
= f (dv/dt)
>
th
?
Yes
Yes
Start
Transient_Up
Gate Pulse
ta_up
Digital
Compensator
d = f (Vo)
Vo < Vth ?
No
No
Steady State
Digital PWM
Stop
Transient_Up
Gate Pulse
ta_up = f ( )
Combine
Gate for SS and
Transient
Fig. 3-22 Flow chart of the control algorithm during Normal Steady State Mode and Transient-Up Mode
If the derivative of the output voltage is positive and exceeds a certain threshold
value, implying the load current step-down change exceeds a certain percentage, the
control circuit will activate the Transient-Down Mode. The flow chart is given in Fig. 3-23.
The length of time ta_down is determined by the detected output voltage slew rate and the
circuit parameters as well.
Fig. 3-22 and Fig. 3-23 can also be merged together to cover the whole operation of
Normal Steady State Mode, Transient-Up Mode, and Transient-Down Mode.
89
Fig. 3-23 Flow chart of the control algorithm during Normal Steady State Mode and Transient-Down Mode
3.3.4 Control Algorithm for Light Load Mode
The VR should enter Light Load Mode once it receives the Power State Indicator
(PSI) from the microprocessor. Upon PSI, the digital controller will shut down 3 phases
and keep one phase operating. The transient control part of the digital controller will
respond accordingly when the VR enters PSI state to avoid out of specification undershoot
voltage. Once exiting PSI, the digital controller enables all the phases and its transient
control will ensure voltage regulation even when a sudden load step-up is applied.
90
3.4 OUTPUT OVERSHOOT ANALYSIS
In practical VR design, we may often find that it is more challenging to satisfy the
voltage regulation specification upon a load release than that upon a load step-up. Thus, it
is necessary to theoretically analyze the overshoot behavior of the VR upon a load release
to help select the component values and determine the non-linear operation of the VR upon
a load release.
As has been described in Section 3.2.1.3, upon a large load release, one option of
non-linear operation is that all the low side power MOSFETs Q1-4_LS of the main phases are
turned off. The energy stored in the main phase inductors Lo and the output capacitor Co
will drive the current to flow through the body diode of the low side MOSFETs of the
main power circuit. The equivalent circuit of Transient-Down Mode at load release is
given in Fig. 3-24, in which Le is the equivalent inductance of the main phase inductors
given in (3-1). The voltage source VD represents the forward voltage drop of the body
diode of the low side MOSFETs in the multiphase interleaved buck converter. The current
source ICC represents the load current after the load release, which is also denoted as ICC_min
in the following analysis.
QLS
Le
ie(t)
Co
VD
+
vc(t)
-
ICC
Fig. 3-24 Equivalent circuit of the VR during load release (low side MOSFETs are turned off)
91
The initial current ie(0+) through the equivalent inductor Le upon load step-up is the
maximum load current ICC_max given in (3-16). The initial current it(0+) through the
transient inductor Lt is zero. The initial voltage vc(0+) across the output capacitor is the
output voltage VCC prior the load release. The load current ICC after the load release is
ICC_min, which is given in (3-18). The load current step change ICC is given in (3-19).
ie (0  )  I CC _ max
(3-16)
v c (0  )  VCC
(3-17)
I CC  I CC _ min
(3-18)
I CC  I CC _ max  I CC _ min
(3-19)
The voltage across the output capacitor Co, i.e. the output voltage vc can be derived
from the equivalent circuit given in Fig. 3-24. Its expression in differential equation format
is given in (3-20).
Le  Co   dvc (2t )
2
dt
 vc (t )  VD
(3-20)
The output voltage vc(t) can be obtained by solving the differential equation in
(3-20) and is expressed in (3-21), in which  and  are given in (3-22) and (3-23)
respectively. ICC is the load current change upon the load release.
vc (t )  VD 
VCC  VD 
2

92
I CC 2
  Co
2
2
 sin t   
(3-21)

1
Le  Co
(3-22)
 VCC  VD

   Co 
 I CC

  arctan
(3-23)
The maximum output voltage happens at time tmax after the load release, which is
given in (3-24). The maximum output voltage vc_max at tmax is given in (3-25). The
overshoot of the output voltage at load step up is therefore obtained in (3-26).

t max
vc _ max  VD 
 2

(3-24)

VCC  VD 
2
Vcc _ max  Vc _ max  VCC  VCC  VD  

I CC 2
(3-25)
 2  Co 2
VCC  VD 2 
I CC
2
 2  Co 2
(3-26)
The output voltage vc(t) minus its initial value VCC as a function of time for various
phase inductor Lo is plotted in Fig. 3-25. The maximum overshoot occurs at time tmax,
which is approximately 4µs for the given circuit parameters, as shown in Fig. 3-25.
The current through the output capacitor during load step-up is given in (3-27). The
peak current through the output capacitor is given in (3-28).
ic (t )   2  Co 2  VCC  VD 2  I CC 2  cost   
(3-27)
ic _ max (t )   2  Co 2  VCC  VD 2  I CC 2
(3-28)
93
80
72
Vc(t)-VCC (mV)
64
56
48
40
32
24
16
8
0
0
6
110
6
210
6
310
410
6
6
510
6
610
6
710
6
810
6
910
5
110
t (second)
Fig. 3-25 Output voltage overshoot as a function of time for various phase inductors when low side
MOSFETs are tuned off upon a load release (Co=6×560µF+18×22µF, ICC=100A, VCC=0.9Vdc)
The current through the equivalent inductor Le is given in (3-29).
iLe (t )  I CC   2  Co 2  VCC  VD 2  I CC 2  cost   
(3-29)
The current through the body diode of the low side MOSFET in each phase of the
VR is given in (3-30) and plotted in Fig. 3-26, which is also the current through the phase
inductor upon the load release.
i D (t )  i Lo (t ) 
1
N
  I CC   2  Co 2  VCC  VD 2  I CC 2  cost   


94
(3-30)
25
Lo=200nH
Lo=250nH
Lo=300nH
Lo=350nH
Lo=400nH
iD(t) (A)
20
15
10
5
0
0
110
6
6
210
310
6
410
6
510
6
t (second)
Fig. 3-26 Current through the body diode of the low side MOSFET as a function of time for various phase
inductance Lo upon load release (Co=6×560µF+18×22µF, ICC=100A, VCC=0.9Vdc)
Upon a large load release, another option of non-linear operation described in
Section 3.2.1.3 is that all the low side power MOSFETs Q1-4_LS of the main phases are
turned on. The equivalent circuit of this operation is given in Fig. 3-27, in which the on
resistance of the low side MOSFETs is ignored. The maximum of the overshoot voltage of
this operation is given in (3-26). The overshoot curves as a function of time for various
inductors are plotted in Fig. 3-28. Compared to the curves plotted in Fig. 3-25, the
overshoot is larger due to the conducting of the low side MOSFETs upon load release.
QLS
Le
ie(t)
Co
+
vc(t)
-
ICC
Fig. 3-27 Equivalent circuit of the VR during load release (low side MOSFETs are turned on)
95
Vcc _ max  VCC  VCC 2 
I CC 2
(3-31)
 2  Co 2
140
120
Vc(t)-VCC (mV)
100
80
60
40
20
0
0
6
110
6
210
6
310
410
6
510
6
610
6
710
6
6
810
6
910
5
110
t (second)
Fig. 3-28 Output voltage overshoot as a function of time for various phase inductors when low side
MOSFETs are turned on upon a load release (Co=6×560µF+18×22µF, ICC=100A, VCC=0.9Vdc)
The simulated output voltage overshoot upon a load release for the above two
operation options are given in Fig. 3-29 and Fig. 3-30 respectively, which verifies that
turning the low side MOSFETs off during load release can further reduce the overshoot
voltage. The further reduced overshoot voltage will then be given more room to reduce
output capacitors so as to lower the cost of the VR. However, the cost of further
suppressed overshoot voltage is extra power losses on the body diodes of the low side
MOSFETs. The power loss analysis in Section 3.5 will address this point again. Thus
compromise among voltage regulation, system cost and efficiency needs to be made while
deciding which option to choose.
96
Fig. 3-29 Output voltage upon 100A-5A load current step-down, low side FETs are turned off (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
Fig. 3-30 Output voltage upon 100A-5A load current step-down, low side FETs are turned on (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
97
3.5 POWER LOSS ANALYSIS OF LINEAR AND NON-LINEAR OPERATION
3.5.1 Power Loss Analysis under Static Load Condition
When the load current is static, the proposed non-linear operation of the VR will
not be activated. Thus the power loss analysis is based on the linear operation of switch
mode power converters. The power loss of the dominant components of the VR can be
calculated and they can be roughly categorized as conducting related losses and switching
related losses.
For given static load current ICC, the minimum current in each phase of the VR is
Iph_min and is given in (3-32). The maximum current in each phase of the VR is Iph_max and
is given in (3-33). The root mean square current (RMS) through the high side MOSFET in
each phase of the VR is given in (3-34). The root mean square current (RMS) through the
low side MOSFET in each phase of the VR is given in (3-35).
I ph _ min 
I CC Vin  VCC   D  Ts

N
2  Lo
(3-32)
I ph _ max 
I CC Vin  VCC   D  Ts

N
2  Lo
(3-33)
I rms _ HS
Vin  VCC   D  T 2 

2



I
D
T
ph
s
s 
_
min

Lo


 
  f sw
2
 1   Vin  VCC    D  T 3

s

 3 

Lo




(3-34)
I rms _ LS
VCC
1
2
2
 4  I ph _ min  D  Ts  L  1  D   Ts  
o


 
  f sw
2
 1  VCC   1  D   T 3

s
 3 L 

 o 


(3-35)
98
The conduction loss of the high side MOSFET per phase is given in (3-36)
Pc _ HS  I rms _ HS 2  Ron _ HS
(3-36)
The switching loss of the high side MOSFET per phase is given in (3-37)


1
 Vin  VD   I ph _ min  t r _ HS  Vin  V D   I ph _ max  t f _ HS  f sw
4
1
2
  C oss _ HS  Vin  f sw
2
Ps _ HS 
(3-37)
The gate loss of the high side MOSFET per phase is given in (3-38)
Pg _ HS Q g _ LS  f sw  V DR
(3-38)
The total power loss of the high side MOSFET per phase is given in (3-39).
PHS  Pc _ HS  Ps _ HS  Pg _ HS
(3-39)
The conduction loss of the low side MOSFET per phase is given in (3-40)
Pc _ LS  I rms _ LS 2  Ron _ LS
(3-40)
The switching loss of the low side MOSFET per phase is given in (3-41)
Ps _ LS 

1
1 C
2
 I ph _ min  I ph _ max  V f  t dead    snubber  Coss _ LS   Vin  f sw (3-41)
nLS  Ts
2  nLS



The gate loss of the low side MOSFET per phase is given in (3-42)
Pg _ HS Q g _ LS  f sw  V DR
(3-42)
The total power loss of the low side MOSFET per phase is given in (3-43).
PLS  Pc _ LS  Ps _ LS  Pg _ LS
(3-43)
The power loss of standard off-the-shelf phase inductor could be found from
manufacture’s datasheet thus will not be particularly analyzed here.
99
Fig. 3-31 gives the chart of power loss composition of high side and low side
MOSFETs. The switching related gate and output capacitance loss of the MOSFETs are
insignificant at 250kHz. Thus resonant gate drive is not necessary as has been pointed out
in Section 1.2.4. Fig. 3-32 gives the power loss distribution among power components, in
which the inductor loss is small, therefore standard off-the-shelf inductor can be used to
reduce cost. The steady state power losses of the VR are summarized in TABLE 3-1.
Conduction, 3.28
3.50
Power Loss (Watts)
3.00
Switching, 2.50
Conduction
Switching
2.50
Gate
Coss
2.00
1.50
Conduction, 1.14
1.00
Switching, 0.38
0.50
Gate, 0.08
Gate, 0.08
Coss, 0.01
Coss, 0.07
0.00
MAIN_HS_FET
MAIN_LS_FET
Fig. 3-31 Power loss composition in high side and low side MOSFETs (ICC=125A)
Power Loss Distribution
MAIN_INDUCTOR
10%
MAIN_HS_FET
30%
MAIN_LS_FET
60%
MAIN_HS_FET
MAIN_LS_FET
MAIN_INDUCTOR
Fig. 3-32 Total power loss distribution among power components (ICC=125A)
100
Load Condition
Current Voltage Pout
0
1.200
0.00
5
1.195
5.98
10
1.190
11.90
15
1.185
17.78
20
1.180
23.60
25
1.175
29.38
30
1.170
35.10
35
1.165
40.78
40
1.160
46.40
45
1.155
51.98
50
1.150
57.50
55
1.145
62.98
60
1.140
68.40
65
1.135
73.78
70
1.130
79.10
75
1.125
84.38
80
1.120
89.60
85
1.115
94.78
90
1.110
99.90
95
1.105 104.98
100
1.100 110.00
105
1.095 114.98
110
1.090 119.90
115
1.085 124.78
120
1.080 129.60
125
1.075 134.38
130
1.070 139.10
High Side MOSFET Power Losses
Low Side MOSFET Power Losses
Inductor Power Losses
Total Power Losses and Efficiency
Duty Pcond_HS Psw_HS Pdrive_HS Pout_HS Ploss_total_HS Pcond_LS Psw_LS Pdrive_LS Pout_LS Ploss_total_LS Pcopper_Lout Pcore_Lout Ploss_total_Lout P_loss_phase P_loss
Efficiency
10.00%
0.01
0.23
0.08
0.01
0.02
0.04
0.08
0.07
0.01
0.07
0.83
3.34
0.33
0.21
0.08
0.0%
9.96%
0.01
0.28
0.08
0.01
0.04
0.04
0.08
0.07
0.02
0.10
0.96
3.85
0.38
0.23
0.12
60.8%
9.92%
0.02
0.33
0.08
0.01
0.05
0.05
0.08
0.07
0.02
0.15
1.11
4.42
0.44
0.25
0.17
72.9%
9.88%
0.03
0.37
0.08
0.01
0.07
0.06
0.08
0.07
0.03
0.19
1.26
5.05
0.49
0.27
0.23
77.9%
9.83%
0.03
0.42
0.08
0.01
0.09
0.06
0.08
0.07
0.04
0.25
1.44
5.74
0.54
0.30
0.29
80.4%
9.79%
0.04
0.48
0.08
0.01
0.11
0.07
0.08
0.07
0.05
0.29
1.63
6.52
0.61
0.34
0.34
81.8%
9.75%
0.06
0.58
0.08
0.01
0.15
0.09
0.08
0.07
0.07
0.29
1.87
7.47
0.73
0.39
0.36
82.4%
9.71%
0.08
0.67
0.08
0.01
0.20
0.10
0.08
0.07
0.09
0.29
2.13
8.52
0.84
0.46
0.38
82.7%
9.67%
0.10
0.77
0.08
0.01
0.26
0.12
0.08
0.07
0.11
0.29
2.41
9.66
0.96
0.53
0.40
82.8%
9.63%
0.12
0.86
0.08
0.01
0.33
0.13
0.08
0.07
0.14
0.28
2.72
10.90
1.08
0.61
0.42
82.7%
9.58%
0.15
0.96
0.08
0.01
0.41
0.15
0.08
0.07
0.17
0.28
3.06
12.24
1.20
0.70
0.45
82.5%
9.54%
0.19
1.06
0.08
0.01
0.49
0.16
0.08
0.07
0.20
0.28
3.42
13.69
1.33
0.81
0.48
82.1%
0.24
0.28
3.81
15.25
9.50%
0.22
1.15
0.08
0.01
0.59
0.18
0.08
0.07
0.92
0.51
81.8%
1.46
9.46%
0.26
1.25
0.08
0.01
0.70
0.19
0.08
0.07
0.28
0.28
4.23
16.93
1.60
1.04
0.55
81.3%
9.42%
0.30
1.34
0.08
0.01
0.82
0.21
0.08
0.07
0.32
0.27
4.68
18.72
1.74
1.18
0.59
80.9%
9.38%
0.35
1.44
0.08
0.01
0.95
0.22
0.08
0.07
0.36
0.27
5.16
20.64
1.88
1.32
0.63
80.3%
9.33%
0.40
1.54
0.08
0.01
1.10
0.24
0.08
0.07
0.41
0.27
5.67
22.67
2.03
1.48
0.68
79.8%
9.29%
0.46
1.63
0.08
0.01
1.25
0.25
0.08
0.07
0.46
0.27
6.21
24.84
2.18
1.65
0.73
79.2%
9.25%
0.51
1.73
0.08
0.01
1.42
0.26
0.08
0.07
0.52
0.26
6.78
27.14
2.33
1.84
0.78
78.6%
9.21%
0.58
1.82
0.08
0.01
1.60
0.28
0.08
0.07
0.57
0.26
7.39
29.57
2.49
2.03
0.84
78.0%
9.17%
0.65
1.92
0.08
0.01
1.80
0.29
0.08
0.07
0.64
0.26
8.03
32.14
2.66
2.24
0.89
77.4%
9.13%
0.72
2.02
0.08
0.01
2.01
0.31
0.08
0.07
0.70
0.26
8.71
34.85
2.82
2.47
0.96
76.7%
9.08%
0.79
2.11
0.08
0.01
2.23
0.32
0.08
0.07
0.77
0.25
9.43
37.70
3.00
2.70
1.02
76.1%
9.04%
0.87
2.21
0.08
0.01
2.47
0.34
0.08
0.07
0.84
0.25
10.18
40.71
3.17
2.96
1.09
75.4%
9.00%
0.96
2.30
0.08
0.01
2.72
0.35
0.08
0.07
0.91
0.25
10.97
43.86
3.35
3.23
1.16
74.7%
8.96%
1.05
2.40
0.08
0.01
2.99
0.37
0.08
0.07
0.99
0.25
11.79
47.17
3.54
3.51
1.23
74.0%
8.92%
1.14
2.50
0.08
0.01
3.28
0.38
0.08
0.07
1.07
0.25
12.66
50.64
3.73
3.81
1.31
73.3%
TABLE 3-1 Summary of calculated power loss under steady state load condition
101
3.5.2 Power Loss Analysis under High Frequency Dynamic Load Condition
The VR is subject to dynamic load changes. According to Intel and AMD’s VR
specifications, the CPU current may change repeatedly at a frequency up to 1MHz [3, 42].
It is therefore necessary to analyze the power losses of the VR under such high frequency
dynamic load conditions, particularly with the proposed non-linear operation.
The extra power losses brought by load oscillation and non-linear operation will
increase as the load frequency increases, till a frequency defined as critical load oscillation
frequency is reached. This critical load frequency fc_load is given in (3-44).
f c _ load 
N  VCC  V D 
2  I CC _ max  Lo
(3-44)
When the load frequency fload is lower than the critical load frequency fc_load, the
extra power loss of the VR during load oscillation is mainly the power loss of the body
diode of the low side MOSFET. The power loss of the body diode is given in (3-45).
Pdiode 
2  I CC _ min  I CC
f load

 VD  f load  f c _ load
2  f c _ load
2 N
(3-45)
When the load frequency exceeds the critical load frequency, the power loss of
body diodes of low side MOSFETs is given in (3-46).
Pdiode 
2  I CC _ min  I CC
4 N
 VD  f load  f c _ load
(3-46)
The relationship between the power losses on the body diode of low side
MOSFETs as a function of load frequency is therefore illustrated in Fig. 3-33, in which the
critical load frequency is approximately at 150kHz, beyond which point the power loss
will no longer increase.
102
25
Power Loss (Watts)
20
15
10
5
0
0
50
100
150
200
250
300
Load Frequency (kHz)
Fig. 3-33 Power loss as a function of load frequency
However, neither Intel nor AMD gives specification on VR’s efficiency under high
frequency oscillation load conditions. It is mainly because the load oscillation up to 1MHz
is solely a test condition serving as an tentative way to model the microprocessor’s
possible extreme power consuming behavior, so as to ensure the VR have no excessive
undershoot and overshoot under no circumstance in the real world working conditions. In
reality, the power consumption change rate of a microprocessor is believed to be below
10kHz for full load step.
103
3.6 SIMULATION RESULTS
In this section, a four-phase VR is designed to verify the proposed control method.
Various simulations are carried out to examine the performance of the VR against Intel’s
VR specifications. The key design criteria and key parameters of the VR are briefly listed
in TABLE 3-2. The VR circuit is built and simulated in Matlab/Simulink environment.
TABLE 3-2 VR design specifications and parameters
Vin
Input voltage
12Vdc
VCC
Output voltage
0.85-1.4Vdc
ICC_min
Minimum load current
5A
ICC_max
Maximum load current
125A
ICC
Maximum load current step
95A
dICC/dt
Load current slew rate
2000A/µs, 95A step in 50ns
VCC_ripple
Output voltage ripple
10mV peak to peak
N
Number of phases
4
fsw
Switching frequency
250kHz
Lo
Phase inductor
320nH / 1m ESR
Co
Output capacitor
6×560µF + 18×22µF MLCC
RLL
Load line impedance
1m
3.6.1 Single Load Step Simulation Results
Various load steps are applied to the VR to examine the voltage regulation of the
VR with the proposed control method. Fig. 3-34 to Fig. 3-43 gives the simulation results
of the output voltage response to various single load steps, in which the VID voltage is set
to be 1.0Vdc. The simulation results show that the output voltage undershoots or overshoots
are all in satisfactory range.
104
Fig. 3-34 Output voltage waveform upon 30A-125A load current step-up (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
Fig. 3-35 Output voltage waveform upon 125A-30A load current step-down (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
105
Fig. 3-36 Output voltage waveform upon 5A-100A load current step-up (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
Fig. 3-37 Output voltage waveform upon 100A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
106
Fig. 3-38 Output voltage waveform upon 25A-75A load current step-up (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
Fig. 3-39 Output voltage waveform upon 75A-25A load current step-down (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
107
Fig. 3-40 Output voltage waveform upon 5A-55A load current step-up (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
Fig. 3-41 Output voltage waveform upon 55A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
108
Fig. 3-42 Output voltage waveform upon 5A-10A load current step-up (VID=1.0Vdc)
[ICC: y-axis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
Fig. 3-43 Output voltage waveform upon 10A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
109
3.6.2 Load Oscillation Simulation Results
Various high frequency oscillation load conditions are applied to the VR to
examine the voltage regulation of the VR with the proposed control method. Fig. 4-46 to
Fig. 3-53 gives the simulation results of the output voltage response to different load steps
at various oscillation frequencies all the way from 10kHz to 1MHz, in which the VID is set
at 1.0Vdc. The simulation results show that the output voltage undershoots or overshoots
are all within a satisfactory range.
Fig. 3-44 Output voltage waveform upon 5A-100A/10kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 50µs/div; VCC: y-axis 50mV/div, x-axis 50µs/div]
110
Fig. 3-45 Output voltage waveform upon 5A-55A/10kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 100µs/div; VCC: y-axis 50mV/div, x-axis 100µs/div]
Fig. 3-46 Output voltage waveform upon 5A-10A/10kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 5A/div, x-axis 50µs/div; VCC: y-axis 10mV/div, x-axis 50µs/div]
111
Fig. 3-47 Output voltage waveform upon 30A-125A/10kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 100µs/div; VCC: y-axis 50mV/div, x-axis 100µs/div]
Fig. 3-48 Output voltage waveform upon 30A-125A/50kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 50µs/div; VCC: y-axis 20mV/div, x-axis 50µs/div]
112
Fig. 3-49 Output voltage waveform upon 30A-125A/100kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 50µs/div; VCC: y-axis 20mV/div, x-axis 50µs/div]
Fig. 3-50 Output voltage waveform upon 30A-125A/250kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div]
113
Fig. 3-51 Output voltage waveform upon 30A-125A/500kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div]
Fig. 3-52 Output voltage waveform upon 30A-125A/800kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 2µs/div; VCC: y-axis 20mV/div, x-axis 2µs/div]
114
Fig. 3-53 Output voltage waveform upon 30A-125A/1MHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 20mV/div, x-axis 5µs/div]
115
3.7 EXPERIMENTAL RESULTS
Experiments were carried out of the proposed non-linear voltage mode control
method. A four-phase VR prototype was built, with the key parameters of the power
conversion circuits given in TABLE 3-2, the same as that of the simulation given in
Section 3.6. The proposed digital control was implemented by a FPGA device Altera
Stratix II
®
chip. Fig. 3-54 gives a snapshot of the prototype showing the FPGA
implemented control circuit. The testing equipments, the set up, and the measuring
methods are carried according to the specifications given in [2, 3].
FPGA
Bottom Side
Control Circuit
Fig. 3-54 Prototype board of the VR
Fig. 3-55 gives the measured output voltage VCC response at 95A load steps. The
preset load line is 1mΩ. When the load current is oscillating at 1kHz, the output voltage is
able to respond accordingly to maintain the undershoot and overshoot specification of the
VR.
Fig. 3-56 gives the measured output voltage ripple at 5A load current. The ripple is
about 8mV peak to peak. Fig. 3-57 gives the measured output voltage ripple at 100A load
116
current. The ripple is about 9mV peak to peak. For the given circuit parameters, the output
voltage ripple is smaller than 10mV, and thus within the VR design specification.
Fig. 3-55 Measured step response under 95A/1kHz load condition
[VCC: y-axis 50mV/div, x-axis 400µs/div]
Fig. 3-56 Measured output voltage ripple (8mVpp) at 5A load current
[VCC: y-axis 10mV/div, x-axis 400µs/div]
117
Fig. 3-57 Measured output voltage ripple (9mVpp) at 100A load current
[VCC: y-axis 10mV/div, x-axis 20µs/div]
Fig. 3-58 gives the measured efficiency of the VR prototype with and without light
load PSI control. With the proposed PSI control, the efficiency of the VR below 20% load
current is greatly improved compared with that without PSI control.
84
PSI Mode
82
Non-PSI Mode
80
78
Efficiency (%)
76
74
72
70
68
66
64
62
60
5
15
25
35
45
55
65
75
85
95
105
115
Load Current Icc (A)
Fig. 3-58 Measured efficiency of the prototype
118
125
3.8 SUMMARY
The proposed control method utilizes voltage mode control and thus can maximize
its bandwidth for steady state linear operation. Non-linear predictive voltage mode control
is adopted during load transients. It greatly accelerates the transient response of the voltage
regulator based on the sensed output voltage and its slope. To obtain sufficient flexibility, a
digital control approach is adopted to realize the proposed non-linear predictive control
method.
The digitally implemented non-linear predictive controller enables the VR to
operate at moderate switching frequency, hence enabling the VR to achieve high efficiency
easily. The controller also enables utilizing simple conventional multiphase buck converter
topology, which utilizes more standard components, thus lowering the cost of the power
conversion circuits. The digitally implemented controller also gives flexibility for the VR’s
light load operation. The proposed light load control algorithm can greatly improve the
VR’s efficiency at light load compared to that of the conventional method.
Simulation and experimental results show that the control method reduces the
required output capacitance and hence the number of output capacitors. It can reduce the
number of 560µF bulk capacitors from about 10 in the conventional control method to
about 6.
119
CHAPTER 4
VOLTAGE REGULATOR WITH TRANSIENT CIRCUIT AND
DIGITAL CONTROLLER
4.1 INTRODUCTION
In addition to low cost and tight voltage regulation, VRs are also subject to higher
efficiency requirement. Computer manufacturers and end users are becoming increasingly
committed to environmental protection and efficient energy utilization. To achieve desired
results, more sophisticated power management techniques are required. A digitally
controlled voltage regulator with fast transient circuit is therefore proposed in this chapter
to comply with the above requirements and trends. The proposed digital controller enables
the VR’s main power circuit to operate at a relatively low frequency around 250kHz to
minimize the switching losses for higher efficiency and to keep the power circuit including
the gate drives, simple and at same mean time to allow use of lower performance but less
expensive power MOSFETs. The proposed transient circuit is idle under normal static load
conditions, but will be activated and controlled by the digital controller to operate at much
a higher frequency up to 3-5MHz for a short period of time upon large load steps. The
proposed operation greatly enhances the VR’s transient response. Consequently, the VR
needs much less output capacitance and can potentially eliminate all the 6-10 output bulk
capacitors indispensable to conventional VR solutions. The remaining MLCC ceramic
capacitors therefore form the output filter capacitor. The advantages of MLCC capacitors
are that they have much less ESR and ESL than bulk capacitors and they are also more
reliable than bulk capacitors.
120
Since the VR is regulated by a digital controller, about 20 surface mount passive
resistors and capacitors necessary for analog controllers are removed. VR costs are
lowered due to savings in terms of passive components and the capability of utilizing
standardized magnetic components. With this digital controller, advanced power
management functionality such as light load operation upon Power Sate Indicator (PSI)
[42] required by Intel can be easily achieved. With the proposed digital controller, the
measured efficiency of the VR can be as high as 85% at light load.
Moreover, current active components such as semiconductor power MOSFETs
usually demonstrate longer Mean Time between Failure (MTBF) than passive components
such as bulk capacitors which are used in large numbers in today’s VRs. Those passive
bulk capacitors usually contain chemicals that have negative impact on environment if not
properly disposed after recycled. Also the performance of the active semiconductor
components is improving and the price of higher performance power semiconductor
switches becomes more affordable.
The philosophy behind the VR with transient circuit and digital control method
proposed in this chapter is to utilize active components to substitute for passive capacitive
components, especially bulk capacitors, so as to meet the above requirements and to
comply with technology development trends in industry. In this chapter, the proposed
transient circuit accelerated VR with a digital control method is described and analyzed.
Simulations are carried out to aid in the design and verify the performance of the VR.
Experimental results that presented verify the operation of the proposed topology and
control method.
121
4.2 TOPOLOGY OF THE VR AND TRANSIENT CIRCUIT
Fig. 4-1 gives the schematic of the proposed multiphase VR, which consists of a
main power circuit, a four-phase interleaved buck converter in this case, a Transient
Circuit, and a digital controller. The main power circuit can be a single or multiphase buck
converter depending on the rated load current. A four-phase configuration is used in this
chapter for the design. Each phase of the main power circuit consists of high side
MOSFET Q1_HS to Q4_S, low side MOSFET Q1_LS to Q4_LS, and output filter inductor Lo1 to
Lo4. The output capacitor Co is made up of MLCC capacitors only. The transient circuit
consists of two power MOSFETs Qt_HS and Qt_LS, an inductor Lt, and a transient circuit
gate drive.
Fig. 4-1 Four-phase VR and transient circuit
122
4.3 OPERATION MODES OF THE VR WITH TRANSIENT CIRCUIT
The operation of the proposed VR with Transient Circuit can be divided in to three
modes: (1) Normal Steady State Mode; (2) Transient-Up Mode; and (3) Transient-Down
Mode.
4.3.1 Normal Steady State Mode
During Normal Steady State Mode, the output voltage is regulated by the main
power circuit switching at 250kHz with voltage mode control. The gate drive of the
transient circuit is disabled in this mode, and thus the power switches of the transient
circuit Qt_HS and Qt_LS are both turned off. In other words, the Transient Circuit is idle
during Normal Steady State Mode. The waveforms of the gate signals of the main power
circuit and the transient circuit are displayed in Fig. 4-2 in the time segments t0-t2 and t3-∞.
4.3.2 Transient-Up Mode
When the load steps up at time t1, all the high side switches of the main power
circuit are turned on and all the low side switches are turned off for the duration of ta_up,
which can be calculated from (4-1). At the same time, the gate drive of the Transient
Circuit is enabled for the duration of ta_up. The transient switch Qt_HS of the Transient
Circuit is turned on and off at a frequency up to 3-5MHz, to quickly deliver the current to
the load via the transient inductor Lt. The value of the transient inductor Lt is selected to be
much smaller than that of the main circuit inductor Lo, as has been given in (4-2).
t a _ up 
Le  I CC
Le


Vin  VCC  Vin  VCC 
Lt  Lo
123
 dv (t ) 
f  CC

 dt t 0 
(4-1)
(4-2)
VCC
I CC
Fig. 4-2 Gate patterns of the VR during load step up
124
Three possible gate patterns VGS_TR_HS for the transient switch Qt_HS are shown in
Fig. 4-2. The low side transient switch Qt_LS can switch complementary to high side
transient switch Qt_HS, similar to the switching pattern of a Buck Converter. The
waveforms of the gate signals VGS1_HS-VGS4_HS, VGS1_LS-VGS4_LS of main circuit switches
QGS1_HS-QGS4_HS, QGS1_LS-QGS4_LS, and transient switch Qt_HS are given in Fig. 4-2, in the
time segment of t2-t3.
The equivalent circuit of the VR with Transient Circuit is given Fig. 4-3, in which
Le is the equivalent inductor of the multiphase VR. QHS and QLS are the equivalent switches
of the high side and low side MOSFETs of the multiphase VR. Qt_HS, Qt_LS, and Lt are the
equivalent switches and transient inductor of the Transient Circuit respectively.
Fig. 4-3 Equivalent circuit of the VR with Transient Circuit
Fig. 4-4 to Fig. 4-6 gives the equivalent circuit and current paths of the VR during
load step-up. The waveforms of the current through the transient inductor Lt during load
step-up as well as the gate control signals are shown in Fig. 4-7. In this case the transient
inductor current is continuous. Fig. 4-8 shows the waveforms when the transient inductor
current is discontinuous.
125
Qt_HS
Lt
Qt_LS
QHS
Le
QLS
Vin
Co
ICC
Fig. 4-4 Current path during Interval I in Transient-Up Mode
Qt_HS
Lt
Qt_LS
QHS
Le
QLS
Vin
Co
ICC
Fig. 4-5 Current path during Interval II in Transient-Up Mode
Qt_HS
Lt
Qt_LS
QHS
Vin
Le
QLS
Co
ICC
Fig. 4-6 Current path during Interval III in Transient-Up Mode
126
ILt
t
VGS_TR_HS
t
VGS_TR_LS
t
VTR_EN
t
VTR_PWM
t
VGS1-4_HS
t
VGS1-4_LS
t
VMAIN_EN
t1
t2
t3 ta_up
t
Fig. 4-7 Waveforms of transient circuit and main power circuit in Transient-Up Mode (CCM)
Fig. 4-8 Waveforms of transient circuit and main power circuit in Transient-Up Mode (DCM)
127
The PSpice simulation results of the output voltage in Fig. 4-9 show that given the
same small amount of output capacitance, the Transient Circuit greatly enhances the
dynamic response of the VR upon load step up. Fig. 4-10 gives the simulated output
voltage waveform of a 4-phase VR with Transient Circuit upon 95A load step-up.
1.8V
1.6V
Proposed Solution
1.4V
1.2V
1.0V
Current Solutions
0.8V
0s
50us
V(Vo)
100us
150us
200us
250us
300us
350us
400us
Time
Fig. 4-9 Improvement of transient response of a single phase VR at load step-up
140A
100A
50A
SEL>>
0A
I(Intel_VRD11_Load_Model.I_PWL)
1.24V
1.20V
1.16V
1.12V
1.08V
1.04V
146us
148us
150us
152us
V(Intel_VRD11_Load_Model:N2)
154us
156us
158us
160us
162us
Time
Fig. 4-10 Simulated output voltage at 95A load step up
128
164us
166us
4.3.3 Transient-Down Mode
At load step down, all the switches in the main power circuit are turned off. The
transient circuit power switch Qt_LS is turned on and off during this period of time to clamp
the output voltage via the transient inductor Lt. The transient switch Qt_HS is switching
complementary to Qt_LS, similar to the way in which a Boost Converter operates. Part of
the energy stored in the output capacitors and inductors is therefore regenerated back to the
input voltage source through the transient circuit. The duration ta_down for transient-down
operation is given in (4-3).
t a _ down 
 dv (t ) 
Le  I CC
L
 e  f  CC

VCC
VCC  dt t 0 
(4-3)
The waveforms of the current through the transient inductor Lt and related gate
control signals during load step-down are also given in Fig. 4-11.
ILt
t
VGS_TR_LS
t
VGS_TR_HS
t
VTR_EN
t
VTR_PWM
t
VGS1-4_HS
t
VGS1-4_LS
t
VMAIN_EN
ta_down
Fig. 4-11 Current waveform of transient inductor Lt during Transient-Down Mode
129
Qt_HS
Qt_HS
Lt
Qt_LS
QHS
Vin
Lt
Qt_LS
QHS
Le
QLS
Co
ICC
Vin
(a) Low side MOSFET is turned off
Le
QLS
Co
(b) Low side MOSFET is turned on
Fig. 4-12 Current path during of Interval I in Transient-Down Mode
Qt_HS
Lt
Qt_LS
QHS
Vin
Le
QLS
Co
ICC
(a) Low side MOSFET is off
(b) Low side MOSFET is on
Fig. 4-13 Current path during Interval II in Transient-Down Mode
(b) Low side MOSFET is turned on
(a) Low side MOSFET is turned off
Fig. 4-14 Current path during Interval III in Transient-Down Mode
130
ICC
Fig. 4-12 to Fig. 4-14 gives the equivalent circuits and current paths of the VR
during load step-down. In Interval I the output voltage is clamped by the transient inductor
Lt and power MOSFET Qt_LS, as well as the operation of the main power circuit. In Interval
II and Interval III, the energy stored in Lt is regenerated back to the power source Vin via
Qt_HS. The low side MOSFETs of the main power circuit can remain on or off during this
mode. However, the output overshoot voltage will be different in these two cases.
Fig. 4-15 gives the simulated output voltage response at 95A load release. The
voltage is clamped by Qt_LS of the transient circuit after several transient switching cycles.
We may notice that the output voltage waveforms at load step-up and step-down given in
Fig. 4-10 and Fig. 4-15 are different from the waveforms of conventional VR’s. This
difference is due to the non-linear operation of the VR during load transients. However, the
difference in waveform shapes does not affect the VR’s transient performance as long as
the output voltage is within the limits of the VR specification.
140A
100A
50A
SEL>>
0A
I(Intel_VRD11_Load_Model.I_PWL)
1.24V
1.20V
1.16V
1.12V
1.08V
1.04V
446us
448us
450us
452us
V(Intel_VRD11_Load_Model:N2)
454us
456us
458us
460us
462us
Time
Fig. 4-15 Simulated output voltage at 95A load step-down
131
464us
466us
4.4 DIGITAL IMPLEMENTATION OF THE CONTROLLER
4.4.1 Architecture of the Digital Controller
In order to implement the operation of the proposed multiphase VR with transient
circuit described in Section 4.3, a digital controller is proposed. Fig. 4-16 gives the brief
block diagram of the proposed digital controller. The controller has two major
functionalities. One is to digitally regulate the output voltage by regulating the multiphase
main power circuit during normal steady state operation. Another functionality of the
controller is to control the gates of the main power circuit and the transient circuit so as to
enable the VR to respond quickly to maintain the output voltage during load transients.
Fig. 4-16 Brief block diagram of the digital controller with Transient Circuit control
The sensed output voltage is first digitized by the Analog to Digital Converter
(ADC) in the digital controller. In a steady state, the sensed output voltage is compared to
132
the reference voltage to generate an error signal, which is then digitally compensated to
generate the digital PWM gate signals of the multiphase main power circuit. The digital
controller also detects the slope of the output voltage to determine the transient operation
of the main power circuit and the transient circuit.
HIGH-PRECISION
REFERENCE
SCL
I2C Bus
SDA
NON-VOLATILE
MEMORY
RESET
OTHER CHIP
MANAGEMENT
OUTEN
LL1
LL0
PWR
VRPRES
PWRGD
LOAD
LINE
LOAD
INDICATOR
LDICATOR
VID7
OSCILLATOR
SOFT
START
VID6
VID5
VID4
VID [7:0]
VID3
DECODER
DIGITAL
REFERENCE
CONTROL
DIGITAL
PID
PH1
EN1
VID2
DAC
PH2
VID1
VID0
VSENSE
ADC
DA
VCC_SENSE
DYNAMIC
CONTROL
EN2
DIGITAL
PH3
PWM
VSS_SENSE
GENERATOR
VIN
LOW
VINSENSE
EN3
PH4
ISENP4
ISENN4
EN4
ISENP3
ISENN3
ISENP2
ISENN2
MUX
ISENSE
ADC
ICC/VIN/TEMP
DECODER
PHASE
CURRENT
BALANCE
TRAN
TRAN_EN
ISENP1
ISENN1
TEMPSENSE
TEMPERATURE
VRHOT
GND
Fig. 4-17 Architecture of the digital controller with Transient Circuit control
133
4.4.2 Control Algorithm for Transient Modes
Fig. 4-18 gives a brief flow chart of the control algorithm of the proposed digital
controller during load step-up.
Fig. 4-18 Flow chart of the control algorithm
134
4.5 OUTPUT OVERSHOOT ANALYSIS
Upon a large load release, all the power MOSFETs Q1-4_LS of the main phases will
be turned off. The energy stored in the main phase inductors Lo and the output capacitor Co
will drive the current to flow through the body diode of the low side MOSFETs of the
main power circuit. At the same time, the low side MOSFET Qt_LS of the transient circuit is
turned on to help clamp the output voltage by shunting the current through the transient
inductor Lt.
The equivalent circuit of Transient-Down Mode at load release is given in Fig.
4-19, in which Le is the equivalent inductance of the main phase inductors given in (4-4). Lt
is the inductance of the transient circuit inductor. The voltage source VD represents the
forward voltage drop of the body diode of the low side MOSFETs in the multiphase
interleaved buck converter. The current source ICC represents the load current after the load
release.
Le
Lt
ie(t)
VD
Co
+
vc(t)
-
it(t)
ICC
Fig. 4-19 Equivalent circuit of the VR during load release
The initial current ie(0+) through the equivalent inductor Le upon load step-up is the
maximum load current ICC_max given in (4-5). The initial current it(0+) through the transient
inductor Lt is zero. The initial voltage vc(0+) across the output capacitor is the output
135
voltage VCC prior the load release. The load current ICC after the load release is ICC_min,
which is given in (4-8). The load current step change ICC is given in (4-9).
Le 
Lo
N
(4-4)
ie (0  )  I CC _ max
(4-5)
i t (0  )  0
(4-6)
v c (0  )  VCC
(4-7)
I CC  I CC _ min
(4-8)
I CC  I CC _ max  I CC _ min
(4-9)
The voltage across the output capacitor Co, i.e. the output voltage vc, can be derived
from the equivalent circuit given in Fig. 4-19, and is given in differential equation format
in (4-10), in which Leq and Ve are given in (4-11) and (4-12) respectively. VCC is the steady
state output voltage prior the load release.
Leq  Co  dvc (2t )
dt
Leq 
2
 vc (t )  VCC  Ve
Lt  Le
Lt  Le


Lt
Ve  VCC 
 V D 
Le  Lt


136
(4-10)
(4-11)
(4-12)
The output voltage vc(t) can be obtained by solving the differential equation in
(4-10) and is expressed in (4-13), in which  and  are given in (4-14) and (4-15)
respectively. ICC is the load current change at the load release.
vc (t )  VCC  Ve   Ve 
I CC
2
2
 2  Co 2
 sin t   
1

(4-13)
(4-14)
Leq  C o
 Ve

   C o 
 I CC

  arctan
(4-15)
The maximum output voltage happens at time tmax after the load release, which is
given in (4-16). The maximum output voltage vc_max at tmax is given in (4-17). The
overshoot of the output voltage at load step up is therefore obtained in (4-18).

t max
 2

(4-16)

v c _ max  VCC  Ve   Ve 
2
I CC
2
 2  Co 2
2
Vcc _ max  Vc _ max  VCC  Ve  Ve 
I CC 2
 2  Co 2
(4-17)
(4-18)
The output voltage vc(t) minus its initial value VCC as a function of transient
inductor value is plotted in Fig. 4-20. The maximum overshoots happen at time tmax as
shown in Fig. 4-20.
137
250
tmax
225
200
Vc(t)-VCC (mV)
175
150
Lt=40nH
125
Lt=25nH
100
Lt=20nH
75
Lt=30nH
Lt=15nH
50
Lt=10nH
Lt=35nH
25
0
0
510
7
110
6
1.510
6
210
6
6
2.510
310
6
6
3.510
410
6
t (s econd)
Fig. 4-20 Output voltage minus its initial value as a function of Transient Circuit inductance Lt at load
release (Lo=320nH, Co=528µF, ICC=100A, VCC=0.9Vdc)
The current through the transient inductor Lt during load release is given in (4-19).
Fig. 4-21 gives the current as a function of time for various values of Lt.
Ve 2 
i Lt (t ) 
I CC 2
 2  Co 2
Lt
 VD  t
Le  Lt
 cos   cost    
  Lt
(4-19)
300
Lt=10nH
Lt=15nH
Lt=20nH
Lt=30nH
250
iLt (t) (A)
200
150
100
50
0
0
7
510
6
110
6
1.510
6
210
6
2.510
6
310
6
3.510
6
410
Time (Seconds)
Fig. 4-21 Current through transient inductor Lt at load release for various inductance values (Lo=320nH,
Co=528µF, ICC=100A, VCC=0.9Vdc)
138
The current through the output capacitor during load release is given in (4-20), and
plotted for various transient inductor values in Fig. 4-22.
iCo (t )   2  Co 2  Ve 2  I CC 2  cost   
(4-20)
200
Lt=10nH
Lt=15nH
Lt=20nH
Lt=30nH
iCo (t) (A)
100
0
 100
 200
 300
0
7
510
6
110
6
1.510
6
210
6
2.510
6
310
6
3.510
6
410
Time (Seconds)
Fig. 4-22 Current through output capacitor Co at load release for various Lt values (Lo=320nH, Co=528µF,
ICC=100A, VCC=0.9Vdc)
The current through the body diode of low side MOSFET in each phase of the main
power circuit during load release is given in (4-21).
iD (t ) 
Le
VD  t  I CC _ max
Le  Lt


I CC 2
 Ve 2 



 2  Co 2

 cost     cos 







(4-21)
The output voltage maximum overshoot is plotted in Fig. 4-24 as a function of the
output capacitance Co, the main phase inductance Lo, and the transient circuit inductance
Lt, to help select component values of the main and transient circuit. The curves are plotted
under the worst case scenario when the load release step ICC is the maximum at 100A,
139
from 105A to 5A for instance. From the plot we can notice that when the output voltage
VCC is the minimum at 0.9Vdc, the maximum overshoot is the largest, higher than that when
Vcc=1.4Vdc for instance. Therefore the minimum steady state output voltage will be used
for the worst case design.
28
26
iD(t) (A)
24
22
Lt=10nH
Lt=15nH
Lt=20nH
Lt=30nH
20
18
0
7
6
510
110
6
1.510
6
210
6
2.510
6
310
6
3.510
6
410
Time (Seconds)
Fig. 4-23 Current through the body diode of low side MOSFET in each phase of the main power circuit at
load release for various Lt values (Lo=320nH, Co=528µF, ICC=100A, VCC=0.9Vdc)
400
Lo =560nH
Co =500uF
V o =0.9V
Lo =300nH
Co =500uF
Vo =0.9V
Lo =560nH
Co =500uF
V o =1.4V
Lo =300nH
Co =500uF
Vo =1.4V
Output Voltage Overshoot (mV)
350
300
Lo =560nH
Co =1000uF
Vo =0.9V
Lo =300nH
Co =1000uF
Vo =0.9V
Lo =560nH
Co =1000uF
Vo =1.4V
Lo =300nH
Co =1000uF
Vo =1.4V
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
90
100
Transient Inductor Lt (nH)
Fig. 4-24 Output voltage maximum overshoot at load step-down (ICC=100A)
140
4.6 POWER LOSS ANALYSIS
The Transient Circuit of the VR is in idle mode under static load current condition,
thus the power loss analysis of the VR is the same as that given in Section 3.5.1. During
load transients, the Transient Circuit will be activated and the main power circuit will
work differently. The power losses of the VR are briefly given below.
The critical load oscillation frequency fc_load is given in (4-22).
f c _ load 
N  VCC  V D 
2  I CC _ max  Lo
(4-22)
The conduction loss of Transient Circuit high side MOSFET is given in (4-23), the
switching loss is given in (4-24), and the gate loss is given in (4-25). The total power loss
of Transient Circuit high side MOSFET is given in (4-26).
Pc _ tran _ HS  I rms _ tran _ HS 2  Ron _ tran _ HS  VD  I avg _ tran _ HS _ diode
Ps _ tran _ HS
1
  Vin  VD  
3
 VD 
(4-23)
N tran _ up _ pulse
 I max_ up _ tran _ HS _ n  t f _ tran _ HS  f load
(4-24)
1
N tran _ down _ pulse
 I max_ down _ tran _ HS _ n  t dead _ tran  f load
1
1
  Vin  VCC  
3
N tran _ down _ pulse
 I max_ down _ tran _ HS _ n  t f _ tran _ HS  f load
1
Pg _ tran _ HS  Qg _ TOT _ tran _ HS  f load  (VDR  VD )  N tran _ up _ pulse
(4-25)
PTOT _ tran _ HS  Pc _ tran _ HS  Ps _ tran _ HS  Pg _ tran _ HS
(4-26)
141
The conduction loss of Transient Circuit low side MOSFET is given in (4-27), the
switching loss is given in (4-28), and the gate loss is given in (4-29). The total power loss
of Transient Circuit low side MOSFET is given in (4-30).
Pc _ tran _ LS  I rms _ tran _ LS 2  Ron _ tran _ LS
Ps _ tran _ LS  VD 
(4-27)
N tran _ up _ pulse
 I max_ up _ tran _ LS _ n  t dead _ tran  f load
(4-28)
1
1
  VD 
3
N tran _ up _ pulse
 I min_ up _ tran _ LS _ n  t dead _ tran  f load
1
1
 Vin  VD  
3
N tran _ down _ pulse
 I max_ down _ tran _ LS _ n  t f _ tran _ LS  f load
1
Pg _ tran _ LS  Qg _ TOT _ tran _ LS  f load VDR  N tran _ down _ pulse
(4-29)
PTOT _ tran _ LS  Pc _ tran _ LS  Ps _ tran _ LS  Pg _ tran _ LS
(4-30)
The copper loss of Transient Circuit inductor is given in (4-31).
Pc _ tran _ Lt  I rms _ tran _ Lt 2  rLt
(4-31)
The power loss of low side MOSFETs of main power circuit is given in (4-32).
Pc _ main _ LS  I avg _ main _ LS  VD
(4-32)
The power regenerated back to the input source during load step-down via the
Transient Circuit is given in (4-32).
Preg _ tran _ HS  I reg _ avg _ tran _ HS  Vin
(4-33)
Fig. 4-25 gives the chart of power loss composition in each high side and low side
MOSFET of Transient Circuit during load oscillation.
142
Gate
1.80
Gate, 0.03
Conduction
Power Loss (Watts)
1.60
Switching
1.40
1.20
1.00
0.80
Conduction, 1.46
Gate, 0.03
Conduction, 0.30
0.60
0.40
0.20
Switching, 0.51
Switching, 0.18
0.00
TRAN_HS_FET
TRAN_LS_FET
Fig. 4-25 Power loss composition in each high side and low side MOSFETs of Transient Circuit during load
oscillation at 5A-100A/40kHz
Fig. 4-26 gives chart of power loss distribution among power components in the
main power circuit and Transient Circuit. Among those power losses, 37% is regenerated
back to the input power source.
Power Loss Distribution
TRAN_HS_FET
4%
REGENERATED
37%
TRAN_LS_FET
17%
TRAN_INDUCTOR
10%
MAIN_LS_DIODE
40%
TRAN_HS_FET
TRAN_LS_FET
TRAN_INDUCTOR
MAIN_LS_DIODE
REGENERATED
Fig. 4-26 Power loss distribution among power components during load oscillation at 5A-100A/40kHz
143
Fig. 4-27 gives the experimental measured increased power loss of the VR as a
function of load frequency.
30
28
26
24
Increased Power Loss (W)
22
20
18
16
14
12
10
8
6
4
2
0
0
50
100 150 200 250 300 350 400 450 500 550 600 650 700 750 800
Load Oscillation Frequency (kHz)
Fig. 4-27 Measured power loss as a function of load frequency (ICC=95A)
144
4.7 SIMULATION RESULTS
To verify the performance of the proposed VR and its control method, simulations
utilizing Matlab/Simulink were carried out. The design specifications and the VR
parameters are given in TABLE 4-1
TABLE 4-1 Design specifications and parameters of proposed VR with Transient Circuit
Vin
Input voltage
12Vdc
VCC
Output voltage
0.8-1.5Vdc
ICC
Load current
125A
ICC
Maximum load current step
95A
dICC/dt
Load current slew rate
2000A/µs, 95A step in 50ns
VCC_ripple
Output voltage ripple
10mV peak to peak
N
Number of phases
4
fsw
Switching frequency
250kHz
Lo
Phase inductor
320nH / 1m ESR
Co
Output capacitor
24×22µF MLCC
RLL
Load line impedance
1m
4.7.1 Single Load Step Simulation Results
Various load steps are applied to the VR to examine the voltage regulation of the
VR with the proposed control method. Fig. 4-28 to Fig. 4-37 gives the simulation results
of the output voltage response to various single load steps, in which the VID is set to be
1.0Vdc. The simulation results show that the output voltage undershoots or overshoots are
all in satisfactory range.
Various simulations of load step-up and step-down are carried out for compliance
test. The load step conditions and the quantitative results are summarized in TABLE 4-3.
145
Fig. 4-28 Output voltage waveform upon 30A-125A load current step-up (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
Fig. 4-29 Output voltage waveform upon 125A-30A load current step-down (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
146
Fig. 4-30 Output voltage waveform upon 5A-100A load current step-up (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
Fig. 4-31 Output voltage waveform upon 100A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
147
Fig. 4-32 Output voltage waveform upon 25A-75A load current step-up (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 5µs/div; VCC: y-axis 10mV/div, x-axis 5µs/div]
Fig. 4-33 Output voltage waveform upon 75A-25A load current step-down (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
148
Fig. 4-34 Output voltage waveform upon 5A-55A load current step-up (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
Fig. 4-35 Output voltage waveform upon 55A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 10A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
149
Fig. 4-36 Output voltage waveform upon 5A-10A load current step-up (VID=1.0Vdc)
[ICC: y-axis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
Fig. 4-37 Output voltage waveform upon 10A-5A load current step-down (VID=1.0Vdc)
[ICC: y-axis 5A/div, x-axis 10µs/div; VCC: y-axis 10mV/div, x-axis 10µs/div]
150
TABLE 4-2 Summary of single step load line compliance simulation results
SINGLE STEP LOAD LINE SIMULATIONS
VR Configuration Test Purpose Start Current
(Amps)
Load Step Test
775_VR_CONFIG_06
Overshoot Test
Load Step Test
775_VR_CONFIG_05A
Overshoot Test
Load Step Test
775_VR_CONFIG_05B
Overshoot Test
Light Load Tests
775_VR_CONFIG_XXX
Half Load Test
Complementary
Tests
End Current
(Amps)
Step
(Amps)
Undershoot
(mV)
Overshoot
(mV)
Settling Time Voltage
Time
(µs)
Deviation deviation
Specification
10
50
100 or 25µs
25
75
50
7
-
10
Pass
Pass
75
25
-50
-
8
8
Pass
Pass
5
55
50
8
-
10
Pass
Pass
55
5
-50
-
30
10
Pass
Pass
20
85
65
5
-
8
Pass
Pass
85
20
-65
-
17
7
Pass
Pass
5
70
65
6
-
7
Pass
Pass
70
5
-65
-
40
14
Pass
Pass
30
125
95
6
-
2
Pass
Pass
125
30
-95
-
18
10
Pass
Pass
5
100
95
6
-
2
Pass
Pass
100
5
-95
-
42
10
Pass
Pass
5
10
5
7
-
0
Pass
Pass
10
5
-5
-
12
5
Pass
Pass
5
20
15
8
-
0
Pass
Pass
20
5
-15
-
12
5
Pass
Pass
5
35
30
5
-
8
Pass
Pass
35
5
-30
-
28
7
Pass
Pass
15
65
50
5
-
10
Pass
Pass
65
15
-50
-
23
6
Pass
Pass
45
75
30
6
-
1
Pass
Pass
75
45
-30
-
0
2
Pass
Pass
85
125
40
5
-
5
Pass
Pass
125
85
-40
-
0
5
Pass
Pass
75
125
50
4
-
5
Pass
Pass
125
75
-50
-
13
0
Pass
Pass
4.7.2 Load Oscillation Simulation Results
Various high frequency oscillation load conditions are applied to the VR to
examine the voltage regulation of the VR with the proposed Transient Circuit and control
method. Fig. 4-38 to Fig. 4-44 gives the simulation results of the output voltage response
to different load steps at various oscillation frequencies all the way from 10kHz to 1MHz,
in which the VID voltage is set to be 1.0Vdc. The simulation results show that output
voltage undershoots or overshoots are all in satisfactory range.
Various simulations for AC load line compliance test are carried out in Matlab. The
load step conditions and the quantitative results are summarized in TABLE 4-3.
151
Fig. 4-38 Output voltage waveform upon 30A-125A/10kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div]
Fig. 4-39 Output voltage waveform upon 30A-125A/50kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 10µs/div; VCC: y-axis 50mV/div, x-axis 10µs/div]
152
Fig. 4-40 Output voltage waveform upon 30A-125A/100kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div]
Fig. 4-41 Output voltage waveform upon 30A-125A/250kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 5µs/div; VCC: y-axis 50mV/div, x-axis 5µs/div]
153
Fig. 4-42 Output voltage waveform upon 30A-125A/500kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 2µs/div; VCC: y-axis 50mV/div, x-axis 2µs/div]
Fig. 4-43 Output voltage waveform upon 30A-125A/800kHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 2µs/div; VCC: y-axis 50mV/div, x-axis 2µs/div]
154
Fig. 4-44 Output voltage waveform upon 30A-125A/1MHz load oscillation (VID=1.0Vdc)
[ICC: y-axis 20A/div, x-axis 20µs/div; VCC: y-axis 50mV/div, x-axis 20µs/div]
TABLE 4-3 Summary of AC load line compliance simulation results
AC LOAD LINE SIMULATIONS
VR Configuration Test Purpose
775_VR_CONFIG_05B
Load Step Test
Complementary
Tests
775_VR_CONFIG_XXX
(repeatable load
steps to make
sure the
response is
consistant)
Load Current
Range
Load
Frequency
(kHz)
30A - 125A
5A - 100A
Vmin
Spec
Vmax
Spec
-
Pass
Pass
-
Pass
Pass
19
-
Pass
Pass
18
-
Pass
Pass
8
12
-
Pass
Pass
12
30
-
Fail
Pass
15
40
-
Fail
Pass
Step
(Amps)
Specification
Undershoot
(mV)
10
Overshoot
(mV)
50
1
95
5
19
5
95
8
20
30A - 125A
10
95
10
5A - 100A
20
95
8
30A - 125A
30
95
5A - 100A
50
95
30A - 125A
70
95
5A - 100A
100
95
11
38
-
Fail
Pass
30A - 125A
200
95
7
32
-
Pass
Pass
5A - 100A
250
95
8
25
-
Pass
Pass
30A - 125A
400
95
9
38
-
Pass
Pass
5A - 100A
500
95
0
18
-
Pass
Pass
30A - 125A
600
95
0
20
-
Pass
Pass
5A - 100A
800
95
0
30
-
Pass
Pass
30A - 125A
1000
95
0
15
-
Pass
Pass
5A - 10A
5
5
8
9
-
Pass
Pass
5A - 20A
5
15
8
3
-
Pass
Pass
5A - 30A
5
25
5
40
-
Pass
Pass
5A - 55A
5
50
9
28
-
Pass
Pass
5A - 100A
5
95
8
41
-
Pass
Pass
15A - 65A
5
50
7
30
-
Pass
Pass
155
4.8 EXPERIMENTAL RESULTS
The snapshot of the VR’s prototype board is shown in Fig. 4-45, from which we
can see that all the bulk capacitors are removed and only MLCC capacitors are kept. The
transient circuit occupies only a very small PCB board space. The testing equipments, the
set up, and the measuring methods are carried according to the specifications given in [2,
3].
Top Side
Control Circuit
Transient
Power
Processing
12V
input
Buck
Phases
Vtt
power
Input
Filter
Caps
VTT
Tool
Fig. 4-45 Prototype of the VR with Transient Circuit
Fig. 4-46 gives the measured output voltage waveform upon 95A load step-up. The
output voltage overshoot upon 95A load step-down can be observed in the measured
output voltage waveform given in Fig. 4-47.
Fig. 4-48 shows the measured output voltage waveform at 95A/1kHz load
oscillation. The measured output voltage waveform at 95A/250kHz load oscillation is
given in Fig. 4-49.
156
Fig. 4-46 Waveforms of measured output voltage at 95A load step-up (VID=1.0Vdc)
[VCC: y-axis 50mV/div, x-axis 4µs/div]
Fig. 4-47 Waveforms of measured output voltage at 95A load steps (VID=1.0Vdc)
[VCC: y-axis 50mV/div, x-axis 4µs/div]
157
Fig. 4-48 Measured output voltage at 95A/1kHz load oscillation (VID=1.0Vdc)
[VCC: y-axis 50mV/div, x-axis 400µs/div]
Fig. 4-49 Measured output voltage at 95A/250kHz load oscillation (VID=1.0Vdc)
[VCC: y-axis 50mV/div, x-axis 4µs/div]
The calculated and measured efficiency of the VR is plotted in Fig. 4-50. If more
expensive low side MOSFETs whose on-resistance Ron is 3mΩ instead of 9mΩ are used in
the main power circuit, the efficiency can be further improved as shown in the curves in
158
Fig. 4-50. We can see from the plot that the efficiency of the VR is high, even when the
9mΩ lower performance but cheaper MOSFETs are used. This is mainly because the VR is
switching at a moderate frequency of 250kHz, which enables the VR achieve higher
efficiency easily.
100%
Calculated (Ron=9mΩ)
Measured (Ron=9mΩ)
95%
Calculated (Ron=3mΩ)
Efficiency
90%
85%
80%
75%
70%
65%
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Load Current Icc (A)
Fig. 4-50 Calculated and measured VR efficiency
Upon receiving a Power State Indicator (PSI) signal from Intel’s microprocessor,
the digital controller directs the VR to enter light load operation mode, so that the light
load efficiency can be improved. As shown in Fig. 4-50, at 10% load for instance, the
efficiency is about 85%, a significant improvement from the typical 50-60%. The
improvement thus help reduce computer power consumption, especially that of server
computers operating continually.
159
4.9 SUMMARY
The proposed digitally controlled VR with fast Transient Circuit is able to achieve
fast transient response and high efficiency from light load to full load with low cost. The
digital controller also reduces the passive component counts in power and control circuits
and enables use of standardized magnetic components to keep costs low while still being
able to achieve satisfactory overall performance.
The digital controller enables VR switching at a low frequency of around 250kHz,
thus achieving high efficiency easily and with reduced cost. The digital controller also
makes the VR’s light load operation easy to be realized. As a result, the light load
efficiency of the VR is greatly increased compared to conventional control methods.
The digital controller also provides the potential to remove all bulk capacitors and
use the remaining 18-28 MLCC capacitors only at the output required to satisfy the VR’s
ripple and voltage regulation requirements. Less reliable bulk capacitors are removed, and
the VR’s reliability is increased.
Thus the proposed digitally controlled VR is an energy efficient and
environmentally friendly practical solution to desktop and server microprocessor power
needs.
160
CHAPTER 5
CONCLUSIONS AND SUMMARY
In this thesis, requirements on powering microprocessors and challenges in
designing voltage regulator (VR) are introduced. Various existing techniques and solutions
of VR topology and control are reviewed. New techniques are proposed to improve VR’s
transient performance and to solve the practical problems currently existing in industry.
Firstly, conventional voltage mode control is adopted in combination with load line
positioning and phase current balancing control to power high frequency dynamic load.
The purpose of the proposed method is to enable VR use simple but widely adopted
conventional multiphase interleaved buck converter topology, so as to reduce the cost and
simplify the power circuit design. The bandwidth of voltage control loop and phase current
balancing loop can be independently maximized, so that the tight voltage regulation and
phase current balancing under high frequency dynamic load can be achieved. Beat
frequency oscillation effect is also minimized as a result. The control method can be
analog or digitally implemented, thus is a good candidate for server, desktop, and notebook
applications.
Secondly, a non-linear predictive voltage mode control method is proposed to
further improve the output voltage transient response of the VR and to further reduce the
number of output bulk capacitors. The purpose of the method is to enable using the
simplest multiphase buck converter as the VR’s power circuit to reduce cost and enable the
VR switch at low frequency for higher system efficiency. Upon large load steps, the
controller detects the output voltage and its slope, based on which to predict the duration
161
and action of non-linear operation of the VR, so as to accelerate the speed of energy being
delivered to the load or being restrained from the load. A digital controller with very high
speed processing capability is proposed to implement the proposed non-linear control
algorithm. The digital controller also makes other power management tasks such as light
load operation an easy task. The proposed non-linear control method and the digital
controller improves the output voltage transient response of the VR, reduces the number of
bulk capacitors, and achieves high efficiency from light load to full load, thus is a good
candidate for server and desktop applications.
Thirdly, a VR with Transient Circuit and digitally implemented non-linear control
method is proposed to further enhance VR’s transient response. This solution keeps the
power circuit conventional and simple. The VR switches at low frequency for high
efficiency at static load current. The Transient Circuit is activated to switch at high
frequency upon large load steps so that energy can be quickly delivered to the load or be
restrained from the load with certain regeneration. A digital controller with very high
processing speed is proposed to implement the proposed non-linear control algorithm for
the VR with Transient Circuit. The proposed non-linear control method and the digital
controller greatly enhance the output voltage transient response of the VR. It can
potentially remove all the bulk capacitors to increase reliability of the VR. It also achieves
high efficiency from light load to full load, thus is a good candidate for server and desktop
applications.
In general, the philosophy of the proposed solutions in the thesis is to integrate high
speed processed advanced control techniques in a controller IC to minimize the complexity
of the VR power circuit, to enable the power circuit have fast transient response while
162
switching at low frequency for high efficiency from light load to full load, to shift the low
power passive components to the controller IC, and finally to replace all the passive bulk
capacitors with active power semiconductor switches to increase system reliability.
The objectives of the thesis work listed in Section 1.3 have all been achieved. In
summary, the thesis work has the following contributions: (1) achieved fast voltage
response and current balancing for VRs under high frequency dynamic load conditions; (2)
built new model for the VR with the proposed control method; (3) solved phase current
imbalance problem under high frequency repetitive load condition existing in industry; (4)
solved VR beat frequency effect problem existing in industry; (5) used non-linear
predictive control method to further improve VR’s voltage response and to reduce the
number of bulk capacitors; (6) greatly enhanced VR’s transient response with the proposed
Transient Circuit and its non-linear control method; (7) provided solution to remove all the
bulk capacitors to increase VR’s reliability; (8) reduced the cost of the VR; (9) proposed
digital controllers with fast processing speed to achieve the proposed control methods; (10)
achieved the goal of building energy efficient VRs from light load to full load.
Future work can be carried out in two major areas: (1) apply the presented control
techniques in the thesis to different power conversion topologies for different applications;
(2) optimize the controller IC in terms of control algorithm, architecture, and physical
implementation.
163
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