Download Section J7: FET Amplifier Design

Section J7: FET Amplifier Design
The expressions for amplifier characteristics developed in the previous
section will now be used in the design process. Remember that for design, it
is fundamentally important to understand what it is that you are designing
by defining the operational conditions, any constraints (physical or
operational) that may exist, what is known and what is unknown. Only after
a complete understanding has been achieved can the design process be
implemented effectively – say it with me now, don’t just grab equations!
The CS and SR Amplifier
The circuit for a SR amplifier using an
n-channel JFET is given in Figure 6.40a
and is reproduced to the right
Note that your text describes this
amplifier circuit as a common source
configuration. The only difference
between the SR and CS is the addition
of a bypass capacitor (CS) across RS. As
you go through your text, don’t let this
confuse you – when your author refers
to this configuration as common
source, he is implying common
source with source resistance.
The following discussion on the design procedure of an SR amplifier holds for
JFET and MOSFET devices. It is assumed that a device has been selected
and that its characteristics are known. Also assumed is that sufficient
information as to the supply voltage(s), load resistance, voltage gain,
current gain, and/or input resistances are provided and that the gain
requirements are within the range of the transistor being used. This is the
same thing we did in our study of BJT amplifier design – and just like then, it
is our job as designers to determine the remaining circuit components to
satisfy specifications.
As we did for BJT design, the first step is to define a Q-point. For
convenience, the Thevenin equivalent voltage and resistance and the Qpoint relationships developed in Section J4 are repeated here (remember
that the assumption |λvDS|<<1 in the derivation of these equations):
RG = R1 || R2 =
VGG =
I DQ = K (VGSQ − VT ) (1 + λV DSQ ) ≅ K (VGSQ
2
I DQ
⎛ VGSQ
= I DSS ⎜⎜1 −
VP
⎝
R1 R2
R1 + R2
V DD R1
R1 + R2
⎛ VGSQ
− VT ) = KVT ⎜⎜1 −
VT
⎝
2
2
2
⎞
⎛ V
⎟ (1 + λV DSQ ) ≅ I DSS ⎜1 − GSQ
⎟
⎜
VP
⎠
⎝
⎞
⎟
⎟
⎠
2
⎛ V
⎞
⎟ = I DSS ⎜1 − GSQ
⎜
⎟
VT
⎝
⎠
⎞
⎟
⎟
⎠
2
( MOSFET )
2
( JFET )
VGG = VGSQ + I DQ R S
V DD = I DQ R D + V DSQ + I DQ R S = V DSQ + I DQ ( R D + R S )
gm = −
2 I DSS
VT
V
⎛
⎜1 − GSQ
⎜
VT
⎝
⎞
⎟ Note : VT = V P for JFETs
⎟
⎠
A generic family of characteristic curves
for an n-channel device is shown to the
right. This figure is based on Figure
6.40 of your text, but all specifics as to
identifying
numbers
have
been
removed. Note that the Q-point must
be in the saturation region of the
curves. As illustrated, definition of the
Q-point
identifies
the
operational
conditions VDSQ, VGSQ and IDQ. Assuming
we
have
been
given
sufficient
information as to VDD, RL, gain(s) and Rin, our task is to define RS, RD, R1 and
R2. R1 and R2 are defined once VGG and RG are determined, so we’ll go along
with your author and solve for RS and RD first. We will be (somewhat)
following your text’s derivations, since it cannot be stressed enough that the
resulting equations may have assumptions and/or constraints that must be
followed.
Writing the dc KVL around the drain source loop in the figure above
(assuming IS•ID) and solving for the unknown resistors RS and RD yield one
equation in two unknowns:
RS + RD =
V DD − V DS
= K1
ID
,
(Equation 6.59)
where the constant K1 is introduced to simplify future notation. Note that we
need another equation to solve for the resistances (two unknowns requires
two independent equations). For our second equation, we can use either the
voltage gain or current gain expression derived in the previous section:
AV =
− g m ( R D || R L ) − ( R D || R L )
=
RS + 1 / g m
(1 + g m R S )
Ai =
− RG
RD
RS + 1 / g m RD + RL
The trick here is to realize that R S = K 1 − R D or R D = K 1 − R S and substitute
into one of the gain equations (where K1=(VDD-VDS)/ID from Equation
6.59). When this approach is taken, the gain equation has only one unknown
and may be solved. To follow your text, if we use the voltage gain equation
and substitute for RS, the resulting equation becomes:
AV =
− ( R D || R L )
.
(K1 − RD ) + 1 / g m
(Equation 6.60)
Solving this equation for RD results in the quadratic equation
RD2 − (K1 + 1 / gm − RL − RL / Av )RD − (K1 + 1 / gm )RL = 0 .
There are two possible solutions to the quadratic equation, one negative and
one positive. Since RD must be greater than zero, only the positive solution
is used. However, it’s not quite that simple and we must get through
checkpoint #1…
¾ If the positive solution of the quadratic results in RD > K1 (recall that
RS=K1-RD and K1=(VDD-VDS)/ID), a negative value for RS results. If this
happens, a new Q-point must be selected (i.e., start all over).
¾ If the positive solution results in a positive RS, we’re good to go and can
proceed as follows.
With RS and RD known, the remaining unknowns are R1 and R2. Directly
analogous to our work with BJT amplifiers, the first thing we do is write the
general dc KVL for the gate source loop to solve for VGG:
VGG = VGS + I D R S .
(Equation 6.62)
Once a value for VGG is obtained, we hit checkpoint #2…if VGG has the
same polarity as VDD, use either the equation for input resistance or
current gain (reproduced below) to solve for RG.
Ai =
Rin = RG = R1 || R2
− RG
RD
RS + 1 / g m RD + RL
Using the expressions for the Thevenin equivalent voltage and resistance,
we can now solve for R1 and R2:
R1 =
RG
1 − VGG / V DD
R2 =
RG V DD
.
VGG
(Equation 6.63)
And we’re done!
Otherwise, if VGG has the opposite polarity of VDD, it is not possible to
directly solve for R1 and R2 (since both R1 and R2 must be positive and
greater than RG). In this case, a rule of thumb is to let VGG=0V. This means
that R2 → ∞ (reference the equation above), and R1 = RG . However, the
value of RS now needs to be modified to ensure that Equation 6.62 is equal
to zero, which is direct contradiction to the solution of the quadratic we
started with!
Oh well, can’t do it right? Come now, you’ve been at this long enough to
know that there’s a trick involved!
The solution to these conflicting requirements
is illustrated in Figure 6.41 of your text and is
shown to the right. This is the same nchannel JFET CS amplifier we started with,
but now the source resistance is split and
part of it is bypassed by the capacitor CD.
Using our standard assumption that the
capacitor is open to dc and a short for the
operational frequency range, we get
R S dc = R S1 + R S 2 ; R S ac = R S 1 .
Going back to our dc KVL equation for the gate-source loop and setting VGG
equal to zero, we can define RSdc:
VGG = 0 = VGS + I D RSdc , and
R Sdc =
− VGS
.
ID
(Equation 6.64)
Once we have defined RSdc, we must back up and revise other values in the
design. The dc KVL equation for the drain-source loop (Equation 6.59) now
becomes:
R S dc + R D =
V DD − V DS
= K1 ,
ID
yielding R D = K 1 − R Sdc ( where K1 is still (VDD-VDS)/ID). To find the ac portion
of the source resistance (RSac=RS1), we repeat the step that uses the either
the voltage or current gain and solve the resulting equation. To follow the
earlier procedure, we use the voltage gain and Equation 6.60 becomes:
AV =
− ( R D || R L )
.
R Sac + 1 / g m
(Equation 6.66)
Note that, in this case, RSac is the only unknown. Solving for RSac, we get
RSac = RS1 =
− (RD || RL )
1
−
.
AV
gm
(Equation 6.67)
If we’re taking this route, we’ve got yet one more checkpoint to encounter!
If RSac is positive and
¾ less than RSdc, we can solve for RS2 ( R S 2 = R Sdc − R Sac ) and the design is
complete; or
¾ greater than RSdc. If this happens, the amplifier cannot be designed with
the gain specified and the Q-point selected. If the gain specification is
reasonable, a new Q-point should be chosen and the design process
repeated. However, if the gain specified is too high, the amplifier cannot
be designed with a single stage and/or with the transistor chosen –
which, after all this work, is a total bummer!
The CD (SF) Amplifier
The
two-source
n-channel
JFET
implementation of the CD configuration is
reproduced to the right (note that this is a
corrected version of Figure 6.39a of your
text).
As usual, before we start the specifics of this design process, keep in mind
that the important part of this discussion is how the theory (device and
circuit) is used to develop a sequence of logical steps – not the exact
equations that we’re going to come up with!
The characteristic relationships developed for the CD amplifier in the
previous section are reproduced below. Keep in mind that these expressions
were derived using assumptions such as rO very large and |λvDS|<<1. If this
condition does not hold, all bets are off and these equations must be revised
before the design process is begun.
1
gm
Rout = R S ||
AV =
Rin = RG = R1 || R2
R S || R L
( R S || R L ) + 1 / g m
Ai =
RG R S
( R S + R L )[( R S || R L ) + 1 / g m ]
The first step in any design process is to choose the operating point (Qpoint). This may be achieved by using the device characteristic curves, or
the normalized curve presented in Figure 6.20. Specifically, your author
states that a good rule of thumb for setting a starting point for the quiescent
values is the condition
I DQ = 0.5I DSS
and
VGSQ = 0.3V P .
Once the Q-point is selected, quiescent values for VDS, VGS, ID and gm are
defined. Rearranging the dc KVL equation for the drain-source loop and
solving for dc value of the source resistance, RSdc:
R Sdc =
V DD − V DS
.
ID
(Equation 6.71, Modified)
If the voltage gain is given (this is not in your text), the ac resistance of the
source circuit may be expressed as:
R Sac =
RL
⎞
⎛ 1
g m R L ⎜⎜
− 1⎟⎟ − 1
⎠
⎝ AV
.
This expression will yield a positive value for RSac for any voltage gain less
than 0.5 (recall |AV| < 1 for the CD configuration). However, since the
voltage gain is usually not defined for these amplifiers, the specification of
interest will be the current gain as discussed in your text.
Rearranging the current gain equation and solving for RSac yields:
R Sac =
RL
⎞
⎛R
g m ⎜⎜ in − R L ⎟⎟ − 1
⎠
⎝ Ai
.
(Equation 6.72)
where the substitution RG = Rin has been made. How we proceed now
depends on whether or not Rin is specified.
¾ If Rin is specified, calculate RSac from Equation 6.72. In this case, RSac
will be different from RSdc. Now…
o if RSac < RSdc, the source resistance RS is composed of RS1 and RS2 in
series and RS2 must be bypassed with a capacitor. For this case,
RSdc=RS1+RS2 and RSac=RS1.
o if RSac > RSdc, a smaller VDSQ must be chosen and the design process
started over. Shifting the Q-point in this manner causes a larger
voltage drop across the total source resistance, thereby making RSdc
(=RS1+RS2) larger. If VDS cannot be reduced enough to make RSdc >
RSac, the amplifier cannot be designed with the given Ai, Rin and
transistor type. One (or more) of these specifications must be
changed, or a second amplifier stage introduced to achieve the
required gain.
¾ If Rin is not specified, let RSac=RSdc and solve Equation 6.72 for Rin
(=RG). If the input resistance is not high enough, it may be necessary to
change the Q-point location and begin the design process over.
Once we get all that straightened out, to solve for R1 and R2 it is necessary
to solve for the Thevenin equivalent voltage VGG by writing the dc KVL
equation around the gate-source loop:
VGG = VGS + I D RSdc .
(Equation 6.73)
Using the expressions for the Thevenin equivalent voltage and resistance,
we can now solve for R1 and R2 in the usual manner:
R1 =
RG
1 − VGG / V DD
R2 =
RG V DD
.
VGG
(Equation 6.74)
The SF Bootstrap Amplifier
A variation of the common drain (a.k.a.
source follower) amplifier is known as
the SF bootstrap FET amplifier and is
shown to the right (a corrected version
of Figure 6.45 in your text). Note that
RG is now connected from the gate
across RS1, rather than from the gate to
ground. This allows the bias to be
developed across only a part of the
source resistor. There are two distinct
advantages
to
the
bootstrap
implementation:
¾ The need for a bypass capacitor across part of the source resistance is
removed.
¾ The bootstrap configuration may attain a much larger input resistance
than the normal CD (SF) configuration. This allows the designer to take
advantage of the high impedance characteristic of a FET device without
using a large gate resistance.
The ac small signal model of the
bootstrap circuit is shown to the right
(a modified version of Figure 6.46 in
your text) – notice the changes from
the conventional CD circuit of Figure
6.39b.
Our task now is to reanalyze
the small signal circuit to develop the
characteristics
of
the
bootstrap
configuration.
Please
note:
in
the
following
derivations, I am using the ac only
quantity vgs instead of the total
instantaneous quantity vGS used by your author. The circuit analysis does not
change, but we need to be clear what we’re actually dealing with.
The first thing we’re going to do is make the assumption that Rin is
sufficiently large that iin is very much smaller than i1 (iin << i1). This
assumption will allow us to say that the voltage drop across RG may be
considered negligible when compared to vout. This will allow us to define the
output voltage in terms of RS||RL, where RS=RS1+RS2.
Using the above assumption, we may define the output voltage as
v out ≅ g m v gs ( R S || R L ) .
(Equation 6.75)
The current i1 is found through a current divider as
i1 =
g m v gs R L
RS + RL
.
(Equation 6.79)
To account for the contribution of iin on the input side, the current through
RS2 is the sum of iin and i1. Also, note that there are two possible paths in the
gate-source loop for dc KVL equations (shown in purple and green in the
figure above):
v in = v gs + i1 R S 1 + (i1 + iin ) R S 2 , and
(Equation 6.78)
v in = iin RG + (i1 + iin ) R S 2 .
(1)
I’m going to take a slightly different approach for the next few equations,
but we’ll get the same place…
Combining terms and equating the two expressions for vin, we get:
v gs + i1 ( R S 1 + R S 2 ) + iin R S 2 = i in ( RG + R S 2 ) + i1 R S 2 ,
Solving for iin and substituting the expression of Equation 6.79 for i1:
iin =
v gs + i1 R S 1
RG
=
v gs ⎛
g R R ⎞
⎜⎜1 + m L S 1 ⎟⎟ .
RG ⎝
RS + RL ⎠
(2)
Prove to yourself that the above relationship is exactly the same as Equation
6.82 derived in your text. Next, substitute Equations 6.79 and (2) into (1)
for (after lots of algebra):
⎡
R
v in = v gs ⎢1 + g m ( R S || R L ) + S 2
RG
⎢⎣
⎛
g R R ⎞⎤
⎜⎜1 + m L S 1 ⎟⎟⎥ .
R L + R S ⎠⎥⎦
⎝
(3)
Finally, for the input resistance Rin, divide (3) by (2), shake violently, and we
come up with:
⎛
⎞
⎜
⎟
v in
1 + g m ( R S || R L ) ⎟
⎜
Rin =
+ RS 2 ,
= RG ⎜
g m R L RS1 ⎟
iin
⎜⎜ 1 +
⎟
R S + R L ⎟⎠
⎝
which gets you the same place as Equation 6.83, but (to my mind anyway)
doesn’t look quite so horrific.
If Rin is known or specified, RG may be solved from the above equation:
RG =
( Rin − R S 2 )( R S + R L + g m R L R S1 )
=
RS + RL + g m RS RL
[
( Rin − R S 2 ) ( R S + R L ) / g m + R L R S 1
]
.
(Equation 6.84)
(RS + RL ) / g m + RS RL
Note that the denominator in Equation 6.84 is larger than the numerator (RS
> RS1), so RG < (Rin - RS2). Equivalently, Rin > (RG + RS2), so the input
impedance may be made larger without simply relying on RG.
The current gain for the SF bootstrap is found by using Equation 6.75 to
express iout=vout/RL and calculating Ai=iout/iin:
Ai =
RG R S
.
R L R S1 + ( R L + R S ) / g m
(Equation 6.86)
Finally, the voltage gain may be found by calculating vout/vin or by using the
gain impedance formula (the easier way):
Av =
Ai R L
RG R S R L
,
Rin Rin [ R L R S 1 + ( R L + R S ) / g m ]
where Rin is given by the expression above or by Equation 6.83 in your text.