Download Slow Control - ALICE TPC Front End Electronics

Slow Control
TPC Electronics Meeting, 13/01/05
Carmen González Gutiérrez
Slow Control Architecture
RCU
Local
Slow Control
Interface
BC
commands
error
interrupt
Ethernet
warnings
FEC
Result
Memory
Local Slow Control bus
~ I2C protocol:
2 unidirectional serial data lines
1 serial clock line
DCS board
central
DCS
Board Controller


Enable the clocks and the power supply of the board
Control the power state, voltages, currents and temperature of the FECs






Register the errors of the board
Alert the RCU (INTERRUPT) in case of an abnormal situation in the board
Control the enable of the transceivers in INPUT or OUTPUT
Launch the ALTRO TEST MODE




isolate the card from the Readout bus
set the ALTRO in Test Mode
store the data with a number of words and under-sampling ratio configurable
Scan the EVENT LENGTH of the ALTRO for the Readout optimization




4-channel ADC with a temperature sensor and I2C Interface
compare the result with a configurable thresholds
BC is master of the ALTRO
set 128-bit EVL register (1 bit per channel)
send the EVL register value in 4 - 40 bit words to the ALTRO bus Interface
Counters



L1 and L2 counters
Sampling clock counter
Data Strobe counter
Register Table
Mnemonic
Reg. Name
Width
Acc.
Mode
Allow
Bcast
T_TH
Temperature Thr.
10
R/W
Y
AV_TH
AV threshold
10
R/W
Y
AC_TH
AC threshold
10
R/W
Y
DV_TH
DV threshold
10
R/W
Y
DC_TH
DC threshold
10
R/W
Y
TEMP
Temperature
10
R
N/A
AV
Analog Voltage
10
R
N/A
AC
Analog Current
10
R
N/A
DV
Digital Voltage
10
R
N/A
DC
Digital Current
10
R
N/A
L1CNT
L1 Counter
16
R
N/A
L2CNT
L2 Counter
16
R
N/A
SCLKCNT
Sampling clk counter
16
R
N/A
DSTBCNT
Data Strobe counter
8
R
TSMWORD
Test Mode Word
9
USRATIO
Under sampling ratio
CSR0
CNTLAT
Counters Latch
-
W
Y
CNTCLR
Counters Clear
-
W
Y
CSR1CLR
Conf. St. Reg 1 Clear
-
W
Y
ALRST
ALTRO Reset
-
W
Y
BCRST
BC Reset
-
W
Y
STCNV
Start Conversion mADC
-
W
Y
SCEVL
Scan event length
-
W*
Y
EVLRDO
Read event length
-
W*
N/A
N/A
STTSM
Start Test Mode
-
W*
Y
R/W
Y
ACQRDO
Read acquisition
memory
-
W*
N/A
16
R/W
Y
Configuration Status 0
16
R/W
Y
CSR1
Configuration Status 1
16
R/W
Y
CSR2
Configuration Status 2
16
R/W
Y
CSR3
Configuration Status 3
16
R/W
Y
Slow Control Architecture
RCU
Local
Slow Control
Interface
commands
BC
Ethernet
interrupt
warnings
FEC
Result
Memory
Local Slow Control bus
~ I2C protocol:
2 unidirectional serial data lines
1 clock line
DCS board
central
DCS
Instruction Sequence
Instruction Sequence
Every transaction requires the following sequence (6 words)


start condition (1 clock cycle)
1 byte (9 clock cycles)





bit [0] : read / write
bit [1..4] : FEC address
bit [5] = x
bit [6] : bcast
bit [7] = x


1 byte (9 clock cycles)


bit [0..4] : register address to access in the BC
bit [5..7] : x


WAIT FOR THE ACKNOWLEDGE FROM THE ADDRESSED CARD
2 bytes (18 clock cycles)

bit [0 ..7]: DATA


WAIT FOR THE ACKNOWLEDGE FROM THE ADDRESSED CARD
WAIT FOR THE ACKNOWLEDGE FROM THE ADDRESSED CARD AFTER EACH BYTE
stop condition (1 clock cycle)
Local Slow Control Architecture
Local Slow Control Module
Instruction
Sequence
(6 words)
address
data
command
addresser
we
Send information about:
-write or read cycle
-FEC address, broadcast
-register address
Instruction
Sequence
Builder
Sequencer
sda_in
scl
MASTER
RESULT Memory
sda_out
BC
Normal mode

The DCS sends commands continuously to the SCM for monitoring the FEC




Temperature
Digital and Analog Voltages
Digital and Analog Currents
Control of triggers



send in broadcast the command to latch the counters in the BCs
compare the value of all the counters
The DCS reads the values and controls the margins of each parameter
RCU
Local
Slow Control
Interface
BC
Master
FEC
Local Slow Control bus
Result
Memory
commands
DCS board
CENTRAL
DCS
Board Controller, ERRORS

Errors asserted by the BC








Temperature over threshold
Analog or Digital voltages under threshold
Analog or Digital currents over threshold
Power supply error (related to the ALTRO or the PASA)
Missing sampling clk
Protocol errors (from the ALTRO bus or the Slow Control)
ALTRO error
power
regulator
power
regulator
ALTRO
ps_error
PASA
ps_error
Error asserted by the voltage regulators that supply:





GTL transceivers
FPGA
Clock distribution
EPROM
mADC
THESE ERRORS ASSERT THE INTERRUPT OR THE ERROR LINE
power
regulator
GTL, FPGA, clock
power
regulator
EPROM, mADC
interrupt
interrupt
INTERRUPT
Local
Slow Control
Interface
BC
interrupt
RCU
commands
Master
warnings
FEC
Local Slow Control bus
DCS board
Result
Memory
What the Slow Control Module does if the RCU receives an interrupt ?

The SCM starts polling the error register of each FEC (via the Local Slow Control
bus) to identify the source (which FEC and the error)

Different procedures will start depending of the error:
INTERRUPT

“Hard” errors


Analog or Digital currents over thresholds
Power supply errors




ALTRO or PASA power supply errors
Error in the power regulator that supply GTL transceivers, FPGA, clock distribution,
EPROM and monitor ADC
Switch off immediately the card and inform the DCS
“Soft” errors




Temperature over threshold
Analog or Digital voltages under threshold
Missing sampling clk
Remove the card from the READOUT LIST, mask that error in the BC and
inform the DCS
In case of INTERRUPT:
Local Slow Control Module
Instruction
Sequence
address
data
command
we
Instruction
Sequence
Builder
addresser
Send information about:
-write or read cycle
-FEC address, broadcast
-register address
warning to the DCS
Interrupt
driver
Sequencer
sda_in
scl
MASTER
sda_out
Interrupt
Readout List
Depending of the Interrupt:
• Switch off the card, inform the DCS
• Remove the card from the Readout List,
mask the error, inform the DCS
BC
Status of the work

Completed tested

All the functions of the BC:








Write/Read the configuration parameters
Read all the parameters of the board (temp, voltages, currents, counters …)
ALTRO Test mode
ALTRO Readout optimization
Error flags
Interrupt assertion
The communication between the SCM and the BC
Performance:



The Local Slow Control network runs at a clock frequency of 5 MHz.
The protocol requires the transmission of a large number of control words. A single 16data bit transaction, e.g., requires 8 µs.
When an interrupt occurs, the RCU starts polling the error/status register of all FECs of
one branch. This action could require up to 100 µs in the case of a readout partition
with 13 FEC/branch.
Status of the work

Work to be done:


Complete definition and implementation of the response to an Interrupt
in the SCM
Definition of all the routines in the DCS


In normal mode (monitor the status of the cards)
Safety procedures in case of problems