Download Gsn Casino Update

ETHERNET
Model: FVXO-PC73RGB-644
LVPECL 7 x 5mm 3.3V 50ppm VCXO Freq: 644.5313MHz
for
Features
Low Jitter
Low Cost
Tri-State Enable / Disable Feature
Industry Standard Package
Gold over Nickel Termination Finish
V DD
Enable / Disable
FOX
X PRESSO
OUTPUT
ASICs
GND
Electrical Characteristics
Parameters
Frequency
Symbol
Condition
FO
Absolute Pull Range 1
Temperature Range
Supply Voltage
Input Current
APR
TO
TSTG
VDD
IDD
Output Load
Start-Up Time
644.5313 MHz
Standard operating
Storage
Standard
Standard Load
Standard
TS
±50 ppm MIN
-40°C to +85°C
-55°C to +125°C
3.3V ± 5%
120 mA
50 ohms into VDD -2.0V DC Typ
10 mS
Output Enable / Disable Time
Moisture Sensitivity Level
Termination Finish
Maximum Value
(unless otherwise noted)
100 nS
MSL
1
Au
Note 1 –Inclusive of 25°C tolerance, operating temperature range, input voltage change, load change, aging, shock and vibration.
Output Wave Characteristics
Parameters
Symbol
Condition
Standard Load
Standard Load
@ 50% VDD p-p Level
Maximum Value
Output LOW Voltage
Output HIGH Voltage
Output Symmetry
VOL
VOH
Output Enable (PIN # 2) Voltage
VIH
≥70% VDD
Output Disable (PIN # 2) Voltage
Cycle Rise Time
Cycle Fall Time
VIL
TR
TF
≤ 30% VDD
400 pS
400 pS
20% ~ 80% Vp-p
80% ~ 20% Vp-p
1.305V ~ 1.65V
2.055V ~ 2.405V MIN
45% ~ 55%
DWG-100726 | Rev. 6/2/2010
Page 1 of 2
FOXElectronics 5570 Enterprise Parkway Fort Myers, Florida 33905 USA +1.239.693.0099 FAX +1.239.693.1554 FOXONLINE
EMEA Tel/Fax: +44 .1767.312632 | Asia Hong Kong Tel: +852.2854.4285 Fax +852.2854.4282 | Japan Tel: +81.3.3374.2079 Fax: +81.3.3374.5221
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified
ETHERNET
Model: FVXO-PC73RGB-644
LVPECL 7 x 5mm 3.3V 50ppm VCXO Freq: 644.5313MHz
for
Dimensional Drawing & Pad Layout
Phase Jitter & Time Interval Error (TIE) (Typical Measurements)
Frequency
Phase Jitter
TIE
(12kHz to 20MHz)
(Sigma of Jitter Distribution)
Units
644.5313 MHz
2.2
7.6
pS RMS
Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V.
TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Random & Deterministic Jitter Composition (Typical Measurements)
Frequency
Random (Rj)
Deterministic (Dj)
(pS RMS)
(pS p-p)
Total Jitter (Tj)
(14 x Rj) + Dj
42.0 pS
644.5313 MHz
1.4
21.3
Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Pin Functional Description
Pin #
1
2
3
4
5
6
NOTES:
Name
Type
Vc
1
E/D
GND
Output
Output 2
VDD 2
1
2
Control
Logic
Ground
Output
Output
Power
Function
Enable / Disable Control of Output (0 = Disabled)
Enable / Disable Control of Output ( 0= Disabled)
Electrical Ground for VDD
LVPECL Oscillator Output
Complementary LVPECL Output
Power Supply Source Voltage
Includes pull-up resistor to VDD to provide output when the pin (2) is No Connect.
Installation should include a 0.01µF bypass capacitor placed between VDD
(Pin 6) and GND (Pin 3) to minimize power supply line noise.
DWG-100726 | Rev. 6/2/2010
Page 2 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE