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DRAFT SUBJECT TO CHANGE
Product
Factsheet
DA7210 ULTRA LOW POWER STEREO AUDIO CODEC WITH TRUE-GND
HEADPHONE DRIVER
0BDESCRIPTION
KEY FEATURES
The DA7210 is a high fidelity audio codec with integrated
true-ground capless headphone driver suitable for a variety
of low power, digital portable audio products.
Featuring a high efficiency headphone amplifier and
supporting economic single supply voltages down to 1.8V,
the ultra-low 2.5mW power consumption extends music
playback time for battery operated equipment.
Eight analogue input pins allow multiple audio sources to be
internally mixed, eliminating the need for external switches.
Both single-ended and fully-differential line and microphone
inputs are supported with built-in variable gain amplifiers to
optimize dynamic range prior to digitisation. This allows a
diverse variety of analogue audio sources such as mobile
TV, WiFi and FM radio to be managed. Input and output
mixers with stereo to mono conversion directly support
mono headsets. The acoustic components for baseband
voice are routed via an independent differential up- and
downlink. A dedicated voice mode for the TX and RX path
combined with a digital sidetone engine provides the
complete audio feature set required for mobile phones and
telephony applications.
DA7210 provides simultaneous connection to stereo
headphone, stereo line outputs, and a mono differential
output. Stereo line outputs can be differential or singeended. Both stereo outputs have volume control from -54dB
to +15dB.
Filtering and gain control is performed digitally including 5band EQ and a digital input AGC with programmable attack
and decay parameters. A configurable signal processing
engine allows various enhancements and effects on the
digital audio signal like acoustic filtering, wind noise
suppression and 3D sound.
The multislot I2S/PCM interface supports all common
sample rates between 8-96kHz in master and slave
modes. The integrated PLL supports a large range of input
and output frequencies. Sample Rate Measurement (SRM)
allows a seamless connection with non clock synchronized
audio streams. This is in addition to standard mobile
phone/USB system clock frequencies - enabling audio data
synchronization even in applications with dynamic master
clocks.
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Stereo Multi-bit Delta Sigma DAC with SNR 100dB
('A' weighted @ 48kHz)
Stereo Multi-bit Delta Sigma ADC with SNR 96dB
('A' weighted @ 48kHz)
Ultra low power Stereo Headphone Driver with
Stereo DAC to HP playback power: 2.5mW
2x58mW Output Power (16Ω)
‘Capless’ output via GND centred signals
Four level charge pump with continuous tracking of
audio signal (Class G)
Short circuit protection
Support of 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 and 96
kHz sample rates
On-chip PLL with Signal Shaper and Audio Sample Rate
Measurement
Wide range of external clocks including industry standard
256xFs, system clock 12, 13, 24, 26 or 27MHz and low
power 32kHz mode
Audio Serial Data Bus supports I2S, left/right-justified, DSP
and TDM modes
Stereo or Mono Differential Microphone Interface
Programmable Ultra-low-noise Bias Supply for electret
microphones
Volume controlled Stereo Auxiliary Inputs and Outputs
supporting FM-Radio and fixed gain Speaker Amplifiers
Fully differential Voice Link for analogue baseband
connections
Multi-mode Audio Routing and Mixers
Pop & Click suppression circuitry
ASSP DSP filter engine for digital audio enhancements
(acoustic filtering, wind noise suppression, 5-bandequalizer, 3D sound, automatic gain control)
Supports supply from single voltage (1.8/2.5V) with
embedded VDDD voltage regulator
Extensive modular power control
Package: 49 bump WLCSP - 0.4mm pitch
2BAPPLICATIONS


Smart phones, PNDs and PDAs
Portable multimedia player and camcorder
Page 1 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
DRAFT SUBJECT TO CHANGE
Product
Factsheet
SYSTEM OVERVIEW
PD
OUT1P_L
+
Sidetone-Filter
ATB0_GPO
OUT1 L
OUT1N_L
AUX1_L
A1 PGA L
+
IN PGA L
ADC L
DAC L
HP L
ADC
DIGITAL
FILTERS
Acoustic
Filtering,
Wind/Zoom
Noise
Suppression,
5 Band
Equalizer,
Automatic
Gain Control
+
M PGA L
MIC
-
MICBIAS
DA7210
MICP_R
+
M PGA R
MIC
Headphones
DAC
DIGITAL
FILTERS
Digital Mixer,
Acoustic
Filtering,
5 Band
Equalizer,
3D Sound
DATOUT
MICN_L
FM
Radio
Receiver
HPS
HP_L
MICP_L
-
HP R
HP_R
GROUND CENTRED
CLASS G
HEADPHONE
AMPLIFIERS
HPCSP
1uF
HPCF1P
1uF
HPCF1N
Charge
Pump
GNDCP
HPCF2P
1uF
MICN_R
1uF
HPCF2N
HPCSN
AUX1_R
A1 PGA R
+
IN PGA R
ADC R
Speaker
DAC R
OUT1P_R
100nF
+
AUX2P
Analog Baseband
AUX2N
OUT1 R
DA7201
100nF
+
OUT1N_R
A2 PGA
PLL
MCLK
100nF
OUT2P
+
I2S/PCM
INTERFACE
OUT2
1uF
VMID
DACREF
VBG
ADCREF
VDDDIO
VDDD
XVDDD
VDDADC
VDDDAC
AVDD
VDDCP
WCLK
DATIN
DATOUT
SCLK
SI
SK
SO
1uF 100nF 1uF
nCS
Analog Baseband
OUT2N
100nF
AGND
CODEC CONTROL
INTERFACE
Page 2 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
TABLE OF CONTENTS
SYSTEM OVERVIEW ............................................................................................................................................................... 2
General .................................................................................................................................................................................. 4
POWER SUPPLY BLOCKS ..................................................................................................................................................... 5
Audio Parametrics ................................................................................................................................................................. 5
29BMicrophone Bias ................................................................................................................................................................. 5
30BInput Mixing Units ............................................................................................................................................................... 6
31BAnalogue to Digital Converter (ADC) ................................................................................................................................. 7
32BDigital to Analogue Converter (DAC) ................................................................................................................................. 8
Line Out and Receiver Amplifier ......................................................................................................................................... 9
Line Out Amplifier ............................................................................................................................................................. 10
Dynamic charge pump...................................................................................................................................................... 10
Headphone Amplifier ........................................................................................................................................................ 11
Phase Lock Loop .............................................................................................................................................................. 12
SIGNALS AND PACKAGING ................................................................................................................................................ 13
Pin Description ..................................................................................................................................................................... 13
PACKAGE DETAILS .............................................................................................................................................................. 15
Package Outline Drawings .................................................................................................................................................. 15
ORDERING INFORMATION .................................................................................................................................................. 16
Dialog Semiconductor Worldwide Offices ........................................................................................................................... 17
Page 3 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
General
DA7210 is an ultra low power audio CODEC with a true ground headphone, mixing capability and a programmable ASSP
filter engine. It offers HiFi audio quality with class leading power consumption for portable media applications.
Featuring a high efficiency headphone amplifier and minimum supply voltage of 1.8V, the ultra-low 2.5mW power
consumption extends music playback time for battery operated equipment. The integrated PLL uses a FRACT-N PLL
architecture that supports a large range of input and output frequencies. This is in addition to standard mobile phone/USB
system clock frequencies - enabling audio data synchronization when no master clock is readily available.
Eight analogue input pins allow multiple audio sources to be internally mixed, eliminating the need for external switches.
Both single-ended and fully-differential line and microphone inputs are supported with built-in variable gain amplifiers to
optimize dynamic range prior to digitisation. This allows a diverse variety of analogue audio sources such as baseband
voice, mobile TV, WiFi and FM radio to be managed.
Input and output mixers with stereo-to- mono conversion also support mono configurations such headset/baseband line
outputs.
3 output drivers are designed in the output stage of the DA7210. One output driver will directly drive standard 3-wire 16ohm
headphones whilst the other two provide two adjustable fully differential stereo lineout channels.
Page 4 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
POWER SUPPLY BLOCKS
Audio Parametrics
Test conditions: VDDD=2.5V, Ta=25oC, fs=48kHz, 24 bit audio data unless specified otherwise
Microphone Bias
29B
PARAMETER
SYMBOL
Bias Voltage
VBIAS
TEST CONDITIONS
No load, AVDD = 2.5V
No load, AVDD = 1.8V
Maximum Current
IBIAS
Voltage drop < 50mV
Min
2.2
1.5
Typ
programmable
Max
2.3
1.6
2
UNIT
V
mA
4
Power Supply Rejection
Ratio
Output Noise Voltage
Capacitive Load
4
PSRR with
respect to
AVDD
1F
20Hz -200Hz
>2kHz
VN
IBIAS < 100uA,
100uA < IBIAS < 2mA
70
50
dB
5
µVRMS
100
200
pF
PSRR is the level difference of output signal against the voltage of a sine wave ripple voltage on VDD
Page 5 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Input Mixing Units
30B
( MICP_L, MICN_L, AUX_L, AUX2 to DC L, MICP_R, MICN_R, AUX2 to ADR R)
PARAMETER
SYMBOL
Full-scale Input Signal
VMAX
TEST CONDITIONS
single ended
differential
M/Ax-PGA=0dB, INPGA=0dB
Mic, meas. single ended
A1
A2
Min
+/- 0.5dB
Typ
Max
0.8*AVDD
1.6*AVDD
k
20
20k
Hz
20Hz – 20kHz
-0.5
0.5
dB
M-PGA
A1-PGA
A2-PGA
IN-PGA
M-PGA, A2-PGA
A1-PGA, IN-PGA
-6
-48
-6
-4.5
24
21
12
18
dB
Absolute Gain Accuracy
0dBm0 @ 1kHz
-1.0
1.0
dB
Input Gain L/R-Mismatch
20Hz – 20kHz
-0.1
0.1
dB
Input Gain Step Error
20Hz – 20kHz
-0.1
0.1
dB
RIN
Frequency Response
Amplitude Ripple
Programmable Gain
5
2F
Programmable Gain Step
Size
Input Noise Level
VNOISE
4
Power Supply Rejection
Ratio
PSRR with
respect to
AVDD
159H
Inputs connected to GND
A-weighting input referred,
measured @ ADC output
Mic (Gain = 42dB)
A1 (Gain = 21dB)
A2 (Gain = 18dB)
20Hz -2kHz
20kHz,
single ended input
20Hz -2kHz
20kHz,
differential input
15
variable
30
VPP
18
40
36
Input resistance
12
6
24
UNIT
6
1.5
dB
5
6.5
8.8
µVRMS
80
70
dB
90
70
dB
5
The gain describes the ratio of in- and output signal level at the related amplifier stage (independent whether the
connection is single ended or differential)
Page 6 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Analogue to Digital Converter (ADC)
31B
PARAMETER
SYMBOL
Full-scale Input Signal
VMAX
Signal to Noise Ratio
SNR
Total Harmonic Distortion
Plus Noise
6
3F
THD+N
7
TEST CONDITIONS
Corresponding digital
level 0 dBFS
A-weighting, no input
selected
Min
-1dBFS
Channel separation
Pass band
BPASS
Stop band
BSTOP
Typ
Max
1.6*VDDADC
VPP
96
dB
-89
dB
90
dB
0.45*fs
fs  48kHz
fs = 88.2/96kHz
Voice mode
Music Mode
Voice mode
Music Mode
Voice mode
8
Music Mode
Fs=fs = 88.2/96kHz
Between left and right
channel
Pass band Ripple
Stop band Attenuation
Group delay
Group delay mismatch
7*fs
3.5*fs
+/-0.3
+/-0.1
0.56*fs
70
55
kHz
kHz
dB
dB
4.3/fs
18/fs
9/fs
6 F7F
UNIT
600
2
µs
µs
4
Power Supply Rejection
Ratio
PSRR with
respect to
VDDADC
160H
20Hz -2kHz
20kHz
80
70
dB
6
SNR is a measure of the level difference between full scale output and the output with no signal applied
THD+N is a ratio of noise+distortion against signal
8
with 5-band-equalizer disabled
7
Page 7 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Digital to Analogue Converter (DAC)
32B
PARAMETER
SYMBOL
Full-scale Output Signal
VMAX
TEST CONDITIONS
Corresponding digital
level 0 dBFS
Signal to Noise Ratio
SNR6
Total Harmonic
Distortion Plus Noise
Total Harmonic
Distortion Plus Noise
Min
Typ
Max
UNIT
1.6*VDDDAC
VPP
A-weighting
102
dB
THD+N7
-1dBFS
-90
dB
THD+N7
-1dBFS, 32kHz PLL
mode
-80
dB
90
dB
162H
162H
8F
Channel separation
Pass band
BPASS
Stop band
BSTOP
Pass band Ripple
Stop band Attenuation
Group delay
0.45*fs
fs  48kHz
fs = 88.2/96kHz
Voice mode
Music ModeAudio Mode
Voice mode
Music ModeAudio Mode
Voice mode
Music Mode8Audio
9
Mode
Fs=fs = 88.2/96kHz
7.5*fs
3.5*fs
+/-±0.153
+/-±0.105
0.5556*fs
705
55
kHz
dB
dB
4.8/fs
18.5/fs
9/fs
7
kHz
650
µus
Group delay variation
20Hz to 20kHz
1
µus
Group delay mismatch
Between left and right
channel
2
µus
4
Power Supply Rejection
Ratio
PSRR with
respect to
VDDDAC
164H
20Hz -2kHz
20kHz
70
60
dB
9
MCLK signal can be applied as a CMOS input relative to VDDDIO or as an AC signal directly (excluding 32kHz mode)
from an oscillator output (~300mV) triangle, sine or square wave.
Page 8 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Line Out and Receiver Amplifier (OUT1P_L, OUT1N_L, OUT1P_R, OUT1N_R)
PARAMETER
SYMBOL
TEST CONDITIONS
Min
Full-scale Output Signal
VMAX
No load, single ended
No load, differential
single ended output
mode
Load Impedance
500
Typ
0.8*AVDD
1.6
*AVDD
2k
Max
VPP
1
200

µH
pF

µH
pF
1
200
25
32
differential output mode
9F
Frequency Response
Amplitude Ripple
UNIT
+/- 0.5dB
20
20k
Hz
20Hz – 20kHz
-0.5
0.5
dB
-54
15
dB
Programmable Gain
Mute Attenuation
100
dB
Programmable Gain Step
Size
1.5
dB
Absolute Gain Accuracy
0dBm0 @ 1kHz
-0.8
0.8
dB
Input Gain L/R-Mismatch
20Hz – 20kHz
-0.1
0.1
dB
Input Gain Step Error
20Hz – 20kHz
-0.1
0.1
dB
SNR6
Signal to Noise Ratio
Output Noise Level
Total Harmonic Distortion
Plus Noise
Power Supply Rejection
Ratio
Power Supply Rejection
Ratio
VNOISE
THD+N7
4
PSRR with respect
to AVDD
167H
4
PSRR with respect
to AVDD
167H
A-weighting
20 -20kHz, unweighed
Gain
gain < -15dB
Singlesingle ended
Differential
-1dBFS, 44.1kHz slave
mode non A-weighting
20Hz -2kHz
20kHz
single ended ouput
20Hz -2kHz
20kHz,
differential ouput
102
dB
µV
<5.5
<4.5
-90
dB
70
47
dB
90
70
dB
Page 9 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Line Out Amplifier (OUT2P, OUT2N)
PARAMETER
SYMBOL
Full-scale Output Signal
VMAX
TEST CONDITIONS
Min
No load
Typ
25
Amplitude Ripple
UNIT
1.6*AVDD
VPP
1
200

µH
pF
32
Load Impedance
Frequency Response
Max
+/- 0.5dB
20
20k
Hz
20Hz – 20kHz
-0.5
0.5
dB
-18
6
dB
Programmable Gain
Programmable Gain Step
Size
6
dB
Input Gain L/R-Mismatch
20Hz – 20kHz
-0.1
0.1
dB
Input Gain Step Error
20Hz – 20kHz
-0.2
0.2
dB
Signal to Noise Ratio
SNR6
A-weighting, gain = 0dB
102
dB
Output Noise Level
VNOISE
20 -20kHz, unweighed
Gain < -15dB, gain  12dB
<5
µV
-1dBFS , A-weighting
-90
dB
Total Harmonic Distortion
Plus Noise
168H
THD+N7
169H
4
Power Supply Rejection
Ratio
PSRR with
respect to
AVDD
170H
Dynamic charge pump (HPCSP, HPCSN)
PARAMETER
SYMBOL
20Hz -2kHz
20kHz
TEST CONDITIONS
Positive dynamic supply
voltage
VDDCSP
VDDCP/3/4 can optionally
be enabled if two flying
caps are available
Negative dynamic supply
voltage
VDDCSN
-VDDCP/3/4 can optionally
be enabled if two flying
caps are available
90
70
Min
dB
Typ
VDDCP
VDDCP/2
(VDDCP/3,
VDDCP/4)
-VDDCP
-VDDCP/2
(-VDDCP/3,
-VDDCP/4)
Max
UNIT
Floating capacitors
one (two)
1.0
µF
Storage capacitors
two
1.0
µF
Page 10 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Headphone Amplifier (HPL, HPR)
PARAMETER
SYMBOL
Full-scale Output Signal
VMAX
TEST CONDITIONS
Min
No load
DC output offset
Output Power per channel
PMAX
Dynamic internal supply
voltages
Quiescent current per
channel
IQ
Load Impedance
Frequency Response
Amplitude Ripple
Typ
UNIT
1.6*VDDCP
VPP
100
µV
28
mW RMS
58
mW RMS
VDDCP = 1.8V, THD <
0.1%, RL=161kHz
VDDCP = 2.5V, THD <
0.1%, RL=161kHz
VDD/3 or VDD/4 can
optionally be selected if
two flying caps are
available
±VDD
±VDD/2
(±VDD/3
(±VDD/4)
from VDDCP
100
uA
400
500

µH
pF
20
20k
Hz
-0.5
0.5
dB
-54
15
dB
13 < RL < 
13
+/- 0.5dB
20Hz – 20kHz
Programmable Gain
Max
16
Mute Attenuation
100
dB
Programmable Gain Step
Size
1.5
dB
Absolute Gain Accuracy
0dBm0 @ 1kHz
-0.8
0.8
dB
Input Gain L/R-Mismatch
20Hz – 20kHz
-0.1
0.1
dB
Input Gain Step Error
20Hz – 20kHz
-0.1
0.1
dB
Signal to Noise Ratio
SNR6
Output Noise Level
VNOISE
Total Harmonic Distortion
Plus Noise
THD+N5
172H
4
Power Supply Rejection
Ratio
A-weighting, gain = 0dB
17H
PSRR with
respect to
VDDCP
173H
20 -20kHz, unweighed
Gain, gain < -15dB
VDDCP = 1.8V, -5dBFS,
RL=16
20Hz -2kHz
20kHz
100
dB
<4.5
µVrms
-80
dB
70
50
dB
Page 11 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Phase Lock Loop (MCLK)
PARAMETER
SYMBOL
Input Jitter
Input Impedance
Input frequency
Fin
TEST CONDITIONS
Min
Max
UNIT
cycle to cycle
35
Ps
rms
100
2
Ps

pF
12.288
MHz
300
DC impedance > 10 M
0.5
Interface mode (MCLK is 256 Fs, PLL off)
256 Fs
11.289
128 Fs (96kHz)
Typ
1
Oscillator mode (MCLK from standard oscillator, PLL on)
Input frequency
Fin
I2S tracking range (SRM)
I2S clock drift
MCLK Shaper range 9
0F1
VIN AC
12.0, 13.0, 13.5, 14.4,
19.2, 19.68 MHz (x 1, 2 or
4)
32 kHz mode
Maximum mismatch of I2S
word-clock
Maximum frequency drift of
I2S word clock
For AC coupling with
internal clock shaping
10
80
MHz
32.768
300
500
kHz
4
%
50
ppm/s
1000
mVPP
Page 12 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
SIGNALS AND PACKAGING
Pin Description
A
AVDD
VMID
OUT1N_L
OUT1P_
R
DAC
REF
B
MICN_L
AGND
VDDADC
OUT1N_R
OUT2P
C
MICP_R
MICP_L
VBG
OUT1P_
L
D
AUX2P
MICN_R
AUX1_L
E
AUX2N
AUX1_R
F
DATIN
MCLK
G
7
VDDDAC
GPO
HPS
HPL
OUT2N
HPR
HPCSP
ADC
REF
AGND1
HPCSN
HPCF2N
MICBIAS
PD
HPCF1P
HPCF2P
GNDCP
DATOUT
SO
nCS
WCLK
VDDCP
HPCF1N
Sk
SI
CLK
VDDIO
VDDD
XVDDD
6
5
4
3
2
1
Figure 1: DA7210 pad arrangement for WLCSP version (Bottom view ball side up)
Below is a pin description for the DA7210. In the type column the following abbreviations have been used
 PS, VSS
Power Supply
 DI, DO, DIO
Digital Input, Output, Input/Output
 AI, AO, AIO
Analogue Input, Output, Input/Output
BUMP
7A
2A
5B
2F
1G
2G
NAME
AVDD
VDDDAC
VDDADC
VDDCP
XVDDD
VDDD
TYPE
PS
PS
PS
PS
PS
PS
DESCRIPTION
Supplies and references
Analogue supply (PLL, bias, etc)
DAC and line output supplies
Mic input and ADC supplies
Charge pump supply
Digital supply (regulator input)
Digital supply (1.5V, if on-chip regulator is active)
Page 13 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
3G
3A
4D
6A
5C
5E
1A
6B
3D
1E
VDDDIO
DACREF
ADCREF
VMID
VBG
MICBIAS
GPO
AGND
AGND1
GNDCP
PS
AI
AI
AI
AI
AO
AIO
VSS
VSS
VSS
5F
5G
6G
4F
4E
2B
SO
SI
SK
nCS
PD
HPS
DO
DIO
DI
DI
DI
AIO
4G
CLK
3F
WCLK
7F
DATIN
6F
DATOUT
7G
MCLK
Audio In-/Outputs
6C
MICP_L
7B
MICN_L
7C
MICP_R
6D
MICN_R
5D
AUX1_L
6E
AUX1_R
7D
AUX2P
7E
AUX2N
4C
OUT1P_L
5A
OUT1N_L
4A
OUT1P_R
4B
OUT1N_R
3C
OUT2N
3B
OUT2P
1B
HP_L
2C
HP_R
3E
1F
2E
1D
1C
2D
HPCF1P
HPCF1N
HPCF2P
HPCF2N
HPCSP
HPCSN
DIO
DIO
DI
DO
DI
AI
AI
AI
AI
AI
AI
AI
AI
AO
AO
AO
AO
AO
AO
AO
AO
PS
PS
PS
PS
PS
PS
Digital supply for I/O
Decoupling capacitor for DAC
Decoupling capacitor for ADC
Decoupling capacitor for VMID
Decoupling capacitor for VBG
Current supply for microphone (2mA max)
General Purpose Output
Analogue GND
Analogue GND
Digital and charge pump ground, attached to paddle
Control
4-WIRE Data output
4-WIRE Data input/2-WIRE bidirectional Data
4-WIRE/2-WIRE Clock
4-WIRE Chip select
Power down signal (power down when high)
Headphone Ground Sense
Digital Audio Interface
Digital Audio bit clock
Digital Audio left/right clock
Digital Audio Data input
Digital Audio Data output
Master clock input
Left channel differential microphone +ve input
Left channel differential microphone –ve input
Right channel differential microphone +ve input
Right channel differential microphone –ve input
Left channel single-ended auxiliary input
Right channel single-ended auxiliary input
nd
2 channel differential auxiliary +ve input
nd
2 channel differential auxiliary –ve input
Differential or single ended +ve line out left
Differential –ve line out left
Differential or single ended +ve line out right
Differential –ve line out right
nd
2 channel differential auxiliary -ve output
nd
2 channel differential auxiliary +ve output
Left head phone amp output
Right head phone amp output
Charge pump
Head phone amp charge pump floating cap1 +ve
Head phone amp charge pump floating cap1 –ve
Head phone amp charge pump floating cap2 +ve
Head phone amp charge pump floating cap2 –ve
Head phone amp charge pump storage cap +ve
Head phone amp charge pump storage cap –ve
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© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
PACKAGE DETAILS
Package Outline Drawings
This package is a 49 bump WLCSP 0.4mm pitch
Page 15 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
ORDERING INFORMATION
Part Number
DA7210-00UC6
DA7210-00UC2
Package
49-bump CSP Pbfree/green
49-bumo CSP Pbfree/green
81H
82H
Shipment Form
Waffle pack
Pack quantity
900 pcs.
T&R
2,000 pcs.
Data Sheet Status Definitions
The Data Sheet version consists of two characters, a numeral followed by a lower-case alphabetic character. The numeral
indicates Product Status (see table below), and the alphabetic character indicates the document revision level.
Notes:
Version
1a – 1z
Data Sheet
Status
Draft
Product
Status
Development
2a – 2z
Preliminary
Qualification
3a – 3z
Released
Production
Definition
Version 1 Data Sheets contain pre-tapeout information from the objective
design specification.
Dialog reserves the right to change the specification in any manner without
notice
Version 2 data sheets contain information on post-tapeout and pre-volume
production products.
Dialog reserves the right to change the specification in any manner without
notice, in order to supply
the best possible product by improvements to the design. Relevant changes
will be communicated
via Dialog’s Sales and Marketing departments
Version 3 Data Sheets contain information on volume production products.
Dialog reserves the right
to make changes at any time in order to improve the design, manufacturing
and supply. Relevant
changes will be communicated via Customer Product Notification
1. To avoid confusion, the following alphabetic characters shall not be used in document version references: i, j, l, o.
2. Please consult the latest issued version of the data sheet before initiating or completing a design.
3. The product status of the device may have changed since this data sheet was published.
Please contact Dialog for the latest information.
Page 16 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126
Disclaimer
Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties,
expressed or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for
the content in this document if provided by any information source outside of Dialog Semiconductor.
Dialog Semiconductor reserves the right to change without notice the information published in this document, including without limitation the specification
and the design of the related semiconductor products, software and applications.
Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no
representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further testing or
modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes
all liability in this respect.
Customer notes that nothing in this document may be construed as a license for customer to use the Dialog Semi-conductor products, software and
applications referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.
All use of Dialog Semiconductor products, software and applications referred to in this document are subject to Dialog Semiconductor’s Standard Terms
and Conditions of Sale, unless otherwise stated.
© Dialog Semiconductor GmbH. All rights reserved.
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Dialog Semiconductor complies to European Directive 2001/95/EC and from 2 January 2013 onwards to European Directive 2011/65/EU concerning
Restriction of Hazardous Substances (RoHS/RoHS2).
Dialog Semiconductor’s statement on RoHS can be found on the customer portal https://support.diasemi.com/. RoHS certificates from our suppliers are
available on request.
Contacting Dialog Semiconductor
Germany Headquarters
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
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Phone: +1 408 845 8500
Singapore
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Phone: +65 64 849929
United Kingdom
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Phone: +44 1793 757700
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Phone: +81 3 5425 4567
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Phone: +86 21 5178 2561
The Netherlands
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Phone: +82 2 3469 8291
Email:
[email protected]
Web site:
www.dialog-semiconductor.com
Page 17 of 17
© Dialog Semiconductor 2013 Confidential
DA7210-FS1e-131126131126