Download Tutorial 3 - Lehrstuhl für Technische Elektronik

Lehrstuhl für Technische Elektronik
Technische Universität München • Arcisstraße 21 • 80333 München
Tel.: 089/289-22929 • Fax.: 089/289-22938 • email: [email protected]
Prof. Dr. Doris Schmitt-Landsiedel
MSCD-GIST - Tutorial 3
Sample-and-Hold Circuits
Consider the Sample-and-Hold circuit shown in the figure below. The threshold voltage of the
NMOS transistor is Vth,n = 0.5V .
φclk
C hld
Beispiel fuer Eingangssignal und Takt
3
2
[V]
1
0
−1
−2
−3
0
1
t [s]
2
−5
x 10
2
1. What limits the speed of this Sample-and-Hold circuit? How to size the hold capacitance
Chld if the sampling frequency is to be increased?
2. Mark the ideal and the real sample times and sketch the output signal.
3. What is the difference between a NMOS pass-gate and a CMOS transmission-gate with
respect to the input voltage? What is the difference to an ideal switch?
4. Calculate the error of the output signal due to charge injection in dependence on the
dimensions of the switch device and the hold capacitance.
5. Calculate the ratio between the hold capacitance and the gate overlap capacitance for a
clock-feed-through voltage smaller than 100mV .
6. What is the output voltage of the Sample-and-Hold circuit if you consider the errors
calculated in question (4) and (5). Draw the transfer characteristics and discuss the
results.
7. Insert a dummy transistor and find its dimensions to compensate for charge injection and
clock-feed-through.
8. What is the consequence of a finite offset voltage in the operational amplifier?