Download Paper

Sampling Receive Equalizer
with Bit-Rate Flexible Operation up to 10 Gbit/s
Markus Grözing, Bernd Philipp, Matthias Neher, and Manfred Berroth
Institute of Electrical and Optical Communication Engineering
University of Stuttgart
Stuttgart, Germany
0
90 cm
- 18 dB
@ 5.0 GHz
-10
173 cm
S21 [dB]
Abstract—A receive equalizer IC implemented in 0.13 µm
standard CMOS technology is presented. The equalizer filter
works with sampled analog signals within a half-rate
architecture. Due to its discrete-time nature, the circuit
operates continuously on bit rates ranging from 0.5 Gbit/s to
10 Gbit/s. The equalizer core consists of a 3-tap finite-impulseresponse filter and a subsequent decision-feedback filter with
first and second post cursor feedback taps. Up to 24 dB
channel loss at the Nyquist frequency can be compensated. The
reception of a 231-1 PRBS binary data stream transmitted over
a 90 cm long trace on FR4 with 10 Gbit/s and over a 173 cm
long trace with 7 Gbit/s with a BER < 10-12 and receive-only
equalization is presented. The power consumption of the
equalizer core is 21 mW and the core area is 60 µm x 56 µm.
-20
- 19 dB
@ 3.0 GHz
-30
- 24 dB
@ 3.5 GHz
-40
-50
I.
0
INTRODUCTION
Baseband data transmission over PCB-backplanes, in
memory-processor interfaces and in fiber local area networks
reaches multi-Gbit/s rates per channel. But electrical
transmission over traces on standard PCB substrate, as well
as optical transmission over multimode fibers, suffers from
dispersion, losses and reflections. Simple binary transmitters
and receivers fail due to intersymbol interference (ISI) when
used beyond a certain transmission distance, which can be
observed at closing eye diagrams at the receiver.
Transmitter predistortion and receiver equalization are
methods to mitigate the channel impairments [1]. An
accepted method is a finite-impulse-response (FIR) filter in
the transmitter and a decision-feedback equalizer (DFE) in
the receiver [2]. Additional continuous time peaking
amplifiers at the front-end of the receiver are also used [3].
Disadvantages of predistortion are the required knowledge at
the transmitter side about the channel characteristics as well
as increased high-frequency signal power at the transmitter
that potentially couples to other channels. Equalizers for
optical systems often employ relatively long FIR-filters in
the receiver, mostly implemented with power- and areaintensive full-rate buffered LC-delay lines [4]. In contrast,
heavy 8-fold interleaving is used in the 4-tap discrete-time
FIR-only backplane receive equalizer presented in [5].
1-4244-0303-4/06/$20.00 ©2006 IEEE.
516
1
2
3
4
5
6
7
8
9
10
frequency [GHz]
Figure 1. Measured frequency response S21 of a 90 cm long and a
173 long 50 Ω transmission line on FR4 standard PCB substrate.
The equalizer presented in this work integrates a receiveside discrete-time 3-tap FIR-filter with a subsequent 2feedback-tap DFE filter. Basic track & hold circuits are used
as the FIR-filter delay elements. Neither area-consuming
LC- nor transmission line delays, nor any other continuoustime analog delays are necessary within this concept. The tap
delay is governed by the data-synchronous clock, making the
filter concept fully bit-rate flexible. Moderate two-fold
interleaving of the discrete-time signal processing is used to
enhance the maximum speed of the equalizer and to decrease
the length of the delay lines.
II.
CHANNEL RESPONSE & EQUALIZER CONCEPT
Balanced pairs of 50 Ω transmission line traces on
standard FR4 PCB substrate are used as test channels for the
equalizer. The frequency response of a 90 cm and a 173 cm
trace is shown in Figure 1. The loss of the 90 cm trace is
18 dB at the Nyquist frequency for 10 Gbit/s transmission,
19 dB for the 173 cm trace at 6 Gbit/s and 24 dB for the
173 cm trace at 7 Gbit/s.
relative response
S&H
0.4
0.3
T
T
T
T
Dout
0.2
0.1
CLK
0.0
-0.1
-5
-4
-3
-2
-1
precursor ISI
0.4
0
1
time [UI]
2
3
4
5
c-1
c1
c-2
c2
Figure 3. Filter structure of the sampling equaliser.
postcursor ISI
0.3
Dout1
c-2
c2
c-1
c1
c-1
c1
to output drivers
relative response
finite-impulse-response filter decision-feedback filter
Din
c-2
c2
Dout2
D
Din
0.2
0.1
CLK
2
0.0
-0.1
-5
-4
-3
-2
-1
0
1
time [UI]
2
3
4
5
T&H 1
Figure 2. Measured single symbol response of the
90 cm trace @ 10 Gbit/s (top) and the 173 cm trace @ 6 Gbit/s (bottom).
A. Filter design
The time-domain response of the 90 cm and 173 cm
channels to a single symbol with one unit interval (UI) length
and unity amplitude at 10 Gbit/s respectively 6 Gbit/s data
rate are shown in Figure 2. The sampled discrete-time
response is the starting point for the filter design. The
sampled response has two strong interferers preceding the
main peak – precursor ISI - and two strong interferers
following the main peak – postcursor ISI. Most of the
precursor ISI is effectively removed by a FIR filter with one
fixed and two variable feedforward paths and most of the
remaining postcursor ISI is removed by a DFE filter with a
variable first and second post cursor feedback path. The
resulting structure of the implemented sampling equalizer
filter is shown in Figure 3.
B. Half-rate signal processing
The unit interval delays necessary for the FIR-filter are
implemented with track & hold (T&H) circuits. In a full-rate
clocked concept, two cascaded T&Hs in a master-slave
configuration are necessary to implement a single unit
interval delay, with only 50% of the unit interval time
available for tracking. Thus, a chain of 6 cascaded T&Hs is
necessary for the FIR-filter, as the front-end sample & hold
circuit also incorporates two cascaded T&Hs. The
bandwidth of the T&Hs in the chain is limited by both the
sampling switch RC bandwidth at the input and the
bandwidth of the capacitively loaded output. As a result, the
overall cascaded bandwidth of a 6 stage T&H chain is too
small for 10 Gbit/s operation in 0.13 µm CMOS. Thus, a
half-rate filter structure as shown in Figure 4 is
implemented. Two interacting and interleaved FIR filters
work in push-pull manner, clocked by a differential half-rate
clock. The bandwidth advantage of the half-rate concept is
two-fold. Firstly, the unit interval delay is now implemented
with a single T&H, i.e. the chain length of T&Hs in the FIR
517
T&H 2
T&H 3
FIR filter
adder
DFE adder &
decision latch
D-Latch
Figure 4. Half rate implementation of the sampling equaliser core.
delay line is halved. Secondly, the whole unit interval is
now available for tracking. Thus, the cascaded bandwidth
problem is relaxed by a factor of four, and the problem of
accumulated noise and distortion throughout the chain is
relaxed by a factor of two. A disadvantage is the necessity
of matching between the two paths, but this issue can be
solved by symmetrical layout of the circuit. Compared to
the FIR-only receive equalizer presented in [5], the order of
interleaving is reduced drastically and is even smaller than
the order of the FIR-filter. Thus, substantial savings
concerning chip area and power consumption are possible
with the presented concept.
The half-rate concept is continued in the DFE part of the
equalizer [6]. The feedback signal addition is integrated into
the decision latches. The upper decision latch is in its
regenerative decision mode during the half-rate clock lowphase, and the up-building decision result is simultaneously
applied to the lower decision latch, which is in sense mode.
During the half-rate clock high-phase, the decision latch
modes are interchanged.
III.
CIRCUIT DESIGN
A. Track & hold circuit
The T&H circuit shown in Figure 5 is a combination of a
differential CMOS transfer gate with a unity gain buffer.
The hold capacitance is composed of the buffer input
capacitance and the hold-side transfer gate capacitance. The
clock for the n-channel transfer MOSFET is bootstrapped,
as the common mode level of the input voltage is only about
300 mV beneath the VDD level. To ensure the symmetry of
the clock paths for the n-channel and the p-channel transfer
MOSFET, the clock for the p-channel transfer transistor is
bootstrapped, too. Single-ended clock feedthrough is
minimized due to the complementary transfer gate topology.
Parametric amplification of the differential hold voltage
CLK/2n
_CLK/2p
VDD
VDD
Vout,D
I1+
I1-
I2+
Vout,D
I2-
Vin,D
Vin,D
I0
CLK/2
VSS
Figure 5. Track & hold circuit.
/2(I-2+I-1)
1
CLK/2
n/p
CLKin
V-1,D
V0,D
CLK/2
CLK/2n
CLK/2p
_CLK/2n
_CLK/2p
_CLK/2
÷2
BootStrap
CLK/2out
(V DD-VSS)/2
I0
VSS
V-2,D
V2,D
Figure 7. DFE decision latch with integrated adder.
Vout,D
I-1
VSS
V1,D
VDD
I-2
_CLK/2
I0
Figure 8. Clock generation circuitry.
Figure 6. Clocked FIR filter adder.
occurs when the transfer gate passes from track to hold
mode [7]. This effect is accepted, as it provides linear hold
voltage amplification and does not compromise the filter
action. The unity gain buffer is dimensioned for maximum
linearity by using relatively narrow differential pair
transistors and a relatively large load resistor voltage drop.
This dimensioning also optimizes the buffer speed.
B. FIR filter adder
The clocked FIR filter adder shown in Figure 6 is set up
by three differential transmission gates connected to
differential pair transconductors that add up their output
currents on a common pair of load resistors. As only the
magnitude and not the sign of the optimum FIR tap weights
changes with PCB trace length and data rate, the tap sign is
fixed by wiring. The tap weights maxima are set by the
dimensioning of the respective transconductor transistor
widths. The weights are adjusted by steering the currents I-1
and I-2 via current mirrors, that are fed by externally applied
control currents. Half the sum of the currents I-1 and I-2 is
injected into each output node by p-channel MOSFETs to
ensure a constant common mode voltage level at the output.
This is especially important for the input of the following
DFE adder and avoids degeneration of the differential pair
transconductors at large tap weights.
C. DFE decision latch with integrated adder
The adder for the decision feedback equalization is
integrated into a CML decision latch as shown in Figure 7.
The input voltage is applied to the clocked track
transconductor, and the decision is made by the clocked
cross-coupled latch transconductor. During tracking, the
feedback signals are added via adjustable differential
518
transconductors. A separate transconductor is attached for
plus and minus feedback sign. The respective sign is selected
by applying the DFE tap control currents to the respective
current mirror control input.
D. Clock generation circuitry
Six individual half-rate clock paths have to be provided
for the equalizer core. The DFE works with a
complementary pair of full swing CMOS clock signals. The
T&H circuits and the clocked FIR filter adder require
complementary pairs of bootstrapped near full swing signals
for both the n-channel and the p-channel transfer transistor.
The clock generation circuitry is shown in Figure 8. The
externally provided full rate clock signal is first amplified
and made differentially by an input clock driver chain. The
differential clock signal is then divided by two cascaded
CML-latches. The divided signal enters a tapered CML
driver chain and then two parallel tapered CMOS inverter
chains. The first CMOS inverter decision level is controlled
by a feedback loop to ensure 50% duty cycle at the clock
driver outputs. The complementary bootstrapped clock
signals are generated by bootstrap circuits that incorporate
capacitors and small clocked MOSFETs. The two bootstrap
common mode levels are preset in the circuit, but they may
be tuned by external control voltages.
IV.
EXPERIMENTAL RESULTS
The PCB trace inputs are fed by the differential data
signals of an Anritsu MP1763C pulse-pattern generator
(PPG). The PCB trace outputs and the PPG clock are fed to
the equalizer chip via on-wafer probe heads. The equalizer
half rate data and clock outputs are connected to an error
detector (ED) and to a 20 GHz bandwidth sampling scope.
x: 50 ps/div, y: 60 mV/div
x: 25 ps/div, y: 60 mV/div
Figure 11. Chip photograph with equalizer core magnified.
Chip area: 1400 µm x 600 µm. Equalizer core area: 60 µm x 56 µm
TABLE I.
supply voltage VDD
1.3 V
PDC equalizer core*
21 mW
maximum bit rate fmax 10 GBit/s PDC clock generator**
33 mW
minimum bit rate fmin 0.5 Gbit/s PDC total (with drivers) 200 mW
max. poss. channel loss for BER < 10-12, PRBS 231-1, 7 Gbit/s
24 dB
min. Vpp,PPG for BER < 10-11, PRBS 27-1, 10 Gbit/s, 90 cm FR4 300 mV
min. Vpp,PPG for BER < 10-11, PRBS 27-1, 6 Gbit/s, 173 cm FR4 230 mV
*circuitry corresponding to figure 4; **circuitry in dashed box of figure 8.
equal. off
-2
-4
PRBS
-4
31
-6
-8
PRBS
-10
2 -1
2 -1
7
log(BER)
log(BER)
x: 50 ps/div, y: 50 mV/div
x: 25 ps/div, y: 60 mV/div
173 cm FR4 trace @ 6 Gbit/s
90 cm FR4 trace @ 10 Gbit/s
Figure 9. PRBS 231-1 transmission with Vpp,PPG = 400mV.
Eye diagrams of PCB trace output (top),
of equalizer half-rate output with the equalization disabled (center),
and with the equalization enabled (bottom).
0
0
-2
-6
equalization of channels with about 18 to 19 dB loss is
300 mV at 10 Gbit/s and 230 mV at 6 Gbit/s.
V.
equal. off
PRBS
PRBS
-8
7
31
2 -1
2 -1
-10
-12
-0.5
0.0
0.5
sampling phase [UI]
-12
173 cm FR4 trace @ 6 Gbit/s
90 cm FR4 trace @ 10 Gbit/s
-0.5
EQUALISER PERFORMANCE SUMMARY
0.0
0.5
sampling phase [UI]
CONCLUSION
A 0.5 Gbit/s to 10 Gbit/s sampling receive equalizer is
presented. The combined FIR and DFE filter characteristic
can be frequency-shifted continuously due to the sampling
principle. A channel loss of up to 24 dB can be compensated
with an equaliser core power consumption of 21 mW plus
33 mW for clocking. The core chip area is 60 µm x 56 µm.
The topic of automatic adaption that is integrated into the
equalizer circuit has to be addressed in future work.
Figure 10. Measured BER versus equalizer sampling phase
with Vpp,PPG = 400mV and the equalizer coefficients held constant.
REFERENCES
Pseudo-random bit sequences (PRBS) of length 27-1 and
231-1 are used for bit error rate (BER) testing. The equalizer
coefficients are set manually by external current sources.
Measured eye diagrams at the PCB trace output are
shown in Figure 9 (top). The equalizer output eyes with the
equalization coefficients set to zero (center) and to the
optimum values (bottom) are shown beneath. As the
equalizer filter is clocked and as the DFE latches and the
output driver chains offer a lot of gain, an eye impression is
present even with the equalization disabled, but many
decisions are false or remain metastable. With the
equalization enabled, the eyes become clearly open. The
BER performance versus the equalizer sampling phase
(varied with the PPG clock delay feature) is shown in
Figure 10. A virtual eye appears, when the equalization is
enabled. Table I summarizes the equalizer performance. A
maximum loss of 24 dB at the Nyquist frequency can be
compensated by the equalizer at 7 Gbit/s. The minimum
required voltage swing at the PCB trace inputs for
519
[1]
[2]
[3]
[4]
[5]
[6]
[7]
J. Liu, X. Lin, “Equalization in high-speed communication systems,”
IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 4-17, April
2004.
R. Payne et al, “A 6.25-Gb/s binary transceiver in 0.13-µm CMOS for
serial data transmission across high loss legacy backplane channels,”
IEEE JSSC, vol. 40, no. 12, pp. 2646-2657, December 2005.
T. Beukema et al., “A 6.4-Gb/s CMOS SerDes core with feedforward and decision-feedback equalization,” IEEE JSSC, vol. 40, no.
12, pp. 2646-2657, December 2005.
S. Reynolds, P. Pepeljugoski, J. Schaub, J. Tierno, D. Beisser, “A 7tap transverse analog-FIR filter in 0.13µm CMOS for equalization of
10Gb/s fiber-optic data systems,” ISSCC 2005, pp. 330-331, February
2005.
J. E. Jaussi et al., “8-Gb/s source-synchronous I/O link with adaptive
receiver equalization, offset cancellation, and clock de-skew,” IEEE
JSSC, vol. 40 no. 1, pp. 80-88, January 2005.
Y.-S. Sohn, S.-J. Bae, H.-J. Park, S.-I. Cho, “A 1.2 Gbps CMOS DFE
receiver with the extended sampling time window for application to
the SSTL channel,” 2002 Symp. on VLSI Circuits, pp. 92-93,
February 2005.
S. Ranganathan, Y. Tsividis, “Discrete-time parametric amplification
based on a three-terminal MOS varactor: analysis and experimental
results,” IEEE JSSC, vol. 38 no. 12, pp. 2087-2093, December 2003.