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Custom Silicon Solutions, Inc.
CSS555C
Micropower Timer (with Internal Timing Capacitor)
GENERAL PART DESCRIPTION
The CSS555C is a micropower version of the popular 555 timer IC. It features an operating current
under 5µA and a minimum supply voltage of 1.2V, making it ideal for battery-operated applications. A
six-decade programmable counter is included to allow generation of long timing delays. Configuration
data for the counter is held in EEPROM to maintain the standard pin count of eight. The analog circuits
are temperature compensated to provide excellent stability over a wide ambient temperature range. A
simple four-wire interface provides Read/Write access to the EEPROM. The CSS555C device includes
an internal precision timing capacitor (CTI). Its value is trimmed to 100pF ±1%.
Key Features
Pin Configuration
GND
1
TRIGGER
2
OUTPUT
3
RESET
4
CSS555C
• Lowest power 555 timer (by > 10X)!
Active mode current < 5 µA
• Wide operating range
Wide supply range: 1.2V to 5.5V
Temperature range: -40°C to +85°C
• Internal 6 decade, programmable counter
Settings = 1, 10, 102, 103, 104, 105 & 106
Multiplies delay time by up to 106
Delay times from microseconds to days
8
V+
7
DISCHARGE
6
THRESHOLD
5
CONTROL V
PDIP or SOIC
Figure 1
• Internal 100pF, ±1% Timing Capacitor
User adjustable, 0.2pF resolution
• Pin-for-pin compatible with 555 series timers
Monostable or Astable operation
• Extremely low transient switching current
“Break-Before-Make” output driver
• Temperature stability – 0.005% per °C
Typical Application Circuit
Long Period Delay Generator
VDD
Trigger
Output
2
Reset
4
3
CSS555C
1
8
RA
7
6
5
RB
Operating conditions:
RA = RB = 4.7MΩ,
6
Internal counter = 10 (maximum)
CINT = 100pF, Delay = 16.3 minutes
Average power = 7.5 µW at VDD = 3.0V
Applications
• Portable & Battery-Powered Systems
• Precision Timing & Pulse Generation
Figure 2
• Ultra Long Period Delay Generation
Ordering Information
• Single Cell Battery Applications
• Ultra Low Power Timers
• Pulse Width Modulation
• Low Cost, High Reliability Applications
Part Number
Package Description
CSS555C-ID
8 pin plastic DIP
CSS555C-IS
8 pin plastic SOIC
See page 9 for more details and options.
Custom Silicon Solutions Inc.
17951 Sky Park Circle, Suite F
Irvine, CA 92614
(949) 797-9220 • FAX: (949) 797-9225 • www.CustomSiliconSolutions.com
Custom Silicon Solutions, Inc. ©2009
1
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Block Diagrams
Standard 555 Timer Configuration (Std. Mode)
(Programmable counter bypassed, Divider setting = 1)
VDD
8
R1
Control Voltage
Threshold
VH
5
_
3
Comp
+
6
Q
R
CTI
100pF
Trigger
R1+R2+R3 ~ 6 MΩ
For VDD > 1.8V, VH = 2/3 x VDD, VL = 1/3 x VDD
For VDD < 1.8V, VH = 0.9 x VDD, VL = 0.1 x VDD
R2
Flip
Flop
S
2
_
VL
7
Output
Discharge
Q
Reset
Comp
+
R3
4
Reset
1
VSS
Figure 3
Extended Period Configuration (EP Mode)
(Programmable counter enabled, Divider setting ≥ 10)
VDD
8
R1
Control Voltage
Threshold
VH
5
6
_
Configuration
EEPROM
Sel
In0
Comp
+
Out
Flip
Flop
R2
CTI
100pF
S
_
VL
Clk
Q
R
Mode
Run
Mode
Control
Q
Reset
Reset
Enbl
Sel
6 Decade
Counter
Q
Trig
Q
3
Output
In1
2:1 Mux
Clk
Reset
7
Comp
+
Discharge
R3
1
VSS
2
Trigger
4
Reset
Figure 4
EEPROM Bit Assignments
Counter
Configuration
xxxxx000
xxxxx001
xxxxx010
xxxxx011
xxxxx100
xxxxx101
xxxxx110
xxxxx111
Divider Setting
(Mult)
1 (Std. 555)
10
100
1K
10K
100K
1M
1 (Std. 555)
Mode
Control Bits
xxxx0xxx
xxxx1xxx
xxx0xxxx
xxx1xxxx
xx0xxxxx
xx1xxxxx
Bit 6
Bit 7
Table 1A
Function
Astable Mode (“Don’t Care” if Std. 555)
Monostable Mode (“Don’t Care” if Std. 555)
Micro Power
Low Power
Standard Voltage (Trip levels = ⅓ & ⅔ VDD)
Low Voltage (Trip levels = 10% & 90% VDD)
Unused
1 (Read Only)
Table 1B
Note: For detailed programming information, see Application Note AN555-1 (CSS555_App_Note1_Serial_Interface)
Custom Silicon Solutions, Inc. ©2009
2
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Supply Voltage (VDD)
Voltage at any Pin
Total Current into VDD Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
6V
-0.3 to VDD +0.3V
50 mA
60 mA
-65°C to +140°C
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications
are not ensured when operating the device at absolute maximum ratings.
Electrical Characteristics
Temperature = 25°C, Test Circuit #1, unless otherwi se specified
(If VDD < 1.8V, “Low Voltage” mode must be selected to provide adequate comparator input levels. EE Bit5 = 1)
Parameter
Symbol
Supply Range
VDD
Supply Current
(No DC load on OUTPUT pin, RL = ∞)
IDD
Timing Accuracy
(Micro power setting, EE Bit 4 = 0)
(Monostable & Astable Modes)
TAVDD
Timing Drift with Temperature
(Monostable & Astable Modes)
TDTEMP
Timing Shift with Supply Voltage
(Monostable & Astable Modes)
TSVDD
Maximum Oscillator Frequency
Control Voltage
fMAX
VCTRL
Trigger Voltage
VTRIG
Reset Voltage
Output Voltage
(Timer Output Pin)
VRST
VOL
VOH
Discharge Saturation Voltage
(Discharge Output Pin)
Input Current
(Trigger, Reset & Threshold Inputs)
Discharge Leakage Current
Output Rise & Fall Times
Input Capacitance
Internal Timing Capacitor (NPO)
VDIS
IIN
IDIS
tR, tF
CIN
CTI
Conditions
Min
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
1.8
1.2
Max
Units
5.5
5.5
V
V
2.2
3.1
4.3
4.0
6.0
8.0
µA
µA
µA
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
1.0
1.0
1.0
2.0
2.0
2.0
%
%
%
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
45
35
35
ppm/°C
ppm/°C
ppm/°C
0.10
0.15
0.15
%/V
%/V
%/V
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
RA,B = 4.7KΩ, CTI = 100 pF
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
VDD = 1.5V, ISINK = 1 mA
VDD = 3.0V, ISINK = 4 mA
VDD = 5.0V, ISINK = 10 mA
VDD = 1.5V, ISOURCE = 1 mA
VDD = 3.0V, ISOURCE = 4 mA
VDD = 5.0V, ISOURCE = 10 mA
VDD = 1.5V, ISINK = 2.5 mA
VDD = 3.0V, ISINK = 10 mA
VDD = 5.0V, ISINK = 25 mA
64
88
30
8
0.3 x VDD
1.35
2.75
4.50
Typ
1
67
90
33
10
0.5 x VDD
0.07
0.16
0.31
1.40
2.85
4.73
0.07
0.18
0.36
VDD = 5.5V
VIN = 0.0V to 5.5V
VDD = 5.5V
10
VDD = 3.0V, CL = 10 pF
5
10
100
Trim Resolution = 0.2pF
1
99
70
92
36
12
0.7 x VDD
0.15
0.25
0.50
0.15
0.25
0.50
MHz
%V
%V
%V
%V
V
V
V
V
V
V
V
V
V
V
pA
100
nA
101
ns
pF
pF
Table 2
Custom Silicon Solutions, Inc. ©2009
3
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Electrical Characteristics (cont)
Temperature = -40°C to +85°C, Test Circuit #1, unle ss otherwise specified
(If VDD < 1.8V, “Low Voltage” mode must be selected to provide adequate comparator input levels. EE Bit5 = 1)
Parameter
Symbol
Supply Range
VDD
Supply Current
(No DC load on OUTPUT pin, RL = ∞)
IDD
Timing Accuracy
(Micro power setting, EE Bit 4 = 0)
(Monostable & Astable Modes)
TAVDD
Timing Drift with Temperature
(Monostable & Astable Modes)
TDTEMP
Timing Shift with Supply Voltage
(Monostable & Astable Modes)
TSVDD
Maximum Oscillator Frequency
VCTRL
Trigger Voltage
VTRIG
Reset Voltage
Output Voltage
(Timer Output Pin)
VRST
VOL
Typ
Max
Units
V
V
2.2
3.1
4.3
5.5
5.5
5.0
7.5
10.0
µA
µA
µA
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
1.0
1.0
1.0
2.5
2.5
2.5
%
%
%
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
45
35
35
ppm/°C
ppm/°C
ppm/°C
0.10
0.15
0.15
%/V
%/V
%/V
VDD = 1.5V, ISINK = 1 mA
VDD = 3.0V, ISINK = 4 mA
VDD = 5.0V, ISINK = 10 mA
VDD = 1.5V, ISOURCE = 1 mA
VDD = 3.0V, ISOURCE = 4 mA
VDD = 5.0V, ISOURCE = 10 mA
VDD = 1.5V, ISINK = 2.5 mA
VDD = 3.0V, ISINK = 10 mA
VDD = 5.0V, ISINK = 25 mA
VDD = 5.5V
VIN = 0.0V to 5.5V
VDD = 5.5V
VDD = 3.0V, CL = 10 pF
VDIS
Input Current
(Trigger, Reset & Threshold Inputs)
Discharge Leakage Current
Output Rise & Fall Times
Input Capacitance
Internal Timing Capacitor (NP0)
1.8
1.2
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
VOH
Discharge Saturation Voltage
(Discharge Output Pin)
Min
RA(B) = 1MΩ, CT = 0.001µF
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
RA,B = 4.7KΩ, CTI = 100 pF
fMAX
Control Voltage
Conditions
Standard VDD (EE Bit 5 = 0)
Low VDD (EE Bit 5 = 1)
VDD = 1.5V
VDD = 3.0V
VDD = 5.0V
IIN
IDIS
tR, tF
CIN
CTI
Trim Resolution = 0.2pF
64
88
30
8
0.3 x VDD
1.30
2.70
4.40
99
1
67
90
33
10
0.5 x VDD
0.07
0.16
0.31
1.40
2.85
4.73
0.07
0.18
0.36
10
1
5
10
100
70
92
36
12
0.7 x VDD
0.20
0.30
0.60
0.20
0.30
0.60
100
101
MHz
%V
%V
%V
%V
V
V
V
V
V
V
V
V
V
V
pA
nA
ns
pF
pF
Table 3
Test Circuit #1
VDD
CSS555C
VSS
RA
VDD
Trigger
Output
Trigger Dischg
Reset
Reset Control
Output Thresh
RB
CT
Figure 5
Custom Silicon Solutions, Inc. ©2009
Note:
CT ≡ External Timing Capacitor
CTI ≡ Internal Timing Capacitor
CTOTAL ≡ CT + CTI
4
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
Pin Name
VSS
TRIGGER
OUTPUT
RESET
CONTROL V
THRESHOLD
DISCHARGE
VDD
Primary Function (Normal Mode)
Ground
Initiates timing cycles (Active low)
Timer Output (CMOS Levels)
Asynchronous timer reset (Active low)
Upper comparator switch level
Upper comparator analog input
Open drain FET, on when OUTPUT = 1
Positive voltage supply
Secondary Function (EE Programming)
Serial Clock
Serial Data Out
Serial Data In
R/W enable (Active if VCTRL < 0.5V)
Table 4
Applications Information
General
Delay Time Equations:
For standard supply voltages (VLOW Bit = 0)
Charge time (VTH = 0V to ⅔ VDD) = 1.1 x RA x CTotal
For low voltage mode (VLOW Bit = 1)
Charge time (VTH = 0V to 0.9 VDD) = 2.3 x RA x CTotal
where CTotal = (CInternal + CExternal) or (CTI + CT)
The CSS555C IC may be used in many applications as a
direct replacement for the popular 555 timer. It features
the lowest 555 operating current and a minimum supply
voltage of 1.2V. It also features a programmable decade
counter for generating long time delays. An internal
EEPROM stores the counter configuration: Divide by 1
3
4
5
6
(standard 555) or divide by 10, 100, 10 , 10 , 10 or 10 .
The internal counter allows long time delays to be
generated with small value capacitors.
RESET
TRIGGER
OUTPUT
Monostable Operation
(Standard 555 Mode)
The circuit in Figure 6 shows a monostable or “one shot”
configuration. A single, positive output pulse is generated
on the falling edge of the TRIGGER input. When
TRIGGER goes low, a flip-flop is set, the OUTPUT pin is
set high and DISCHARGE allows the timing capacitor to
charge towards VDD via RA. When VTH reaches the upper
comparator trip level, the flip-flop is reset, OUTPUT is
forced low and DISCHARGE pulls VTH to GND. After VTH
has discharged, the circuit is ready for the next trigger
pulse. Typical signal waveforms are shown in Figure 7.
The RESET input must be held high (inactive) during the
timing cycle. If RESET is brought low, the OUTPUT pin is
immediately forced low and the cycle is terminated.
0V
Figure 7 – Monostable Waveforms (Std. Mode)
Figure 8 provides a log-log selection chart. It shows the
time delay for various combinations of RA and CTotal. With
the counter bypassed (Mult = 1), time delays from 1usec to
1 second are easily generated with capacitor values from
100pF to 1uF. For long time delays (or medium delay
times using small capacitor values) the “Extended Period”
configuration should be used. (See the next section.)
RA
VDD
Trigger
Output
Trigger Dischg
Reset
Reset Control
Output Thresh
⅔ VDD
VCAP
VDD
CSS555C
VSS
Mult = 1
VTH
RA = 1K
1.0000
10K
100K
1M
Ctotal = Ct+Cti (uF)
CT
Optional
Trigger
Output
Reset
Figure 6 – Monostable Circuit (Std. Mode)
Blue:
Std. VDD
10M
0.0100
0.0010
Green:
Low VDD
In the monostable configuration, the duration of the timing
cycle is simply the time required to charge the timing
capacitor from GND to the upper comparator trip level. The
trip level is nominally ⅔ VDD. At low supply voltages it is
increased to 0.9 VDD. (An EEPROM bit controls this
selection.) The delay time equations for both conditions
are provided in the following paragraph.
Custom Silicon Solutions, Inc. ©2009
0.1000
0.0001
0.01
0.10
1.00
10.00
100.00
1000.00
Delay Time (ms)
Figure 8 – Time Delay Chart
5
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Extended Delay Time Equations:
For standard supply voltages (VLOW Bit = 0)
Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal
Total Delay Time = Counter Setting (or Mult) x tOSC
Total Delay Time = Mult x 0.695 x (RA+2RB) x CTotal
where CTotal = CT + CTI
CT = External timing capacitor
CTI = Internal 100pF timing capacitor
Monostable Operation
(Extended Period or “EP” Mode)
For longer time delays, the circuit in Figure 9 uses the
internal decade counter to effectively multiply the value of
the timing capacitor. Three bits in the EEPROM select a
6
multiplier value from 10 to 10 . The 555 analog block is
configured as a free running oscillator, which is the input
clock to the counter. On the falling edge of TRIGGER, the
555 oscillator is enabled, OUTPUT is set high, the decade
counter is enabled and a new timing cycle begins. The
timing cycle ends when the counter reaches the selected
terminal count. Waveforms for an extended delay cycle
are shown in Figure 10.
For low voltage mode (VLOW Bit = 1)
Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal
Total Delay Time = Counter Setting (or Mult) x tOSC
Total Delay Time = Mult x 2.197 x (RA+2RB) x CTotal
The chart in Figure 11 shows nominal delay times for
6
multiplier settings from 1 to 10 and resistor values
(RA+2RB) from 1KΩ to 10MΩ. (The internal timing
capacitor, CTI, equals 100pF. No external capacitor.) The
resulting delay times cover an eight-decade range!
VDD
CSS555C
VSS
RA
VDD
Trigger
Output
Trigger Dischg
Reset
Reset Control
Output Thresh
VTH
RB
CTI = 100pF
RA+2RB = 1K
1000000
10K
100K
1M
10M
CT
100000
Optional
Blue:
Std. VDD
Counter Value
Trigger
Output
Reset
Figure 9 – Extended Period Delay Circuit
10000
1000
100
Green:
Low VDD
10
1
1.E-02
RESET
TRIGGER
1.E-01
1.E+00 1.E+01
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Delay Time (sec)
OUTPUT
Figure 11 – Extended Period Delay Chart
Mult = 10
VCAP
The component values required for some common delay
times are listed in Table 5. For this calculation, the value of
RA and RB are equal. To keep the overall power low,
values above 1MΩ were selected.
⅔ VDD
⅓ VDD
0V
Delay
1 msec
1 sec.
1 min.
1 hour
1 day
1 week
Figure 10 – Extended Period Waveforms
In the Extended Period monostable configuration, the
duration of the timing cycle is the oscillator period
multiplied by the counter setting. The 555 oscillator is
configured for astable operation. (The internal TRIGGER
signal to the oscillator is internally tied to THRESHOLD.
See Figure 4.) VCAP oscillates between ⅓ & ⅔ VDD (or 10%
& 90% if low voltage mode is selected). The delay time
equations for both supply conditions are provided in the
following paragraph.
Custom Silicon Solutions, Inc. ©2009
Multiplier
1
1K
100K
1M
1M
1M
CTotal Value
100pF
100pF
100pF
500pF
0.01uF
0.1uF
RA & RB
2.35 MΩ
4.8 MΩ
2.9 MΩ
3.5 MΩ
4.1 MΩ
2.9 MΩ
Table 5 – Extended Period Delay Table
Note:
CTotal = CT + CTI
CT = External timing capacitor (may be zero)
CTI = Internal 100pF timing capacitor
6
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Free Running Oscillator Equations:
For standard supply voltages (VLOW Bit = 0)
Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal
Osc. Freq. (fOSC) = 1/tOSC = 1.44/[(RA+2RB) x CTotal]
where CTotal = CT + CTI
CT = External timing capacitor
CTI = Internal 100pF timing capacitor
Astable Operation
(Standard 555 Mode)
The circuit in Figure 12 shows the astable or “free running
oscillator” configuration. If the counter setting equals one,
the counter is bypassed and the device operates like a
standard 555 timer. With the TRIGGER input tied to
THRESHOLD, a new timing cycle is started each time VTH
drops below the lower comparator trip level.
For low voltage mode (VLOW Bit = 1)
Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal
Osc. Freq. (fOSC) = 1/tOSC = 0.455/[(RA+2RB) x CTotal]
VDD
CSS555C
VSS
Duty Cycle = RB/(RA+2RB)
RA
VDD
The chart in Figure 14 shows nominal oscillator
frequencies for resistor values (RA+2RB) from 1KΩ to 10MΩ
and capacitor values from 100pF to 1uF. The resulting
frequency range extends from 1 Hz to 1 MHz. (For this
chart, the counter is bypassed; Mult = 1.)
Trigger Dischg
Output
Output Thresh
Reset
Reset Control
VTH
RB
CT
Optional
Output
1.0000
Reset
Ctotal = Ct+Cti (uF)
Blue:
Std. VDD
Figure 12 – Astable Circuit (Std. Mode)
The capacitor charges to ⅔ VDD through (RA+RB) and
discharges to ⅓ VDD through RB. (As in the monostable
mode, the trip levels are changed to 10% & 90% for low
supply voltages. This selection is made via the EEPROM.)
The duty cycle is determined by the ratio of RA and RB.
Typical signal waveforms are shown in Figure 13. The
RESET input must be held high for the oscillator to be
active. If RESET is brought low, the OUTPUT pin is
immediately forced low and oscillation halts. Equations for
the free running oscillator are provided in the following
paragraph.
0.1000
0.0100
RA+2RB =
10M
1M
100K
10K
1K
0.0010
Green:
Low VDD
0.0001
1
10
100
1000
10000
100000
1000000
Frequency (Hz)
Figure 14 – Astable Frequency Chart (Std. Mode)
Astable Operation
RESET
(Extended Period or “EP” Mode)
The circuit in Figure 15 employs the internal decade
counter to divide the 555 oscillator frequency by the
6
multiplier setting. The multiplier value, 10 to 10 , is
selected by the EEPROM. The 555 analog block is
configured as a free running oscillator, which supplies the
input clock to the counter. The oscillator runs when
RESET is high (logic one) and TRIGGER is low. Each
divide by 10 stage of the decade counter consists of a
divide by 5 followed by a divide by 2. This configuration
provides a 50% output duty cycle no matter which multiplier
setting is selected. Waveforms for this mode are shown in
Figure 16.
OUTPUT
Mult = 1
VCAP
⅔ VDD
⅓ VDD
0V
Figure 13 – Astable Waveforms (Std. Mode)
Note: The TRIGGER signal is connected to VTH
Custom Silicon Solutions, Inc. ©2009
7
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
VDD
1000000
CSS555C
RA
Blue:
Std. VDD
VDD
Trigger
Output
Trigger Dischg
Reset
Reset Control
Output Thresh
100000
VTH
Counter Value
VSS
RB
CT
Optional
Trigger
Output
10000
1000
100
RA+2RB =
10M
CT = 100pF
1M
100K
10K
1K
10
Reset
Green:
Low VDD
1
1
Figure 15 – Astable Circuit (EP Mode)
10
100
1000
10000
100000
1000000
Frequency (Hz)
Figure 17 – Astable Frequency Chart (EP Mode)
RESET
TRIGGER
EEPROM (Configuration Memory)
OUTPUT
Mult = 10
VCAP
An internal EEPROM provides two bytes of nonvolatile
memory that stores the configuration information and the
100pF capacitor trim setting. The configuration bits control
6
the multiplier setting (1 to 10 ), the power setting (micro or
low) and the comparator trip levels (standard or low
voltage). (See Tables 1A & 1B for more details.) By
employing an internal EEPROM for configuration control,
the pin count and pin functions remain compatible with
existing 555 IC’s.
⅔ VDD
⅓ VDD
0V
Figure 16 – Astable Waveforms (EP Mode)
The EEPROM includes a high voltage generator. No
special signal levels are required to Read or Write to it.
Access to the EEPROM is enabled by forcing the
CONTROL pin to GND. (This pin is normally left open and
an internal voltage divider holds it at ⅔VDD.) With
CONTROL held at GND, the TRIGGER and RESET pins
are redefined to be SCLK (Serial Clock) and SDIN (Serial
Data In). Data from the EEPROM can be read at the
OUTPUT pin. The interface is simple and straightforward.
It can support programming individual units or devices
installed in their application circuit. A detailed description
of the serial interface is provided in Application Note
AN555-1 (“CSS555C EEPROM Serial Interface”). A
development kit is available and provides both
programming and evaluation capabilities. It uses a
standard PC and one USB port. Please contact Custom
Silicon Solutions for more information.
Free Running Oscillator Equations:
For standard supply voltages (VLOW Bit = 0)
Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal
Osc. Freq. (fOSC) = 1/tOSC = 1.44/[(RA+2RB) x CTotal]
Output Frequency = fOSC/Mult
where CTotal = CT + CTI
CT = External timing capacitor
CTI = Internal 100pF timing capacitor
For low voltage mode (VLOW Bit = 1)
Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal
Osc. Freq. (fOSC) = 1/tOSC = 0.455/[(RA+2RB) x CTotal]
Output Frequency = fOSC/Mult
Duty Cycle = 50%
The chart in Figure 17 shows nominal oscillator
6
frequencies for multiplier settings from 1 to 10 and resistor
values (RA+2RB) from 1KΩ to 10MΩ. (The internal timing
capacitor, CTI, equals 100pF.
No external timing
capacitor.) The resulting frequencies range from less than
1Hz to 1MHz.
Custom Silicon Solutions, Inc. ©2009
The core EEPROM cell is a differential, floating gate circuit.
Like an SRAM, it features zero static current. Its output
data is valid whenever the supply voltage is above 1.0V. It
has excellent data retention and endurance characteristics.
Data retention is greater than 10 years at 85°C and its
endurance (maximum number of Store cycles) is greater
than 100,000 cycles. A typical Store operation can be
performed in less than 25 msec.
8
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Supply Current Considerations
Internal Timing Capacitor
The internal supply current used by the CSS555C can be
divided into three main components:
1) ~ 1.8uA constant current (independent of VDD)
2) ~ 6 MΩ from VDD to GND (0.5uA at VDD = 3V)
3) ~ 0.5uA switching current at VDD = 3V, FOSC = 100KHz
(~ linearly proportional to VDD & FOSC)
To minimize the second component, keep VDD as low as
possible. To minimize the switching current, keep VDD &
FOSC low. (Choose a lower multiplier value so the oscillator
frequency is well below 100 KHz.)
The internal timing capacitor is a Poly/Poly structure which
has excellent stability over temperature (TC ~ 25 ppm/°C)
and voltage (VC ~ 250 ppm/V). It consists of a fixed 75pF
capacitor (CTIB) and a 0pF to 40pF trim capacitor (CTIA).
Eight EEPROM bits store the trim setting with a step size of
~ 0.16pF. The value is set at final package test, but may
be re-adjusted by the user. (See application note AN555-1
for more details.) The third capacitor, CS, is the stray
capacitance due to the pad cell, bond wire and package
leadframe. It is typically 5pF.
The external current is determined by the values of RA and
RB. They should be as high as practical. (PCB surface
leakage typically limits the value to ≤10MΩ.)
THRESHOLD
PIN
EETRIM
The CSS555C has a “Break-Before-Make” driver for the
OUTPUT signal. This circuit eliminates the large “through
current” that flows directly from VDD to GND during each
output transition. This significantly reduces the noise
injected into the power supply. The discharge path in the
monostable configuration is another source of transient
current. (When VTH reaches the upper trip point, the
capacitor is very quickly discharged to GND.) To minimize
this transient current, simply add a resistor (RLIM) in series
with the DISCHARGE pin. (see Figure 18) The value of
RLIM must be low enough to allow the timing capacitor to
completely discharge before the next timing cycle. A
typical value for RLIM is 1KΩ to 10KΩ.
8
Poly/Poly
Capacitor
CTIA
0pF - 40pF
VSS
Ordering Information
Part
Number
Package
Description
Shipping
Options
CSS555C-ID
8 pin plastic DIP
50 units / Rail
CSS555C-IS
8 pin plastic SOIC
CSS555C-ISTR
8 pin plastic SOIC
98 units / Rail
2500 units /
Tape & Reel
Contact CSS
for options
N.A.
CSS555C_IW
RA
VDD
Trigger
Output
Trigger Dischg
Reset
Reset Control
Output Thresh
CS
5pF
Figure 20 – Internal 100pF Timing Capacitor
VDD
CSS555C
CTIB
75pF
CSS555C_DVK
Die or
Tested Wafers
Development Kit
RLIM
VTH
Table 6 – Ordering Options
CT
All packaging options use lead free materials. All part
types are rated for operation from -40°C to +85°C.
Optional
The default configuration stored in EEPROM is:
Configuration Data =
Operating Mode =
Power Setting =
Voltage Setting =
Timing Capacitor =
Figure 18 – Monostable with RLIM
ESD Protection
All input and output pins include protection devices to
guard against ESD damage. A simplified schematic of the
input protection circuit is shown in Figure 19. The voltage
levels at all pins should be kept between (VSS – 0.3V) and
(VDD +0.3V) to prevent forward biasing the diodes.
80HEX
Standard 555
Micro
Standard
Trimmed to 100pF
Packaged parts may be ordered with alternate
configuration settings. A minimum purchase and/or service
charge may apply. Please contact CSS for details.
Development Kit
Input/Output
Pin
The “CSS555C Development Kit” is a PC based system
that allows the user to Read and Program the internal
EEPROM. It includes an easy to use dialog box and serial
interface (USB port required). The circuit card includes
plenty of extra terminals so that most applications can be
built and evaluated quickly and easily.
For more
information, please refer to the development kit’s
instruction manual.
VDD
To Internal
Circuits
Input Protection
Diodes
Figure 19 – Input Protection Circuit
Custom Silicon Solutions, Inc. ©2009
9
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Typical Performance Characteristics
IDD vs. VDD & Temperature
IDD vs. VDD & Temperature
30
10
+125C
Power Setting = Micro
+125C
8
+25C
+25C
-40C
-40C
20
6
IDD (uA)
IDD (uA)
Power Setting = Low
+85C
25
+85C
4
15
10
2
5
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.0
0.5
1.0
1.5
2.0
2.5
Figure 21 Supply Current (Micro Power)
4.0
4.5
5.0
5.5
6.0
Normalized Frequency Drift vs. Temperature
Normalized Frequency Drift vs. VDD
2.0
Astable Mode
VDD = 5.0V
Std. VDD
1.5
1.5
CT = 1nF; RA,RB = 1Meg
Temperature = 25C
Low VDD
Astable Mode
VDD = 3.0V
CT = 10nF; RA,RB = 100K
VDD = 2.0V
1.0
1.0
Delta Freq. (%)
Delta Freq. (%)
3.5
Figure 22 Supply Current (Low Power)
2.0
0.5
0.0
-0.5
0.5
0.0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50
-25
0
VDD (V)
Propagation Delay vs. Trigger
Level
4.0
4.0
Propagation Delay (usec)
4.5
3.5
3.0
1.5
100
Low VDD Trip Levels (10% & 90%)
Standard Trip Levels (1/3 & 2/3 VDD)
2.0
75
Propagation Delay vs. Trigger
Level
5.0
4.5
VDD
5V
3V
2V
Power Setting
Micro
Low
50
Figure 24 Frequency Drift vs. Temperature
5.0
2.5
25
Temperature (deg. C)
Figure 23 Frequency Drift vs. VDD
Propagation Delay (usec)
3.0
VDD (V)
VDD (V)
3.5
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
VDD
3.0V
2.0V
1.5V
Power Setting
Micro
Low
3.0
0.0
0
5
10
15
20
25
30
35
Figure 25 Propagation Delay (Standard VDD)
Custom Silicon Solutions, Inc. ©2009
0
1
2
3
4
5
6
7
8
9
Trigger Low Level (%VDD)
Trigger Low Level (%VDD)
Figure 26 Propagation Delay (Low VDD)
10
Version 1.1, May 2009
10
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Typical Performance Characteristics (continued)
Minimum Trigger Pulse Width vs. Trigger
Level
5.0
Minimum Trigger Pulse Width vs. Trigger
Level
5.0
Low VDD Trip Levels (10% & 90% VDD)
4.5
4.0
4.0
Pulse Width (usec)
Pulse Width (usec)
Standard Trip Levels (1/3 & 2/3 VDD)
4.5
3.5
3.0
VDD
5.0V
3.0V
2.0V
2.5
Power Setting
Micro
Low
2.0
3.5
VDD
3.0V
2.0V
1.5V
Power Setting
Micro
Low
3.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
0
5
10
15
20
25
30
0
35
1
2
3
Trigger Low Level (%VDD)
Figure 27 Trigger Pulse Width (Std. VDD)
6
7
8
9
10
Timer OUTPUT Drive High vs. Temperature
10
VDD
3.0V
1.5
VDD
1.5V
1.0
0.5
IOH measured at VOH = VDD - 0.2V
VDD = 5.0V
9
VDD
5.0V
Output Source Current (mA)
Output High Voltage (VDD-Vout) (V)
5
Figure 28 Trigger Pulse Width (Low VDD)
Timer OUTPUT High Voltage vs. Source
Current
2.0
4
Trigger Low Level (%VDD)
8
7
VDD = 3.0V
6
5
4
3
VDD = 1.5V
2
1
0
0.0
0.1
1.0
10.0
-50
100.0
-25
0
Output Source Current
(mA)
25
50
75
100
125
Temperature (degrees C)
Figure 29 OUTPUT VOH vs. IOH
Figure 30 OUTPUT IOH vs. Temperature
Timer OUTPUT Low Voltage vs. Sink Current
Timer OUTPUT Drive Low vs. Temperature
2.0
10
IOL measured at VOL = 0.2V
VDD
3.0V
9
VDD
5.0V
VDD = 5.0V
8
Output Sink Current (mA)
Output Low Voltage (V)
1.5
VDD
1.5V
1.0
0.5
7
VDD = 3.0V
6
5
4
VDD = 1.5V
3
2
1
0
0.0
-50
0.1
1.0
10.0
0
25
50
75
100
Temperature (degrees C)
Output Sink Current (mA)
Figure 31 OUTPUT VOL vs. IOL
Custom Silicon Solutions, Inc. ©2009
-25
100.0
Figure 32 OUTPUT IOL vs. Temperature
11
Version 1.1, May 2009
125
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Typical Performance Characteristics (continued)
DISCHARGE Output Drive Low vs. Temperature
DISCHARGE Low Voltage vs. Sink Current
20
2.0
VDD
5.0V
IOL measured at VOL = 0.2V
VDD = 5.0V
18
Output Sink Current (mA)
16
Output Low Voltage (V)
1.5
VDD
3.0V
VDD
1.5V
1.0
0.5
VDD = 3.0V
14
12
10
VDD = 1.5V
8
6
4
2
0.0
0
0.1
1.0
10.0
100.0
Figure 33 DISCHARGE VOL vs. IOL
Custom Silicon Solutions, Inc. ©2009
-50
-25
0
25
50
75
100
125
Temperature (degrees C)
Output Sink Current (mA)
Figure 34 DISCHARGE IOL vs. Temperature
12
Version 1.1, May 2009
CSS555C
Micropower Timer (with Internal Timing Capacitor)
PACKAGE DRAWINGS
Pinout Diagram
SOIC Mechanical Drawing
GND
1
8
VDD
TRIGGER
2
7
DISCHARGE
OUTPUT
3
6
THRESHOLD
5
CONTROL V
RESET
4
CSS
CSS555C-IS
YYWWG
Figure 35
SOIC Dimensions
Inches
Symbol
MIN
MAX
A
A1
B
C
D
E
e
H
h
L
α
0.053
0.004
0.014
0.007
0.189
0.150
H
Pin 1 Indicator
D
Millimeters
MIN
MAX
0.069
0.010
0.019
0.010
0.197
0.157
1.35
0.10
0.35
0.19
4.80
3.80
0.244
0.020
0.050
8°
5.80
0.25
0.40
0°
0.050
0.228
0.010
0.016
0°
E
A
A1
1.75
0.25
0.49
0.25
5.00
4.00
e
B
7° Typ
h
0° min
C
α
1.27
6.20
0.50
1.27
8°
L
Figure 36
Table 7
PDIP Mechanical Drawing
PDIP Dimensions
Inches
Symbol
MIN
MAX
A1
A2
b
b2
b3
C
D
E
E1
e
eB
Q1
S
α
0.015
0.128
0.014
0.057
0.032
0.010
0.375
0.300
0.245
0.132
0.022
0.068
0.046
0.012
0.385
0.320
0.255
0.38
3.25
0.36
1.45
0.81
0.25
9.53
7.62
6.22
0.370
0.080
0.080
8°
8.38
1.40
0.06
3°
0.100
0.330
0.055
0.025
3°
CSS
Millimeters
MIN
MAX
CSS555C-ID
3.35
0.56
1.73
1.17
0.30
9.78
8.13
6.48
E1
YYWWG
D
S
Q1
A2
A1
2.54
9.40
2.03
2.03
8°
b
e
b2
b3
Table 8
E
eB
C
α
Figure 37
Custom Silicon Solutions, Inc. ©2009
13
Version 1.1, May 2009