Download PCB Layout Narrative - Purdue College of Engineering

ECE 477
Digital Systems Senior Design Project
Spring 2009
Homework 6: Printed Circuit Board Layout Design Narrative
Due: Friday, February 27, at NOON
Team Code Name: ALF
Group No. 6
Team Member Completing This Homework: Curt Schieler
E-mail Address of Team Member: [email protected]
NOTE: This is the third in a series of four “design component” homework assignments, each
of which is to be completed by one team member. The body of the report should be 3-5 pages,
not including this cover sheet, references, attachments or appendices.
Evaluation:
SCORE
DESCRIPTION
Excellent – among the best papers submitted for this assignment. Very few
corrections needed for version submitted in Final Report.
Very good – all requirements aptly met. Minor additions/corrections needed for
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version submitted in Final Report.
Good – all requirements considered and addressed. Several noteworthy
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additions/corrections needed for version submitted in Final Report.
Average – all requirements basically met, but some revisions in content should
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be made for the version submitted in the Final Report.
Marginal – all requirements met at a nominal level. Significant revisions in
6
content should be made for the version submitted in the Final Report.
Below the passing threshold – major revisions required to meet report
*
requirements at a nominal level. Revise and resubmit.
* Resubmissions are due within one week of the date of return, and will be awarded a score of
“6” provided all report requirements have been met at a nominal level.
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Comments:
ECE 477
Digital Systems Senior Design Project
Spring 2009
1.0 Introduction
ALF is an audio recorder that uses a lossless compression algorithm. The user will have
the ability to start recording, stop recording, playback recorded audio, display information
about the compressed audio file, and choose whether to store the audio or play back the
audio right away.
The interest of this project is to implement an encoding algorithm in an FPGA. Due to the
size of the FPGA, there are many considerations when routing the PCB. ALF will need to be
a four layer board due to the number of capacitors and signals on the board and because
VCC/GND pins are scattered about the FPGA. Generally, capacitors and resistors will go on
the bottom layer, while the FPGA, microcontroller, and ICs will go on the top layer. There is
only a small section of analog signals, those that run from the line-out/mic-in connectors to
the Audio CODEC; all other signals are digital. The only major requirement is that the
SDRAM will need to be physically close to the FPGA; locations for all other chips will be
determined by convenience to route, because the assignments of the I/O pins for the FPGA
can change.
2.0 PCB Layout Design Considerations - Overall
The FPGA is the main component of ALF, and thus is the centerpiece of the PCB. Since the
only analog signals are from the mic-in/line-out connectors, the Audio CODEC chip should be
near the edge of the board (and near the connectors) to minimize the EMI from the analog
signals [6]. After the Audio CODEC, the quantized signals are passed to the FPGA for
compression. The I/O pins of the FPGA have been carefully configured to allow a direct path
from the Audio CODEC to the FPGA, allowing for some freedom when designing the PCB
layout; the Audio CODEC just needs to be placed on the correct side of the FPGA.
The SDRAM is a component that places many constraints on the layout. Because the
SDRAM [3] will be running at a high frequency (50 MHz), and because there are 38 traces that
connect the FPGA to the SDRAM, signal skew is a major concern; this issue can be addressed by
careful PCB layout. The SDRAM should be physically close to the FPGA, and all 38 pins should
be physically grouped together as much as possible. These two concerns can be addressed by
finding the largest set of unused I/O pins on one side of the FPGA. Unfortunately, there is no
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ECE 477
Digital Systems Senior Design Project
Spring 2009
side that can accomodate the entire 38-pin parade. With this in mind, the key consideration will
be ensuring that the various SDRAM traces are fairly comparable in length, to prevent signal
skew. This can be accomplished by using a corner of the FGPA and centering the SDRAM along
the same corner.
On another side of the FPGA, there will be the microcontroller and the various components
that it controls, namely the pushbuttons and LCD. There are few PCB considerations here, given
the low pin and external component requirements for this part of the board. The remaining side
of the FPGA will feature the VCO and debugging components, such as the RS232 transceiver
and the header for FPGA debug pins.
The sheer number of components that will connect the FPGA, and the required proximity of
these components (especially the SDRAM and the decoupling capacitors) demonstrate the need
for a four-layer board. There will be a ground plane and a power plane, which will be split into
1.2V, 2.5V, 3.3V, and 5V sections, relieving the board of complicated power routing on the
surface. The 4-layer board will limit PCB size, which was previously unconstrained. Now, the
board will have to stay within 30 square inches because of cost.
3.0 PCB Layout Design Considerations - Microcontroller
The microcontroller has a 0.1 uF bypass capacitor, as per the PIC24F datasheet [1], and an
internal oscillator (8MHz). There are few routing concerns with the microcontroller; it runs on
3.3V alone, and uses only 15 of its 28 pins to connect to various components. For ALF, the
FPGA will have the most considerations. The need for board centrality and closeness to SDRAM
have already been discussed. There will be one external oscillator (100 MHz VCO) that will be
placed as close to the FPGA as possible, to reduce the effect of the high frequency noise from the
oscillator, and also to preserve it from external noise.
The FPGA [2,5] will be placed such that it will overlap the 1.2V, 2.5V, and 3.3V sections of the
power plane, because it will be using all of these voltages. The presence of the power plane
sections will make the power trace routing local; there will simply need to be 50 mil power
traces (compared to 12 mils for normal traces) from the voltage regulators to the corresponding
power islands. The FPGA has 4 analog ground pins for the internal PLLs, and these will brought
to the outside of the FPGA using surface traces, then connected to a zero ohm resistor, which
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ECE 477
Digital Systems Senior Design Project
Spring 2009
will go to a digital ground section in the ground plane. The other analog circuitry (for line-out
and mic-in) will be grounded to a dedicated analog section of the ground plane, which will then
connect to the aforementioned zero ohm resistor. This layout will provide isolation for the analog
and digital grounds, until they are linked at one point (the zero ohm resistor).
A major PCB design consideration for the FPGA is the large number of datasheet-specified
bypass capacitors. To create 1.2V and 2.5V "power islands", there will be a combination of a
ferrite bead and several parallel capacitors for each of the two levels to isolate the power from
the PLL voltage inputs. There will also be 28 0.1 uF capacitors for each 1.2V power/ground pair
and 14 0.1 uF capacitors for each 3.3V power/ground pair. Finally, there are 100 uF capacitors
between 3.3V supply and ground, and 1.2V supply and ground. All of these FPGA capacitors
will be placed as close to the corresponding pins as possible, and the routing will be local
because of the 1.2V, 2.5V and 3.3V power plane sections.
4.0 PCB Layout Design Considerations - Power Supply
As mentioned previously, there will be a power plane split into 1.2V, 2.5V, 3.3V, and 5V
sections, which will each require a power trace of 50 mils on the surface from the corresponding
voltage regulator. The voltage regulators will be grouped together, with the 5V LDO supplying
the 1.2V, 2.5V, and 3.3V LDOs, and will be placed to minimize the power trace lengths.
Several capacitors will need to be placed next the voltage regulators to charge the bypass
capacitors in the rest of the circuit. Immediately after the 5V LDO, there will be a 220 uF
capacitor, and immediately after the rest of the LDOs will be 100 uF capacitors. The larger
capacitor (220 uF) will be used because of the higher current requirement thereafter, from each
of the other regulators and from the components that use a 5V supply. There might also be a 470
uF capacitor adjacent to the power terminals, for additional protection in case the previously
mentioned capacitors do not supply enough charge.
The ground plane will be split into various sections, to mirror the power plane configuration.
There will be an analog ground section for the audio circuitry between the Audio CODEC [4]
and the audio jacks. The CODEC chip, which has digital and analog circuitry, will straddle the
corresponding sections of the ground plane.
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ECE 477
Digital Systems Senior Design Project
Spring 2009
5.0 Summary
The printed circuit board layout for ALF consists of an FPGA at the center of the layout. The
FPGA interfaces with SDRAM, the microcontroller, and the audio CODEC all of which are
placed in close proximity. The SDRAM location of the SDRAM, in particular, was designed
such that the traces going to the FPGA were all of comparable length, so as to prevent signal
skew. Bypass capacitors for all of the components are placed immediately next to power pins to
supply clean, steady power to the components. There are 4 layers on the board. There are top
layer and bottom layers, which contain all of the components and signal traces. There are also
two inner two layers, which consist of a ground plane and a power plane which is split into 1.2,
2.5, 3.3, and 5V sections. ALF will have a separate analog ground plane to reduce noise coupling
on the digital power lines.
ALL TEAM MEMBERS should read Motorola Application Note AN1259
(posted on course web site) before you begin your PCB layout.
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ECE 477
Digital Systems Senior Design Project
Spring 2009
List of References
[1] Microchip. PIC24FJ64GA004 Family Data Sheet. 2008. [Online]. Available:
http://ww1.microchip.com/downloads/en/DeviceDoc/39881c.pdf. [Accessed Feb. 2009].
[2] Altera. Cyclone III Device Handbook, Volume 2. Jan 2008. [Online]. Available:
http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf. [Accessed Feb. 2009].
[3] Integrated Silicon Solution, Inc. IS42S16400 Data Sheet. Jan. 2008. [Online]. Available:
http://www.issi.com/pdf/42S16400.pdf. [Accessed Feb. 2009].
[4] Wolfson Microelectronics. WM8731 Data Sheet. Aug. 2008. [Online]. Available:
http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf. [Accessed Feb. 2009].
[5] Altera. Pin Information for the Cyclone III EP3C40 Device. 2008. [Online]. Available:
http://www.altera.com/literature/dp/cyclone3/EP3C40.pdf. [Accessed Feb. 2009].
[6] Motorola. 1995. [Online]. Available:
https://engineering.purdue.edu/ece477/Homework/CommonRefs/AN1259.pdf. [Accessed Feb.
2009].
IMPORTANT: Use standard IEEE format for references, and CITE ALL REFERENCES
listed in the body of your report. Provide “live” links to all data sheets utilized.
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ECE 477
Digital Systems Senior Design Project
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Spring 2009