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Symbolic Error Metric Determination for Approximate Computing
Symbolic Error Metric Determination for
Approximate Computing
(Extended Abstract)
Arun Chandrasekharan1 , Daniel Große1,2 , Mathias Soeken3 , Rolf Drechsler1,2
1
Group of Computer Architecture, University of Bremen, Germany
2
Cyber Physical Systems, DFKI GmbH, Bremen, Germany
3
Integrated Systems Laboratory, EPFL, Switzerland
{arun,grosse,drechsle}@cs.uni-bremen.de, [email protected]
Approximate computing refers to techniques that relax the requirement of exact equivalence between the specification and the implementation [8]. There exist several applications,
such as media processing (audio, video, graphics, and image), recognition, and data mining,
that tolerate acceptable though not always correct results [5]. Due to inherent error resilience
a precise functional behavior is not required. Several factors such as the limited perceptual
capability of humans allow imprecision in the numerical exactness of the computation in
these applications. This freedom can be exploited in the implementation of the applications
by achieving a better improvement in terms of performance and energy efficiency [1, 2, 6].
Several approaches for mathematical analyses related to imperfect computation have been
proposed which are heavily used in the implementation of approximate computing [1].
Research in approximate computing spans the whole range of research activities from
programming languages [3] to transistors [4]. There exist two main strategies to introduce
imperfection to the circuit with the aim to improve its performance [8]: (i) timing-induced
errors, e.g., by voltage over-scaling or over-clocking, and (ii) functional approximation, e.g.,
by implementing a slightly different function. Our research targets the latter strategy. Given
a specification f : Bn → Bm that describes the correct functionality, an approximated
function fˆ : Bn → Bm is sought that minimizes a given circuit cost metric (such as area or
delay) but respects a quality threshold. The quality of an approximated circuit is evaluated
using multiple error metrics such as worst-case error, average-case error, or error-rate.
Several synthesis and optimization approaches have been presented recently that approximate a circuit. However, in many cases the error metric cannot be determined precisely and
only statistical methods are used to estimate the metrics. Obviously, this limits the application of approximate computing in practice. We present symbolic methods that precisely
determine various error metrics for both combinational and sequential circuits.
We propose BDD-based methods to precisely determine error metrics in combinational
circuits. Simple metrics such as error-rate simply map to counting solutions in the symbolic
difference of the original and approximated circuit. For error metrics such as worst-case and
R. Wimmer (Hrsg.): MBMV 2016
ISBN: 978-3-00-052380-9
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Symbolic Error Metric Determination for Approximate Computing
average-case error more sophisticated algorithms are required. Details about the algorithms
have already been presented in [7].
Precisely determining the error metric of a combinational circuit is already very helpful in
the design of approximate computing, but the obtained numbers may not be accurate when
considering approximated components in sequential circuits. As an example, although the
worst-case can be computed for the approximated component in isolation, the accumulated
worst-case in the sequential circuit may differ significantly, since only a subset of the input
patterns may actually be assignable over time. Further, the sequence of successive input
patterns for the approximated component depends on the sequential logic of the overall
circuit. We have developed algorithms based on model checking that are able to prove that
certain errors such as accumulated worst-case, maximum worst-case, or average error-rate
can never occur in the design—although theoretically possible when only considering the
approximated component in isolation.
Acknowledgments. This work was supported by the German Research Foundation (DFG)
in the project MANIAC (DR 287/29-1), by the University of Bremen’s graduate school SyDe,
funded by the German Excellence Initiative, by the German Federal Ministry of Education
and Research (BMBF) in the project EffektiV (01IS13022E), and by the German Academic
Exchange Service (DAAD).
References
[1] Breuer, Melvin A.: Hardware that produces bounded rather than exact results. In Design
Automation Conf., pages 871–876, 2010.
[2] Chakradhar, Srimat T. and Anand Raghunathan: Best-effort computing: re-thinking
parallel software and hardware. In Design Automation Conf., pages 865–870, 2010.
[3] Esmaeilzadeh, Hadi, Adrian Sampson, Luis Ceze, and Doug Burger: Architecture support
for disciplined approximate programming. In Int’l Conf. on Architectural Support for
Programming Languages and Operating Systems, pages 301–312, 2012.
[4] Gupta, Vaibhav, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy: Lowpower digital signal processing using approximate adders. IEEE Transactions on Computer Aided Design of Circuits and Systems, 32(1):124–137, 2013.
[5] Han, Jie and Michael Orshansky: Approximate computing: An emerging paradigm for
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[6] Shanbhag, Naresh R., Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones: Stochastic computation. In Design Automation Conf., pages 859–864, 2010.
[7] Soeken, Mathias, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler: BDD minimization for approximate computing. In ASP Design Automation Conf., 2016.
[8] Venkatesan, Rangharajan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan:
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ISBN: 978-3-00-052380-9
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