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A 14-b 30MS/s 0.75mm2 Pipelined ADC
with On-Chip Digital Self-Calibration
Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee*, Mark Spaeth*, Jae-Whui Kim
Samsung Electronics, Co., Yongin-City, Korea 446-711
*Massachusetts Institute of Technology, Cambridge, MA 02139, USA
Stage 1
Stage 2
Vin
1
+
2x
+
-Vref
+Vref
Vo2
Vo1
+
2x
+
Abstract-A 14-b 30MS/s CMOS pipelined ADC is presented.
To prevent wide codes problem, novel 1-b per stage architecture is
proposed. The proposed ADC fully integrates a digital selfcalibration, which performs overall sequence by one flag signal.
Implemented in a 90nm digital CMOS process, the prototype ADC
achieves 83.7dB SFDR and 69.3dB SNDR with calibration. Its
active area is 0.75mm2 including the on-chip calibration logic and
the total power consumes 106mW with 3.3V and 1.0V supply.
1
-Vref
+Vref
0
0
I. INTRODUCTION
Recently-developed highly-integrated SoCs have strongly
required the high resolution ADCs with small active size as
well as low power consumption. Meanwhile, many deep submicron processes begin to provide vertical parallel plate
(VPP) capacitors, which have benefits of higher capacitance
and lower process cost but suffer from a drawback of worse
matching characteristics than metal-insulator-metal (MIM)
capacitors [1][2].
In this paper, a 14-b 30MS/s pipelined ADC is described.
To achieve high resolution of 14-b with small active area and
low power consumption, the proposed ADC employs 1-b per
stage topology without a dedicated S/H. Also, all capacitors
are implemented by VPP capacitors without any special layout
matching technique such as dummy capacitor arrays.
In the proposed digital calibration, the code transition
points are directly calibrated as in [3] for accurate calibration,
but nominal radix 2 is used to reduce the calibration coefficient lengths significantly. The digital calibration also removes the overall gain error due to capacitor mismatch.
II.
A.
PROPOSED ARCHITECTURE
Proposed 1-b per Stage Scheme
General 1-b per stage architecture is shown in Fig. 1.
Because this stage consists of one op amp and one comparator
to generate 1-b output code, 1-b per stage architecture has less
analog error sources and design complexity. Also only one
decision point per stage makes calibration algorithm simpler
and more accurate than other 1.5-b or multi bit stage
architectures. On the other hand, 1-b per stage has the
drawback of wide codes on transfer curve, which can cause a
significant nonlinearity.
To prevent wide codes, the most common method is to use
a “radix <2” stage [3]-[5]. However, it is difficult to decide
optimum radix value and the calibration hardware may be
increased due to gain reduction.
D1
D2
Fig. 1. General 1-b per stage architecture.
This design proposes a novel architecture, which can adopt
a nominal error correction scheme in 1-b per stage. Fig. 2 (a)
shows the proposed 1-b per stage scheme with radix 2 and
radix 1 stages. Using the redundant output bit from 1x gain
stage, the accumulated underflow or overflow errors through
stage 1 to stage 4 can be corrected in error correction block.
Fig. 2 (b) shows the proposed pipelined architecture. To
utilize the proposed 1-b per stage scheme to 14-b ADC, three
1x gain stages (stage 4, 9, and 14) are inserted in every three
or four 2x gain stages.
Stage
1
1
Input
Signal
(Vin)
2
3
5
4
2x
Stage 5
2x
2x
2x
Error
Correction
Output
1
Overflow
(Add 1)
1
1x
0
Nominal
(No operation)
0
1x
1
1x
0
Stage
Output (D)
Stage 4
1
0
0
0
0
1
1
1
0
0
Underflow
(Subtract 1)
(a)
Stage
Output
Bits
1x Gain
1
2
3
4
1x Gain
5
6
7
8
9
1x Gain
10
ADC
Output
Bits
1
2
3
4
5
6
7
8
11 12
9
13 14
15
16 17
10 11 12
13 14
18
19
(b)
Fig. 2. (a) Proposed 1-b per stage scheme and (b) pipelined architecture.
To reduce the calibration truncation error below 1/4LSB,
two 1-b per stages (stage 18 and 19) are added at the end of
the pipeline.
B. On-chip Digital Calibration Scheme
Fig. 3 shows a simplified digital calibration procedure,
which depicts calibration operation of a single stage. Error
components of each stage change the transfer curve from
(+Vref, -Vref) to (S1, S2) and the shift of the transfer curve
generates discontinuity on the full transfer curve of ADC.
D=0
D=1
D=0
ADC
Output
D=1
ADC
Output
-IC
Vo
+Vref
S1
Vin
S2
-Vref
D=0
S2
S1
+IC
IC=(S2-S1)/2
D=1
Vin
Vin
(a)
(b)
Fig. 3. Calibration procedure: (a) extraction mode and (b) hold mode.
Proposed digital calibration procedure consists of two
operating modes. In extraction mode, shown in Fig. 3 (a), the
calibration logic calculates the difference of S1 and S2 and
stores calibration coefficient (IC) as a digital code. In hold
mode, shown in Fig. 3 (b), ADC output code is calibrated by
adding or subtracting the calibration coefficient according to
the polarity of stage output (D). In actual implementation, the
ADC is designed to calibrate an externally-selectable number
of stages up to the first 13 stages for an ample design margin.
Due to the proposed digital correction scheme, the proposed calibration algorithm can detect the S1 and S2 which
exceed +Vref and -Vref, which results in the wide codes
problem. In that case, the calibration coefficient turns to a
negative number.
Fig. 4 shows the block diagram of the digital error correction and calibration logic. The digital calibration logic
consists of calibration control, coefficient extraction, and
coefficient summation blocks.
Calibration control block generates a reference clock
(RCLK) and control signals (CM[13:1], RM[13:1]) for
calibrated stages and coefficient extraction block.
In
coefficient extraction block, calibration coefficients (IC1 ~
IC13) are calculated by adders and stored in flip flop arrays.
In coefficient summation block, calibration coefficients are
added or subtracted according to polarity of stage outputs to
generate the total coefficient (ICT). Then, calibrated ADC
output (CDO) is calculated by adding ICT to RDO from error
correction block. The power consumption of calibration logic
is negligible because only error correction and coefficient
summation blocks operate during normal conversion cycle.
Fig. 5 shows the timing diagram of the proposed calibration
logic. First, stage 13 starts the calibration sequence after a
flag signal (CFLAG) activates the calibration logic. Stage 13
operates in 4 different modes, which are defined by CM[13]
and RM[13]. In reset mode, the comparator output of stage
13 is set to 0. During extraction mode, calibration coefficient
is extracted from add and subtraction operations which
accumulate 2048 codes to suppress glitch noise. In hold mode,
the calibration coefficient is held and reflected on the ADC
output. As soon as stage 13 turns into hold mode, stage 12
enters extraction mode by CM[12] and RM[12]. The same
calibration procedure is repeated from stage 13 to stage 1 and
overall calibration sequence is performed and completed only
by CFLAG.
CFLAG
ADCCLK
RCLK
2048x
CM[13]
RM[13]
CM[12]
RM[12]
CM[1]
RM[1]
IC13
Hold
IC12 Hold
Vin
Reset
Extraction
1-b per stages
IC1 Hold
Error
Correction
Coefficient
Summation
CM[13:1]
RM[13:1]
Reset
Extraction
Add
RDO
Hold
Subtraction
Fig. 5. Timing diagram of the proposed calibration logic.
+
ICT
IC13
IC1
RCLK
Calibration
Control
Hold
Add Subtraction
D
CFLAG
ADCCLK
(Q1)
Reset Extraction
Hold
Add Subtraction
Coefficient
Extraction
Fig. 4. Block diagram of the digital calibration logic.
CDO
III.
CIRCUIT IMPLEMENATION
Fig. 6 shows the block diagram of 1-b per stages with 2x
gain, which accomplishes the digital calibration procedure. In
hold mode (CM = RM = 0), shown in Fig. 5, 1-b per stage
generates output signal (Vo) from input signal (Vin). In
extraction mode (CM = 1, RM = 0), GND signal is sampled on
capacitors (C1 and C2) and comparator output is switched to
RM signal for extracting S2 and S1 in Fig. 3 (a).
CM
0.75mm2 including the on-chip digital self-calibration logic.
As the digital logic occupies only 16% of total ADC size, the
die area penalty of on-chip digital self-calibration is not
significant.
Q1
1
Q1
Vin
0
RM
1
Clock
Level shifters
Calibration and
correction logic
D
+
-
0
Bias
1
Q2
Q2
-Vref
+Vref
Stage1
0
C2
C1
Q1P
Q1P
Q1
Stage 2 Stage 3
Vo
+
Q2P
Q1
Q2
Fig. 8. Die photograph of the prototype ADC.
Fig. 6. 1-b per stage including calibration function.
The op amp is implemented with single-stage folded
cascode amplifiers with gain boosting technique [6] in order to
achieve large output swing range as shown in Fig. 7. The gain
boosting amplifiers employ a no-tail telescopic architecture, in
which input pairs use thin oxide transistors to provide low
parasitic capacitances and wide output swing on the folded
cascode amplifier. Op amps are designed to achieve large
open loop gain to minimize the effects of supply and
temperature variations as well as gain nonlinearity. The open
loop gain of stage 1 is designed to 110dB.
BS1
VDD
VDD
CMFB
BS1
PA
IN+
Fig. 9 shows the measured DNL and INL. With the proposed calibration, the measured DNL and INL are improved
from ±1.1LSB to ±0.5LSB and from ±6.2LSB to ±2.6LSB,
respectively.
BS2
IN-
(a)
OUT-
OUT+
OUT-
OUT+
BS3
NA
BS4
IN-
Thin oxide
transistors
IN+
Fig. 7. Gain-boosted folded cascode amplifier.
The ADC adopts gain-boosted folded cascode amplifiers at
the first 10 stages and the folded cascode amplifiers without
gain boosting techniques at the remaining stages. For high
linearity of the ADC the conventional gate bootstrapping
circuit is employed in stage 1. The size of op amps and
capacitors are scaled down considering the required accuracy
of each stage.
IV. PROTOTYPE MEASUREMENTS
The prototype ADC, shown in Fig. 8, was fabricated in a
90nm digital CMOS process and occupies an active area of
(b)
Fig. 9. Measured DNL and INL
(a) without calibration and (b) with calibration.
The calibrated output spectrum with 5MHz sine wave at
30MS/s is shown in Fig. 10. With the proposed calibration,
the measured SNDR and SFDR are improved from 58.3dB to
69.3dB and from 63.0dB to 83.7dB, respectively.
TABLE I
PERFORMANCE SUMMARY
(a)
Resolution
14-b
Conversion Rate
30MS/s
Process
90nm 1 poly 6 metal CMOS
Supply Voltage
3.3V / 1.0V
DNL / INL
±1.1LSB / ±6.2LSB (Without Calibration)
±0.5LSB / ±2.6LSB (With Calibration)
SNDR / SFDR
(@ fin = 5MHz)
58.3dB / 63.0dB (Without Calibration)
69.3dB / 83.7dB (With Calibration)
Power Consumption
Active Area
106mW
0.75mm2
(1.27mm x 0.59mm)
REFERENCES
(b)
Fig. 10. Measured output spectrum
(a) without calibration and (b) with calibration.
The measured dynamic performance at 30MS/s is illustrated in Fig. 11. The SNDR and SFDR with calibration maintain
higher than those without calibration till Nyquist rate. Table I
summarizes the measured performance.
Fig.11. SNDR and SFDR versus input frequency at 30MS/s.
V. CONCLUSION
A 14-b 30MS/s pipelined ADC has been presented. In this
work, the novel 1-b per stage architecture is proposed to
prevent wide codes problems in radix 2 stages. And the
overall errors of each stage are removed by fully-integrated
self calibration logic which is designed to be controlled by
only single flag signal. Using the proposed techniques, the
prototype ADC was implemented in an active area of
0.75mm2.
The measured results demonstrate that the
proposed techniques improve the performance of the ADC
effectively.
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[2] C.-S. Chang et al., “Advanced CMOS technology portfolio for RF IC
applications,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 13241334, July 2005.
[3] A. N. Karanicolas et al., “A 15-b 1-Msample/s digitally self-calibrated
pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 12071215, Dec. 1993.
[4] M. K. Mayes and S. W. Chin, “Monolithic low-power 16b 1Msample/s
self-calibrating pipeline ADC,” in ISSCC Dig. Tech. Papers, Feb. 1996,
pp. 312-313.
[5] J. M. Ingino and B. A. Wooley, “A continuously calibrated 12-b, 10Ms/s, 3.3-V A/D converter,” IEEE J. Solid-State Circuits, vol. 33, no.
12, pp. 1920-1931, Dec. 1998.
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