Download Memory: Paging - Cornell University

CS 4410
Operating Systems
Memory:
Paging
Summer 2011
Cornell University
1
Today
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What is paging and why do we need it?
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Paging
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Address translation scheme
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Page table
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Implementation of page table
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TLB
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Structure of page table in memory
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Paging
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Memory management scheme.
Noncontiguous physical address space of a
process.
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The process is allocated physical memory wherever
the latter is available.
It avoids external fragmentation.
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Paging
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Divide physical memory into fixed-sized blocks called
frames (size is power of 2, between 512 bytes and
8,192 bytes)
Divide logical memory into blocks of same size called
pages
Keep track of all free frames.To run a program of size
n pages, need to find n free frames and load program
Set up a page table to translate logical to physical
addresses
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Paging
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Address Translation Scheme
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Address generated by CPU is divided into:
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Page number (p) – used as an index into a page table
which contains base address of each page in physical
memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
page
number
page
offset
p
d
m-n
n
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Address Translation Scheme
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Address Translation Scheme
00000
0000
a
0001
b
0010
c
0011
d
k
0100
e
l
0101
f
0110
g
00100
j
01000
m
n
h
00
101
1000
i
01
110
1001
j
10
001
1010
k
11
010
1011
l
1100
m
1101
n
1110
o
1111
p
0111
i
page table
o
p
01100
physical
memory
10000
10100
a
b
c
d
logical memory
11000
e
f
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Paging
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User's view: memory is one single space
Actual view: the program is scattered
throughout physical memory
The OS manages physical memory.
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Frame table: Availability and owner of every frame
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Hardware Support
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The OS allocates one page table per process.
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A pointer to the page table is stored in the PCB.
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The dispatcher defines the correct hardware
page-table values.
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Implementation of page table
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Set of dedicated registers.
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Fast
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Small
In memory
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Page-table base register (PTBR)
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Slow
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Large
TLB + memory
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Translation look-aside buffer
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Special, small, fast-lookup hardware cache
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Contains a few of the page-table entries
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If page_number is in TLB get frame_number out
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Paging Hardware With TLB
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Memory Protection
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Implemented by associating protection bit with
each frame.
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Shared Pages
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Shared code
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One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
Shared code must appear in same location in the logical
address space of all processes
Private code and data
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Each process keeps a separate copy of the code and data
The pages for the private code and data can appear
anywhere in the logical address space
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Structure of the Page Table
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Hierarchical Paging
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Hashed Page Tables
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Inverted Page Tables
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Hierarchical Paging
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Hierarchical Paging
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Two-Level Paging Example
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A logical address (on 32-bit machine with 4K page size) is divided into:
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a page offset of 12 bits
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a page number of 20 bits
Since the page table is paged, the page number is further divided into:
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a 10-bit page number
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a 10-bit page offset
Thus, a logical address is as follows:
page number
p2
p1
10
10
page offset
d
12
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Hierarchical Paging
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Hashed Page Tables
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Common in address spaces > 32 bits
The virtual page number is hashed into a page table.
This page table contains a chain of elements hashing
to the same location.
Virtual page numbers are compared in this chain
searching for a match. If a match is found, the
corresponding physical frame is extracted.
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Hashed Page Tables
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Inverted Page Table
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One entry for each real page of memory.
Entry consists of the virtual address of the page stored
in that real memory location, with information about
the process that owns that page.
Decreases memory needed to store each page table,
but increases time needed to search the table when a
page reference occurs.
Use hash table to limit the search to one — or at most
a few — page-table entries.
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Inverted Page Table
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Today
●
What is paging and why do we need it?
●
Paging
●
Address translation scheme
●
Page table
●
Implementation of page table
●
TLB
●
Structure of page table in memory
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