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Static CMOS Circuits
• Conventional (ratio-less) static CMOS
– Covered so far
• Ratio-ed logic (depletion load, pseudo nMOS)
• Pass transistor logic
ECE 261
James Morizio
1
Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
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Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
D0
S
D1
S
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Example 2
2) Sketch a design using NAND, NOR, and NOT
gates. Assume ~S is available.
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Example 2
2) Sketch a design using NAND, NOR, and NOT
gates. Assume ~S is available.
D0
S
Y
D1
S
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Bubble Pushing
• Start with network of AND / OR gates
• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
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D
Y
(d)
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Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
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Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
D0
S
D1
S
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Y
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Compound Gates
• Logical Effort of compound gates
AOI21
Y=A
Y = A B+C
Y = A B+C D
A
B
C
A
B
C
D
A
Y
A
A
Complex AOI
unit inverter
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y = A (B + C) + D E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
B
gA = 3/3
gA = 6/3
gA = 6/3
gA = 5/3
p = 3/3
gB = 6/3
gB = 6/3
gB = 8/3
gC = 5/3
gC = 6/3
gC = 8/3
p = 7/3
gD = 6/3
gD = 8/3
p = 12/3
gE = 8/3
Y
2
p = 16/3
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Example 4
• The multiplexer has a maximum input capacitance
of 16 units on each input. It must drive a load of
160 units. Estimate the delay of the NAND and
compound gate designs.
D0
S
D1
S
Y
D0
S
D1
S
Y
H = 160 / 16 = 10
B=1
N=2
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NAND Solution
D0
S
D1
S
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NAND Solution
P =2+2=4
G = (4 / 3) (4 / 3) = 16 / 9
F = GBH = 160 / 9
fˆ = N F = 4.2
D0
S
D1
S
Y
D = Nfˆ + P = 12.4τ
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Compound Solution
D0
S
D1
S
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Compound Solution
P = 4 +1 = 5
G = (6 / 3) (1) = 2
F = GBH = 20
fˆ = N F = 4.5
D0
S
D1
S
Y
D = Nfˆ + P = 14τ
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Example 5
• Annotate your designs with transistor sizes that
achieve this delay.
Y
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Input Order
• Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest?
• If B arrives latest?
2
A
B
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2
2
Y
6C
2x
2C
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Input Order
• Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2τ
• If B arrives latest? 2.33τ
2
A
B
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2
2
Y
6C
2x
2C
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Inner & Outer Inputs
• Outer input is closest to rail (B)
• Inner input is closest to output (A)
2
2
A
2
B
2
Y
• If input arrival time is known
– Connect latest input to inner terminal
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Asymmetric Gates
• Asymmetric gates favor one input over another
• Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance) A
– Boost size of noncritical input
reset
– So total resistance is same
•
•
•
•
•
2
2
gA = 10/9
4/3
A
gB = 2
4
reset
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
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Y
Y
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Symmetric Gates
• Inputs can be made perfectly symmetric
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2
2
A
1
1
B
1
1
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Y
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Skewed Gates
• Skewed gates favor one edge over another
• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
A
2
1/2
unskewed inverter
(equal rise resistance)
Y
A
2
1
unskewed inverter
(equal fall resistance)
Y
A
1
1/2
Y
• Calculate logical effort by comparing to unskewed inverter
with same effective resistance on that edge.
– gu =
– gd =
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Skewed Gates
• Skewed gates favor one edge over another
• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
A
2
1/2
unskewed inverter
(equal rise resistance)
Y
A
2
1
Y
unskewed inverter
(equal fall resistance)
A
1
1/2
Y
• Calculate logical effort by comparing to unskewed inverter
with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
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HI- and LO-Skew
• Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to
the input capacitance of an unskewed inverter delivering
the same output current for the same transition.
• Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction
• But larger for the other direction
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Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
HI-skew
LO-skew
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A
A
A
2
1
2
1/2
1
1
Y
gu = 1
gd = 1
gavg = 1
Y
gu = 5/6
gd = 5/3
gavg = 5/4
Y
gu = 4/3
gd = 2/3
gavg = 1
2
A
2
B
2
A
NOR2
Y
4
A
4
1
gu = 4/3
gd = 4/3
gavg = 4/3
1
Y
gu = 5/3
gd = 5/3
gavg = 5/3
B
Y
B
A
B
A
Y
gu =
gd =
gavg =
B
Y
B
A
gu =
gd =
gavg =
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gu =
gd =
gavg =
Y
gu =
gd =
gavg =
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Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
A
2
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
A
2
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
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A
1
1
Y
gu = 4/3
gd = 2/3
gavg = 1
2
A
1
B
1
1
LO-skew
2
1
A
2
B
2
NOR2
Y
B
4
A
4
1
gu = 4/3
gd = 4/3
gavg = 4/3
Y
B
4
A
4
1/2
gu =
gd =
gavg =
Y
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gu =
gd =
gavg =
1
1/2
B
2
A
2
1
1
Y
gu = 5/3
gd = 5/3
gavg = 5/3
Y
gu =
gd =
gavg =
Y
gu =
gd =
gavg =
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Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
A
2
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
A
2
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
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A
1
1
Y
gu = 4/3
gd = 2/3
gavg = 1
2
A
1
B
1
1
LO-skew
2
1
A
2
B
2
NOR2
Y
B
4
A
4
1
gu = 4/3
gd = 4/3
gavg = 4/3
Y
B
4
A
4
1/2
gu = 1
gd = 2
gavg = 3/2
Y
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gu = 2
gd = 1
gavg = 3/2
1
1/2
B
2
A
2
1
1
Y
gu = 5/3
gd = 5/3
gavg = 5/3
Y
gu = 3/2
gd = 3
gavg = 9/4
Y
gu = 2
gd = 1
gavg = 3/2
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Asymmetric Skew
• Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
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2
Y
4/3
4
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Best P/N Ratio
• We have selected P/N ratio for unit rise and fall resistance
(µ = 2-3 for an inverter).
• Alternative: choose ratio for least average delay
P
• Ex: inverter
A
–
–
–
–
–
–
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Delay driving identical inverter
tpdf =
tpdr =
tpd =
Differentiate tpd w.r.t. P
Least delay for P =
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Best P/N Ratio
• We have selected P/N ratio for unit rise and fall resistance
(µ = 2-3 for an inverter).
• Alternative: choose ratio for least average delay
P
• Ex: inverter
A
–
–
–
–
–
–
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Delay driving identical inverter
tpdf = (P+1)
tpdr = (P+1)(µ/P)
tpd = (P+1)(1+µ/P)/2 = (P + 1 + µ + µ/P)/2
Differentiate tpd w.r.t. P
µ
Least delay for P =
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P/N Ratios
• In general, best P/N ratio is sqrt of that giving
equal delay.
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
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A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
2
A
2
B
2
NOR2
Y
James Morizio
gu = 4/3
gd = 4/3
gavg = 4/3
B
2
A
2
1
1
Y
gu = 2
gd = 1
gavg = 3/2
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Observations
• For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
• For area and power:
– Many simple stages vs. fewer high fan-in stages
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Combinational vs. Sequential Logic
In
Logic
Circuit
In
Out
Logic
Out
Circuit
State
(a) Combinational
(b) Sequential
Output = f(In, Previous In)
Output = f(In)
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Static CMOS Circuit (Review)
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Static CMOS (Review)
VDD
In1
In2
In3
PUN
PMOS Only
F =G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Netwo rks
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Properties of Complementary CMOS Gates
(Review)
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
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Influence of Fan-In and Fan-Out
on Delay
VDD
A
B
C
A
B
C
D
D
Fan-Out: Number of Gates Connected
Every fanout (output) adds two gate
capacitances (pMOS and nMOS)
FanIn: Quadratic Term due to:
1. Resistance Increasing
2. Capacitance Increasing
tp = a1 FI + a 2 FI 2 + a3 FO
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Fast Complex Gate-Design Techniques
• Trans is to r S izing :
As long as Fan-out Capacitance dominate s
• Pro g res s ive S izing :
Out
InN
MN
CL
M1 > M2 > M3 > MN
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In3
M3
C3
In2
M2
C2
In1
M1
C1
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Fast Complex Gate - Design Techniques
• Trans is to r Ordering
c ritic al path
c ritic al path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
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CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
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Fast Complex Gate - Design Techniques
• Imp ro ved Lo g ic Des ig n
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Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
VT < 0
F
In1
In2
In3
F
In1
In2
In3
PDN
VSS
(a) resistive load
VDD
PDN
VSS
(b) depletion load NMOS
PMOS
Load
VSS
In1
In2
In3
F
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
Careful design needed!
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Ratioed Logic
VDD
Resistive
Load
• VOH = VDD
VOL =
RL
RPDN
RL + RPDN
Desired: RL >> RPDN (to keep noise
margin low)
F
In1
In2
In3
tPLH = 0.69RLCL
PDN
VSS
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RPDN
Problems: 1) Static power dissipation
2) Difficult to implement a large
resistor, eg 40kΩ resistor (typical
value) needs 3200 µ2 of n-diff, i.e.
1,000 transistors!
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VDD
Depletion
Load
Active Loads
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
F
In1
In2
In3
PDN
VSS
VSS
depletion load NMOS
pseudo-NMOS
• Depletion-mode transistor has negative threshold
• On if VGS = 0
• Body effect may be a problem!
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Pseudo-nMOS
VDD
A
B
C
D
F
CL
• No problems due to body effect
• N-input gate requires only N+1 transistors
• Each input connects to only a single transistor, presenting smaller
load to preceding gate
• Static power dissipation (when output is zero)
• Asymmetric rise and fall times
Example: Suppose minimal-sized gate consumes 1 mW of static power.
100, 000 gate-circuit: 50 W of static power (plus dynamic power)!
(half the gates are in low-output state)
• Effective only for small subcircuits where speed is important, eg address
decoders in memories
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Pseudo-NMOS NAND Gate
VDD
GND
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Pass-Transistor Logic
B
Inputs
Switch
Network
Out
A
B
Is this transmission gates
necessary?
Out
B
AND gate
Need a low impedance path to ground when B = 0
• No s tatic c o ns umptio n
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Pass-Transistor Based Multiplexer
S
F = AS + BS
S
A
S
VDD
V DD
M2
Out F
F
S
M1
B
S
GND
In1
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S
S
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In2
46
Transmission Gate XOR
6 transistors
only!
B
Case 1:
B = 1, M3/M4 turned
off, F = AB
B
M2
A
A
F
M1
B
M3/M4
Case 2:
B = 0, M3/M4 turned
on, F = AB
B
F always has a path to VDD or Gnd, hence low impedance node
If not, node would be dynamic, requiring refresh due to charge leakage
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Delay in Transmission Gate Networks
5
5
5
V1
In
Vi
Vi-1
C
0
5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
(b)
m
Req
Req
Vi
Req
Req
Req
Req
Req
In
C
CC
C
C
(c)
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CC
C
Insert buffers after every m switches
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Delay in Transmission Gate
Networks
Consider Kirchoff’s Law at node Vi
Vi+1-Vi + Vi-1-Vi
C dVi
= dt
Req
Req
Therefore, dVi Vi+1 + Vi-1 - 2Vi
=
ReqC
dt
Propagation delay can be determined using Elmore delay analysis
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Delay Optimization
Delay can be reduced by adding buffers after m stages
(tbuf = delay of a buffer)
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Transmission Gate Full Adder
P
VDD
A
A
VDD
Ci
P
P
B
A
P
Ci
S Sum Generation
Ci
B
P
A
VDD
Co Carry Generation
P
Ci
Setup
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Ci
A
VDD
A
P
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NMOS Only Logic: Level Restoring Transistor
VDD
Level Restorer
B
A
Mn
VDD
Mr
M2
X
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
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Single Transistor Pass Gate with VT=0
VDD
0V
5V
VDD
0V
VDD
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS
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Complimentary Pass Transistor Logic
B
A
A
B
B
Pass-Transistor
Network
A
A
B
B
Inverse
Pass-Transistor
Network
(a)
B
B
A
F
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
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A
F=A⊕Β
(b)
A
A
B
B
F=A+B
B
OR/NOR
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F=A⊕Β
EXOR/NEXOR
54
4 Input NAND in CPL
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