Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Future Memory Devices
Document related concepts
Transcript
Indo German Winter Academy 06 Future Memory Devices By Pratik Kotkar Dept. Of Electronics and Communication Engg. IIT Guwahati under the guidance of Prof. Heiner Ryssel, University of Erlangen-Nuremberg 1 The Topic Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices? Development cycle 1. Past and present memory devices 2. Comparison of the trends in development Requirements of future devices Some materials that can be used in the future 1. Analysis of each material 2. Advantages and disadvantages 3. Comparative study Summary 2 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices ? Development cycle Requirements of future devices. Some materials that can be used in the future Summary 3 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Memory Memory is the retention of, and ability to recall, information, personal experiences, and procedures Data storage for any processor Physical memory vs. virtual memory RAM vs. ROM: RAM 4 ROM • Memory can be accessed in any order • Class of storage that cannot be written to • Read and write allowed • Contents close to hardware • Primary data storage • Programmable types • SRAM, DRAM etc. • PROM, EPROM, EEPROM etc. What are Memory Devices? Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices ? Development cycle Requirements of future devices Some materials that can be used in the future Summary 5 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Development of Memory Devices : Vacuum Tubes A device generally used to amplify, or otherwise modify, a signal by controlling the movement of electrons in an evacuated space Based on Thermionic Emission (Edison Effect) Diode and Triode types Transistors A semiconductor device that uses a small amount of voltage or electrical current to control a larger change in voltage or current BJT and FET Uses: Switching, Amplification Using in memory 6 Evolution of Memory (Past) Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Current IC Technology: Miniaturized electronic circuit consisting mainly of semiconductor devices, as well as passive components manufactured into the surface of a thin substrate of a semiconductor SRAMS Type of memory that stores data till power is applied to it It uses a “6- transistor” per bit type storage facility Advantages: High speed & no refresh needed Disadvantages: Power needs & low density 7 DRAMS Type of memory that stores data till power is applied to it but leaks out fast It uses a capacitor to store each data bit Advantages: Simplicity & high density Disadvantages: Low speed & refresh required frequently Evolution of Memory Devices Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices? Development cycle Requirements of future devices Some materials that can be used in the future Summary 8 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Current Devices: DDR , DDR 2 & SDRAM’s 1. SDRAMs wait for clock pulse before responding 2. Rated as per maximum clock rate allowed for a chip 3. SDRAM transfers data only positive edge DDR 2 Module 4. DDR 2 doubles bus frequency for more speed Flash Memory 1. Works on floating gate principal. MOSFET with two gates where one is for control and other is insulated 2. Non volatile and more shock absorbing 3. Faster access times Factors for improvement: 9 Memory density Volatility High speed Direction for Future Development USB Flash Drive Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices? Development cycle Requirements of future devices Some materials that can be used in the future Fe RAM M-RAM Phase change memory Programmable metallization cell Bi stable organic devices Molecular memory Summary 10 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What is it? Similar in construction to DRAM, which is currently used in the majority of a computer‘s main memory, but uses a ferroelectric layer to achieve nonvolatility. Ferroelectric capacitors possess the two characteristics required for a nonvolatile memory cell, that is they have two stable states corresponding to the two binary levels in a digital memory, and they retain their states without electrical power. Ferroelectricity: Phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials In a ferroelectric material, on the other hand, there is a spontaneous polarization - a displacement which is inherent to the crystal structure of the material Does not disappear in the absence of the electric field The direction of this polarization can be reversed or reoriented by applying an appropriate electric field 11 Ferroelectric RAM A FeRAM chip Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Binary state 0 Positive electric field Positive polarization Binary state 1 Negative electric field Negative polarization Working & principle: Can be permanently programmed in two different states by simply applying an electrical bias to the films Electric field causes mobile ions to align along the applied field The individual unit cells of the crystal interact with their neighboring cells to form ferroelectric domains in the material 12 Ferroelectric RAM Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Materials used: PbZrxTi1-xO3 (PZT) SrBi2Ta2O9 (SBT) (BiLa)4Ti3O12 (BLT) 1 T - 1 C type cell: 13 Read - WL: addressed - DL: addressed with positive voltage +Vcc - BL: capacitor divider between Cfe and Cbl, sense amplifier compares voltage with Vref - V < Vref: Binary state 0 - V > Vref: Binary state 1 Ferroelectric RAM Write - WL: addressed - DL: pulse +VCC (half length) - BL: +VCC: “1”, ground: ”0” Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Problems faced and disadvantages: A decrease of the remanent polarization reduces the difference between switching- and non-switching charge Polarization fatigue (after repeated read-write cycles) Fatigue Retention loss (with time) Imprint shift of the hysteresis loop leads to preference of one polarization state (write failure; only critical at low voltage) or loss of polarization (read failure) Loss Increase of temperature leads to worse material properties (i.e. defect distribution) Reading operation is “destructive” High quality semiconductor/ferroelectric material 14 Ferroelectric RAM Imprint Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What is it? Combines a magnetic device with standard silicon-based microelectronics to obtain the combined attributes of non-volatility, high-speed operation and unlimited read and write endurance not found in any other existing memory technology Magneto-resistivity: Two ferromagnetic plates separated by a thin insulating material Each memory element uses a magnetic tunnel junction (MTJ) device for data storage Composed of a fixed magnetic layer, a thin dielectric tunnel barrier, and a free magnetic layer When a bias is applied to the MTJ, electrons that are spin polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free layer moment is oriented antiparallel to the fixed layer moment 15 Magneto-Resistive RAM M-RAM Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Principle & Working: Data is stored as a magnetic state, rather than charge Sensed by measuring the resistance without disturbing the magnetic state Digit Lines and bit lines: Used for cross point writing ”Single line disturb” phenomena Sense Transistor Write: Single Bit storage MRAM During the write operation, current pulses are passed through a digit line and a bit line, writing only the bit at the cross point of those two lines Read: The isolation transistor of the target bit is turned on to bias the MTJ and the resulting current is compared to a reference to determine if the resistance state is low are high 16 Magneto-Resistive RAM MRAM array with bit and digit lines Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Toggle M-RAM: Through the use of a new free layer structure (SAF), bit orientation and current pulse sequence, the MRAM bit state can be programmed via a “toggle" mode “toggle” means that exactly the same pulse sequence is used to write from the “0” state to the “1” state and for “1” to “0;” Each time the sequence is executed the device toggles Working: Synthetic Anti Ferromagnet(SAF) Unique behavior of a synthetic anti ferromagnet (SAF) free layer that is formed from two ferromagnetic layers separated by a non-magnetic coupling spacer layer Rather than following an applied magnetic field, the two anti parallel layer magnetizations will rotate to be approximately orthogonal to the applied field A current pulse sequence is used to generate a rotating magnetic field that moves the free-layer moments through the 180° switch from one state to the other 17 Magneto-Resistive RAM Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Advantages: Disadvantages: the magnetic polarization does not leak away with time like charge does, so information is stored even when the power is turned off switching the magnetic polarization between the two states does not involve actual movement of electrons or atoms and thus has no known wear-out mechanism Induced Field Overlap Issues Power Needs in “read cycle” are much higher for the high voltage tunneling The “toggle mode” gives slower speeds due to its “multi step” write process Non volatile Density and speed comparable to DRAMs When compared to FLASH drives it has greater endurance and lower power requirement in “write cycle” where high voltage tunneling is not needed 18 Magneto-Resistive RAM Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What is it? Resistor based approach Relies on phase transitions induced by nanosecond-scale heating and cooling of small volumes of chalcogenide films within the memory cell 650 MB PD and CD-RW disks and 5.2 GB DVD-R optical memory disks using a laser-induced structural phase change in a chalcogenide alloy are now in production Chalcogenides: Collective name for group VI elements in the periodic table Property of stability at room temperature in two forms Example: Alloys of GeSbTe in “pseudo binary composition” Group VI in the periodic table 19 Phase Change Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Amorphous state (Reset state): High resistivity High current and fast quenching Crystalline state (Set state) Low resistivity Medium current for longer pulse time 20 Phase Change Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Principle and Working: The phase conversion is accomplished by heating and cooling the material When melted it loses all crystalline structure, and rapid cooling below glass transition temperature causes the material to be locked into its amorphous phase To switch the memory element back to its conductive state, the material is heated to a temperature between the glass transition temperature and the melting temperature Set - reset transition: No change for lower currents Rapid change for I > 450 µA The amorphous form is established by rapid cooling on the falling edge of pulse 21 I-R characteristics of PCM Reset - set transition: Resistance steeply decreases for I >100 µA Crystallization of GST Very large currents lead it to amorphous form again hence medium currents are used Phase Change Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Use in memory Arrays: An array of access transistors must each be capable of providing sufficient power to a memory element to melt a portion of the chalcogenide alloy Thermal isolation of the memory element itself from the heat-sinking substrate and metallization is crucial Three modes of operation: VA RC D e v ic e VA RC D e v ic e Cn VA RC D e v ic e VA RC D e v ic e C n+1 Row n Row n+1 Memory Array using PCM’s Read: The electric field is limited by applying a low voltage. A small current will pass if the material is in the amorphous state; in the crystalline phase, the applied voltage and the resistance of the contact will limit the current through the device Set: The voltage must be high enough to ensure that the alloy will switch into a low impedance state. An intermediate current level will heat the material but not melt it Reset: The voltage must be high enough to ensure that the alloy will switch into a low impedance state with sufficient current to heat a portion of the material above its melting temperature. When the current is removed, the small volume of material that has melted will rapidly quench into the amorphous state 22 Phase Change Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Schematic configuration: SiO2 Chalcogenide SiO2 via Thin Contact SiO2 Si The bottom electrode contacts the chalcogenide alloy material, forming a ringshaped contact area The chalcogenide alloy is deposited in the highly conductive crystalline phase The region where phase transition occurs is limited to the chalcogenide material immediately adjacent to the lower electrode This reduction in the volume of material being melted reduces the power requirement sufficiently to allow a minimum-feature-size MOS transistor to easily control the device 23 Phase Change Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Scaling of devices: Main scaling limitation of a memory device based on a phase change alloy is the minimum amount of material that can reliably undergo a phase transition Power needed to operate the memory goes down dramatically as the device size is decreased Quenching time is roughly proportional to the device size as well Advantages: Non volatile memory . Since crystallization energy is > 3.4 eV it cant be provided at room temperature Disadvantages: Proximity Disturbances Stuck Cells: Fast read and write cycles Low voltage and moderate energy consumption. 24 Phase Change Memory - Over heating of cells reduces cycling capability as cells are “stuck in Set- State” - High cycle failure leading to cell “stuck in reset state” because of open circuit at contact region Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What is it? Programmable Metallization Cell (PMC) memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolyte Use a little-known feature of some amorphous materials that they can incorporate relatively large amounts of metal and behave as solid electrolytes Electrochemistry: Oxidation as the losing of electrons and reduction as the gaining of electrons Accompany each other in redox reaction Example: - Reduction Cu2+ + 2e− → Cu (E = +0.34 V) - Oxidation Zn → Zn2+ + 2e− (E = −0.76 V) 25 Programmable Metallization Cell Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Schematic configuration: The electrodes are separated by a dielectric and a via in this layer defines the electrolyte area that contacts the bottom electrode Good solid electrolytes contain large numbers of highly mobile positively charged metal ions The backbone material separating these conducting regions is a good dielectric so the resistivity of the electrolyte is high As the high resistivity provides a high off resistance and the abundance of mobile ions is critical for rapid and stable resistance lowering Charge neutrality Using Ag or Cu deposits for ease of oxidation 26 Programmable Metallization Cell Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Working & principle: An oxidizable metal layer and an inert electrode formed in contact with the electrolyte film creates a device in which information is stored via electrical changes caused by the oxidation of the metal electrode and reduction of metal ions in the electrolyte Change of state (set and reset states): Aapplied bias as low as a few hundred mV and can result in a resistance change of many orders of magnitude within a few tens of nanoseconds even for currents in the μA range Reverse bias of the same magnitude will reverse the process until the electrodeposited metal has been removed, thereby erasing the device Information is retained via metal atom electrodeposition rather than charge storage 27 Programmable Metallization Cell Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Characteristics: Applied voltage of a few hundred mV will reduce ions to form an electro deposit of metal atoms at the cathode and inject ions into the electrolyte via oxidation at the anode The apparent rise in resistance following switching is caused by the current limit (compliance) control in the measurement instrument V-R characteristics Hysterisis Reduced Threshold on the I-V characteristics: Once electro deposition is initiated, the threshold for further electro deposition is decreased. This is evident by the presence of a lower voltage, in this case 220 mV, at which the current drops below compliance on the negative-going sweep V-I characteristics of PMC 28 Programmable Metallization Cell Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Advantages: Information is retained via metal atom electro deposition rather than charge storage, PMC memory has excellent retention characteristics. Do not readily tolerate Non volatile Electro deposition of metal in the electrolyte cannot be sustained if the voltage across the structure drops below that necessary to overcome the electrochemical potential or if the supply of oxidizable metal becomes exhausted Excellent switching characteristics The write threshold decreases with increasing temperature Switching may be achieved using low voltage 50 ns pulses Ag-doped materials will survive backend-of-line processing to 430 °C 29 Disadvantages: processing conditions much beyond 200 Celsius for selenide type. Higher for sulphides Programmable Metallization Cell Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What is it? The resistive switching phenomenon observed in organic semiconductor layers containing granular metal particles conforms to a charge storage mechanism. The space-charge field due to the stored charge inhibits further charge injection from the electrodes The equilibrium current-voltage curve is N shaped and the low and high resistance states are obtained by applying voltage close to the local maximum and minimum Schematic configuration: Device proposed is a sandwich structure consisting of three layers between top and bottom metal electrodes 3 layers are, respectively, the organic semiconductor, the metal, and the organic semiconductor, specifically AIDCN/Al/AIDCN Metal layer actually consists of discrete particles, and is therefore electrically discontinuous Specifically, here we use aluminum tris~8hydroxyquinoline (Alq3) as the semiconducting medium and granular aluminum for the charge-trapping sites The electrodes are also aluminum 30 Bi-stable Organic Memory Devices Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Working & principle: When the device is in the low resistance ON state, and the voltage is ramped up from zero, an ‘‘N-shaped’’ I-V curve is obtained If a voltage near Vmin is applied and then rapidly set back to 0 V, the device is left in its high-resistance OFF state When the device is in the OFF state, and the voltage is ramped up from zero, the current remains low until a threshold is reached, at which the high-current ON state is established The threshold voltage (Vth) is comparable to, but slightly less than, Vmax 31 Bi-stable Organic Memory Devices Indian Institute of Technology, Guwahati Indo German Winter Academy 06 32 The ON state is obtained by setting the voltage close to Vmax and above Vth , then reducing it to zero Intermediate states, i.e., those between the ON and OFF resistance values, can be obtained by setting the voltage between Vmax and Vmin in the NDR(negative differential resistance) region The region of bistability is obtained for voltages below the threshold (Vth +2.7 V) Set State: - Voltage is ramped from zero in the OFF state the current increases rapidly at the threshold voltage, and then follows an N shape. By sweeping the voltage back towards zero, the current follows the upper curve and the device is set in its ON state and it will stay in that state unless voltage between Vmin and Vmax is applied Reset state: - Set the device at a certain voltage in the NDR region and returning rapidly to zero Bi-stable Organic Memory Devices Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Principle: Variety of different materials and concepts all of which using individual molecules as building blocks for memory cells storing bit information in the space of an atom or a molecule Create a monolayer (ML) film consisting of a large number of functional molecules and thereafter contacting these films by depositing an electrode layer on top of it Techniques used: Rapid reversible conductance switching of molecules Self assembled monolayers of these molecules and embedding them into an Au/molecular ML/Au electrode structure a fast and reversible resistance switching Single time programmability Problems faced: Finding of adequate deposition methods Thermodynamic stability of the different molecular states and the reaction kinetics have to be studied Formation of a well defined metallic contact to the molecules or molecular arrangements in order allow a reliable reading and writing 33 The Ultimate : Molecular Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 “Punch card”: Storing a terabit of data on a chip no bigger than a postage stamp has been developed by researchers at IBM ”Millipede” chip, created by a team in Zurich, Switzerland, stores single bits of data in the form of tiny indentations The indentations are made in the surface of the chip using tiny "spikes" or tips on the end of pivoting arms. These same spikes are used to write, read and erase data on the chip Atomic memory: Scattering gold atoms on a silicon wafer caused the silicon atoms to assemble into tracks exactly five atoms wide Works well at very low temperatures with loosely-bound atoms, but not at room temperature Writing and Reading from each atom is very slow at present 34 “Punch Card” and Atomic Memory Indian Institute of Technology, Guwahati Indo German Winter Academy 06 What are memory devices? Development cycle Requirements of future devices Some materials that can be used in the future Summary 35 An Overview Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Summary: ¾ The present: Nonvolatile memories are based on charge storage Aim is to either realize a memory that can be operated like a DRAM or SRAM and additionally exhibits non volatility, or to realize a considerably higher density of nonvolatile memories than the currently available ones ¾ The future devices: 36 Inorganic materials are simplest to integrate into an existing CMOS process. (FeRAM already available in market till 256 Kb and MRAM of 1Mb is in the making) On the other hand the phase change memory concept has a number of open questions with respect to the stability of the electrode/chalcogenide interface as well as the thermal isolation between neighboring bits For molecular memory fundamental fabrication and integration issues will have to be solved before we can expect first products Conclusion Indian Institute of Technology, Guwahati Indo German Winter Academy 06 Indian Institute of Technology, Guwahati 37
