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MASTERS OF MEMORY’S:
ABSTARCT:
Today’s state of art microprocessor should not be thought of as logic chips
with embedded memory rather should be called as memory chips with
embedded logic. Present on chip memory takes 50 percent of the available
area of any respectable microprocessor. Recently world has seen the densest
and cheapest embedded memory technology in the world. It’s called ZRAM, for zero capacitor dynamic random access memory. Basically it
doesn’t require any new material or extra processing steps in the fabrication
process. Each memory cell is just a single transistor. Conventional on chip
memory consisted of 6 transistors per memory cell.
So one can fit 5
megabytes of conventional memory in the same memory space as the
conventional on-chip memory.
Z-RAM is a technology that straddles two great industries ever more on-chip
memory and transistors that operate faster and consume less power. Adding
the speed of SRAM to DRAM and removing the capacitor one gets Z-RAM.
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MASTERS OF MEMORY’S:
1. INTRODUCTION
Today's system-on-a-chip (SoC) designers face a myriad of challenges, not the least of
which is shrinking the die size when memory dominates chip area and cost. And with
each subsequent generation of silicon, that domination is steadily increasing. The reason
for this is simple. As processors continue to get faster, main memory grows larger. In
fact, with each succeeding generation, main memory access takes longer in terms of
processor cycles. Fig. 1 shows how embedded memory accounts for more than half die
area of typical microprocessors and SoCs and it will soon overwhelm the silicon devoted
to logic.
Fig. 1: Semiconductor Industry Association (SIA), and the International Technology
Roadmap for Semiconductors (ITRS 2000).
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MASTERS OF MEMORY’S:
With memory latency closely tied to overall system performance, it’s easy to see how the
designer’s choice of memory technology can have a dramatic impact not only on system
performance, but on overall cost as well. SoC designers are now being forced to find
alternate options to some of the more common types of embedded memory.
So what are the memory choices available to today’s SoC designer? SRAM embedded
memory traditionally has been the designer’s option of choice for fast memory. Yet its
speed comes at the expense of both cost and silicon area. Other alternatives such as
embedded DRAM or zero-capacitor DRAM (Z-RAM) technology have the benefit of
lower costs, though they have higher latency and are typically used further from the
processor.
In spite of this, using more memory closer to the processor can generate a performance
advantage, even if the raw memory latency is higher. Because of their potential for both
lower cost and higher performance, alternative memories like DRAM and Z-RAM are
now replacing SRAM in what was traditionally considered sacred SRAM territory.
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MASTERS OF MEMORY’S:
2. TRADITIONAL MEMORY TYPES
2.1. Static random access memory (SRAM) is a type of semiconductor memory.
The word "static" indicates that the memory retains its contents as long as power remains
applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed
Random access means that locations in the memory can be written to or read from in any
order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters.
This storage cell has two stable states which are used to denote 0 and 1. Two additional
access transistors serve to control the access to a storage cell during read and write
operations. It thus typically takes six MOSFETs to store one memory bit.
Access to the cell is enabled by the word line (WL in figure) which controls the two
access transistors M5 and M6 which, in turn, control whether the cell should be connected
to be bit lines: BL and
. They are used to transfer data for both read and write
operations. While it's not strictly necessary to have two bit lines, both the signal and its
inverse are typically provided since it improves noise margins.
During read accesses, the bit lines are actively driven high and low by the inverters in the
SRAM cell. This improves SRAM speed compared to DRAMs—in a DRAM, the bit line
is connected to storage capacitors and charge sharing causes the bitline to swing upwards
or downwards. The symmetric structure of SRAMs also allows for differential signaling,
which makes small voltage swings more easily detectable. Another difference with
DRAM that contributes to making SRAM faster is that commercial chips accept all
address bits at a time. By comparison, commodity DRAMs have the address multiplexed
in two halves, i.e. higher bits followed by lower bits, over the same package pins in order
to keep their size and cost down.
The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.
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MASTERS OF MEMORY’S:
Fig.2: A six-transistor CMOS SRAM cell.
SRAM operation
A SRAM cell has three different states it can be in: standby where the circuit is idle,
reading when the data has been requested and writing when updating the contents. The
three different states work as follows:
Standby
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from
the bit lines. The two cross coupled inverters formed by M1- M4 will continue to reinforce
each other as long as they are disconnected from the outside world.
Reading
Assume that the content of the memory is a 1, stored at Q. The read cycle is started by
precharging both the bit lines to a logical 1, then asserting the word line WL, enabling
both the access transistors. The second step occurs when the values stored in Q and Q’
are transferred to the bit lines by leaving BL at its precharged value and discharging
through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit
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MASTERS OF MEMORY’S:
line towards VDD, a logical 1. If the content of the memory was a 0, the opposite would
happen and
would be pulled towards 1 and BL towards 0.
Writing
The start of a write cycle begins by applying the value to be written to the bit lines. If we
wish to write a 0, we would apply a 0 to the bit lines, i.e. setting
to 1 and BL to 0.
This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to
change state. A 1 is written by inverting the values of the bit lines. WL is then asserted
and the value that is to be stored is latched in. Note that the reason this works is that the
bit line input-drivers are designed to be much stronger than the relatively weak transistors
in the cell itself, so that they can easily override the previous state of the cross-coupled
inverters. Careful sizing of the transistors in a SRAM cell is needed to ensure proper
operation.
2.2. Dynamic random access memory (DRAM) is a type of random access
memory that stores each bit of data in a separate capacitor within an integrated circuit.
Since real capacitors leak charge, the information eventually fades unless the capacitor
charge is refreshed periodically. Because of this refresh requirement, it is a dynamic
memory as opposed to SRAM and other static memory. Its advantage over SRAM is its
structural simplicity: only one transistor and a capacitor are required per bit, compared to
six transistors in SRAM. This allows DRAM to reach very high density. Since DRAM
loses its data when the power supply is removed, it is in the class of volatile memory
devices.
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MASTERS OF MEMORY’S:
Fig.3: Principle of operation of DRAM
for read, for simple 4 by 4 array.
Fig.4: Principle of operation of DRAM write,
Simple 4 by 4 array.
Principle of operation
DRAM is usually arranged in a square array of one capacitor and transistor per cell. The
illustrations above show a simple example with only 4 by 4 cells (modern DRAM can be
thousands of cells in length/width). A read operation proceeds as follows: the row of the
selected cell is activated, turning on the transistors and connecting the capacitors of that
row to the sense lines. The sense lines lead to the sense amplifiers, which distinguish
signals that represent a stored 0 or 1. The amplified value from the appropriate column is
then selected and connected to the output. At the end of a read cycle, the row values must
be restored to the capacitors, which were depleted during the read. A write operation is
done by activating the row and connecting the values to be written to the sense lines,
which charges the capacitors to the desired values. During a write to a particular cell, the
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MASTERS OF MEMORY’S:
entire row is read out, one value changed, and then the entire row is written back in, as
illustrated in the figure to the right.
Typically, manufacturers specify that each row should be refreshed every 64 ms or less,
according to the JEDEC standard. Refresh logic is commonly used with DRAMs to
automate the periodic refresh. This makes the circuit more complicated, but this
drawback is usually outweighed by the fact that DRAM is much cheaper and of greater
capacity than SRAM.
2.3 eDRAM stands for "embedded DRAM", a capacitor-based dynamic random access
memory usually integrated on the same die or in the same package as the main ASIC or
processor, as opposed to external DRAM modules and transistor-based SRAM typically
used for caches.
Embedding permits much wider buses and higher operation speeds, and due to much
higher density of DRAM in comparison to SRAM, larger amounts of memory can
potentially be used. However, the difference in manufacturing processes makes on-die
integration difficult, so several dies have to be packaged in one chip, raising costs. The
latest developments overcome this limitation by using standard CMOS process to
manufacture eDRAM, as in 1T-SRAM.
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MASTERS OF MEMORY’S:
3. BASIC FUNDAMENTALS
In present System on Chip (SoC) applications, memory already dominates silicon area is
steadily increasing with each generation. On chip memory already takes up 50 percent
area of any respectable microprocessor. It’s expected to occupy a whooping 83 percent
of the area of high-end processors made in 2008 and 90 percent by 2010. And that’s no
joke for designers who will be hard-pressed to cram in hundreds of megabytes of memory
without making their chips any bigger. The most common types of embedded memory in
current use are 1T/1C DRAM and 6T SRAM. As CMOS technology achieves sub 100
nm geometries, new memory devices are being considered for DRAM/SRAM
replacement. However most of these new memories rely on the integration of exotic
materials into a baseline CMOS process and require relatively large cells. Innovative
Silicon has developed a true capacitor-less, single transistor DRAM - named Z-RAM
for Zero Capacitor DRAM by harnessing the floating body effect of Silicon on
Insulator (SOI) devices. This technology is capable of achieving twice the memory
density of existing embedded DRAM technology and five times that of SRAM yet
requires no special materials or extra mask/process steps. That’s extremely important
to chip makers, who are reluctant to add any new materials to their already complex and
delicate processes, for fear of how the additions may erode the proportion of working
chips that emerge from their fabrication units. Z-RAM if it grabs even a little change the
on-chip memory market, it will design and quickly overwhelm the market.
3.1 SILICON-ON-INSULATOR (SOI)
A SOI wafer differs from an ordinary silicon wafer in that it has a very thin layer of
insulating silicon dioxide buried a few hundred nanometers or less below the surface.
That layer of insulation cuts the transistors off from the vast bulk of the wafer-which, in
turn, limits the amount of charge the transistor must move in order to switch on or off.
The result is to speed up the circuits by as much as 30 percent. As transistors shrink
they increasingly leak current, even they are turned off. But the insulation in SOI
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MASTERS OF MEMORY’S:
wafers blocks a major power that transistors draw by 30 percent when they are
switching and 50 percent to 90 percent when they are not.
But those advantages come at a cost. A 200 millimeter SOI wafer sells for about $275,
while a plain silicon wafer of the same size goes for $65. But still all things being equal
SOI chip will cost almost 9 percent more than the bulk-silicon chip.
Fig.5: SOI die-cost reduction from bulk CMOS.
But all things are no longer equal. The SOI wafer lets one to substitute Z-RAM for the
chip’s conventional embedded memory. SOI ’s insulating layer is a key to storing the bit
in Z-RAM, so one cannot build it on a plain wafer. Innovative silicon estimates that if the
conventional memory takes up half the area, replacing it with Z-RAM would let
designers shrink a chip to 72 square millimeters from 120 square millimeters. That would
boost the number of chips per wafer and cut the final cost almost in half. Suddenly, SOI
looks like a bargain.
Fig. 6: Cell layout of SOI standard cells library for 90nm process
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MASTERS OF MEMORY’S:
SOI or not, microprocessors makers are compelled to continue boosting the amount of
on-chip memory in their designs for simple reason that they cannot get the performance
they need any other way. The other means of increasing processing speeds and putting
more processor cores on a chip are effective only if those processor cores have rapid
access of data.
Table 1: Bulk CMOS vs. SOI.
Table 2: Bulk CMOS vs. SOI for 90nm wafer.
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MASTERS OF MEMORY’S:
3.2 Z-RAM TAKES THE SPOTLIGHT
Z-RAM, a new player in this market, is perhaps the less well known of the two
alternative memory options. As a capacitor-less, single-transistor DRAM technology that
exploits the intrinsic floating-body effect of silicon-on-insulator (SOI) devices, its cell
size can be half the size of an embedded DRAM transistor plus capacitor cell. Also, it
is less than a fifth the size of a six-transistor SRAM equivalent.
Z-RAM’s small cell size results in higher memory density, allowing more memory in
the same silicon real estate or the same amount of memory in proportionally less space.
In addition to reducing cost, the small cell size reduces the probability of memory cell
alpha particle hits, which improves soft error rate (SER) performance up to 10 times
over SRAM.
The savings don’t end there. Relative to embedded DRAM, the Z-RAM cell requires no
special materials or extra mask/ process steps. And because Z-RAM doesn't require a
capacitor cell, the additional process complexity dictated by an embedded DRAM isn't
required. The result is lower processing costs, faster manufacturing cycle times, and
higher yields. That’s the beauty of Z-RAM: no exotic semiconductors, no oddly
structured parts, and no experimental insulators. Each memory cell is just a single
transistor. That’s it. Transistors are the most studied device in the world. To make it
work as a memory, we have to find something different. That’s possible by temporarily
storing a bit as charge inside the body of a transistor made on a silicon-on-insulator (SOI)
semiconductor wafer.
Fig.7: Z-RAM 5x denser than SRAM and 2x denser than eDRAM.
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MASTERS OF MEMORY’S:
Furthermore, Z-RAM’s simple cell layout and process improves scalability and sets the
stage for the realization of even greater benefits as smaller technology nodes evolve. ZRAM technology also features reduced standby power, which can be orders of
magnitude lower than SRAM. Depending on the application and array configurations, ZRAM standby power can be as low as 10 µA/Mbit of memory.
3.3 NO-CAPACITOR DRAM DOUBLES MEMORY DENSITY
A new type of memory is poised to replace bulk CMOS DRAM and SRAM, promising to
save space and money by eliminating capacitors from DRAM.
Innovative Silicon has developed a capacitor-less technology based on SOI (silicon on
insulator)
transistors.
Called ZRAM (zero capacitance DRAM), the technology breakthrough is claimed to
have doubled the memory density of DRAM, and be 5x denser than SRAM, since it
consists only of a single SOI transistor, and not a combination of transistor and capacitor
as
in
normal
DRAM.
ZRAM is based on SOI processing, the process that has already replaced CMOS for
some SoC manufacturers. More importantly, the adoption rate of SOI is on the increase:
a Gartner-Dataquest study predicts a CAGR of 41.2% for SOI wafers between 2002
and 2008, and expects middle to low-end applications with high volume to begin
switching to SOI this year. ISi says its ZRAM can be fabricated using the standard silicon
on insulator process, and needs no exotic materials or extra mask steps.
ISi CEO, Mark-Eric Jones explains: "Embedded memory occupies at least 70% of the die
area of today's complex SoCs. The combination of our ZRAM memory - which requires
less than half the die area required for traditional embedded DRAM, without the
additional process steps required to embed traditional DRAM and existing SOI
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MASTERS OF MEMORY’S:
processing, which additionally offers large performance and power benefits, means that
not only are ZRAM SoCs higher performance and lower power, they are also much
cheaper
than
SoCs
based
on
bulk
CMOS
wafers."
He continues: "By reversing the traditional economics and making SOI wafers a lower
cost solution than bulk silicon for most SoCs and microprocessors, we expect our ZRAM
memory technology to accelerate the anticipated industry switch from bulk silicon to
SOI. As a result, designers of cost-sensitive products will also be able to take advantage
of
the
increased
performance
and
lower
power
consumption
of
SOI."
Furthermore, ISi claims that substituting SRAM for ZRAM (which is five times more
memory-dense) can reduce die costs by a staggering 55%. With processed SOI wafers
attracting a price premium of, typically, 15% over bulk CMOS, the cost savings overall
could
be
as
much
as
40%.
The standard form of embedded memory used on microprocessor chips is static random
access memory. Designers incorporate the SRAM as blocks of memory called caches.
The level 1 cache, or L1, is optimized for speed and located near the processor, it stores
the most frequently needed few kilobytes of data, so when the processor needs data, it
looks there first. Then it checks in a larger but more distant and somewhat slower cache,
called L2, which is usually about 16MB for next-generation chips.
If the data it requires are in neither of those caches, L3, in which to look. Failing that,
it’s off to the computer’s main memory, which consists of hundreds of megabytes of
dynamic random access memory (DRAM), or as a last resort, the hard drive.
ZRAM doesn’t have to be better than traditional embedded SRAM; it also has to be
better than DRAM, a memory technology that has been slowly winning a place on logic
chips. Though slower than SRAM, DRAM consumes about one-fifth as much power
and is about four times as dense. DRAM is so much denser than SRAM because it
consists of a single transistor and a capacitor instead of SRAM’s six transistors.
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MASTERS OF MEMORY’S:
But the capacitor is the problem. Moore’s law doesn’t apply to it, so it stays big while
transistors all around it continue their mad descent into infinitesimal. The capacitor
can’t shrink further because it needs to stay large to store large amount of charge.
The growing mismatch between the size of transistors and size of capacitors has led to
strange looking arrangements, such as capacitors built as narrow trenches having
depth many times greater than chip’s transistors. The capacitor trench makes the bitcell much taller than its width and poses a problem for advanced fabrication processes.
Another configuration has relatively enormous fin-shaped capacitors built above the
silicon in the area that usually holds the chip’s wiring. Both arrangements are too
expensive to put into many logic chips, requiring several extra manufacturing steps.
Nevertheless, DRAM is a well-understood technology, and it is embedded in some
memory-intensive chips such as IBM’s Blue-gene processor.
Fig.8: conventional embedded DRAM requires a deep trench capacitor structure with a
transistor for each cell.
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MASTERS OF MEMORY’S:
Fig. 9: ZRAM requires only one
transistor per bit cell.
Fig 10: Stacked structure of DRAM.
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MASTERS OF MEMORY’S:
4. FLOATING BODY EFFECT
Add the speed of SRAM
to DRAM and remove the capacitor and you get Z-RAM. To
turn a capacitor into a memory bit-cell, ISi has harnessed the floating body effect of
silicon on insulator devices. The term comes from the fact that the insulation layer in an
SOI wafer electrically separates the body of the transistors from the rest of the silicon,
letting its voltage vary, or “float’. This effect, which is usually considered to be parasitic,
results in a charge developing in the FET device body. In ZRAM, the charge is controlled
and enhanced, leading to a device which can store "1's" and "0's" effectively.
When a transistors is “on” electric current runs from the transistor’s source to its
drain. By the time those accelerating electrons get to the boundary of the drain, they are
moving so quickly that some will whack into silicon atoms energetically enough to ionize
them. This impact ionization, it’s called, generates pairs of electrons exit the transistors
through the drain, which is connected to a positive voltage. But the holes are repelled by
the drain. In a bulk silicon crystal, this extra positive charge would harmlessly drift out
into the silicon, but in SOI, the insulating layer traps it in the transistors, forming a body
of charge that floats above the transistors. A transistor with such a floating charge is
basically a Z-RAM cell storing a 1. To erase the 1 and store a 0, increase the voltage on
the transistor’s gate. That pushes the holes out of the transistors through the source
electrode and even leaves a slight negative charge behind.
An excess of positive of negative charge in the body of an N or PMOS device is used to
store the data .For an NMOS device, an excess of positive charge in the channel
decreases the threshold voltage of the device, which increases the channel current Ids,
defining
the
state
"1".
An excess of negative charge is obtained by removing the holes present, which decreases
Ids, defining the state "0". The information is read by applying a small pulse to the
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MASTERS OF MEMORY’S:
selected bit-cell transistor and comparing the Ids of the selected cell to the current of a
reference cell using a sense amplifier.
Fig 11: NMOS Floating body charging to write: a) the “1” b) the “0”.
Reading a bit from a Z-RAM cell is simple. A transistor is turned on and measures the
amount of current flowing through it. In the field effect transistor, turning the device on
involves applying a voltage to the transistor’s gate. The voltage force opens a conductive
channel between the source and the drain, allowing current to flow. More current will
flow through a cell with a 1 than through one with a 0, because the floating body charge
that makes up the bit exerts its own force on the channel and acts almost like a second
gate, amplifying the effect of the real gate. By comparing the two voltages with a
reference one can distinguish between a 0 and 1.
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MASTERS OF MEMORY’S:
Fig 12: Reading current from ZRAM bit-cell.
In the first test devices the difference between 1 and 0 was just 3 to 15microamps per
micrometer
of
channel
width.
ZRAM technology does not require designers to compromise on speed or power: read
and write operations in under 3ns have already been demonstrated on silicon; while ISi's
low power ZRAM option promises significant power savings compared to traditional
embedded
DRAM.
Scalability should not pose a problem, either. A main problem with the evolution of
DRAM is the lack of scalability of the capacitors; so ZRAM, without any capacitors, is
dependent only on the properties of the much more scaleable transistor. ISi has taped out
several 90nm megabit designs and demonstrated the technology's bit-cell scalability at
the
It
45nm
is
envisaged
by
ISi
that
ZRAM
node.
will
easily
scale
to
22nm.
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MASTERS OF MEMORY’S:
5. ADVANTAGES
5.1. Reducing die size or increasing memory density with reduced cost:
The massive increase in memory density does not come at a price penalty even though, in
the past, SOI has represented a cost premium over bulk silicon. If we assume that
memory occupies around 70 percent the die area using traditional embedded SRAM, then
we can see that by substituting Z-RAM which is five times as dense, die costs can be
reduced by as much as 55%.with processed SOI wafers typically attracting a price
premium of around 15% over their bulk CMOS counterparts, by using a combination of
Z-RAM technology and processing, cost savings could amount to around 40%.
Fig.13: Embedded memory density and economics.
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MASTERS OF MEMORY’S:
Fig.14: Memory density vs. process geometry.
5.2. Less power consumption: Demonstrated ~ 30 percent less power consumption
than eDRAM.
Fig.15: Power consumption vs. supply voltage.
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MASTERS OF MEMORY’S:
5.3. No extra processing steps: That’s extremely important to chip makers, who are
reluctant to add any new materials to their already complex and delicate processes, for
fear of how the additions may erode the proportion of working chips that emerge from
their fabrication units. Z-RAM if it grabs even a little change the on-chip memory
market, it will design and quickly overwhelm the market.
5.4. Based on SOI so better performance: Compared to bulk CMOS SOI-based
chips have 20-35 %( frequency) performance gain or 2-3x lower power at the same
frequency. This is equivalent to about 2 years of progress in bulk CMOS technology.
Fig.16: Performance vs. year qualified.
5.5. Greater speed: The key drivers for electronic circuitry are density, speed and
power. Z-RAM can be optimized for any of these three parameters. Demonstrated <3ns
read
and
write
on
silicon
material.
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MASTERS OF MEMORY’S:
As speed is dependent mainly on the capacitance of the bit line, for fast access times the
bit line can be shortened to deliver up to 400MHz array speed at 65nm. For low power
operation, although a shorter bit line does reduce power the effect is not that great since
the change in bit line voltage is small. However, by reducing the Word Line length and
hence the Word Line capacitance, active power levels of only 10Wµ/MHz at 65nm are
achievable.
To achieve the ultimate in array density (>5Mbit/mm²), longer Word Lines and Bit Lines
are required. However this is obviously at the expense of access time and power.
Z-RAM memory technology was co-invented by Pierre Fazan and Serguei Okhonin, who
also co-founded Innovative Silicon Inc. (ISi) to commercialize the technology.
Fig.17: Z-RAM performance metrics.
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MASTERS OF MEMORY’S:
5.6. Z-RAM fulfills wide range of product requirements through
different architectures.

Asynchronous

Synchronous

Pipelined

Early write

Late write
5.7. Ultra-high density reduces wire lengths

Reduced word line, bit-cell and bit line capacitance

40% less capacitance than eDRAM

Promises continued improvements as geometries shrink
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MASTERS OF MEMORY’S:
6. COMPARISION
Table 3: Memory technology comparison.
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MASTERS OF MEMORY’S:
7. FUTURE OF TECHNOLOGY
TECHNOLOGY ROADMAP
Innovative Silicon proprietary Z-RAM memory cell is highly scalable, and has been
demonstrated on Partially Depleted (PD), Fully Depleted (FD) and on FinFET SOI
devices. The figure below summarizes Innovative Silicon technology roadmap.
Fig.18: Die size vs. technology years.
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MASTERS OF MEMORY’S:
8. Z-RAM GENERATION 2
Ideal for both high-performance and battery-powered applications
Innovative Silicon Inc. (ISi), the developer of Z-RAM high density memory intellectual
property (IP announced availability of its second generation Z-RAM technology, named
Z-RAM Gen2, which delivers significant performance improvements with greatly
reduced power consumption. Simultaneously, the company is announcing that
microprocessor giant Advanced Micro Devices, Inc. (NYSE:AMD), has contracted to
purchase a license for Z-RAM Gen2, having contracted to purchase a license to the
previous generation technology in December of last year.
Commented Craig Sander, corporate vice president, technology development at AMD:
“We are very excited about Z-RAM Gen2. The combination of density, power, and
performance coupled with its ability to work with our standard manufacturing processes
makes it an extremely attractive option for use in our future microprocessors.”
Z-RAM technologies achieve world-leading density and performance by using a single
transistor as a memory bitcell, which is made possible by harnessing the Floating Body
Effect found in circuits fabricated using SOI (silicon-on-insulator) wafers. Moreover,
since Z-RAM takes advantage of a naturally-occurring SOI effect, Z-RAM works on SOI
logic processes without requiring exotic process changes to build capacitors or other
devices.
Z-RAM Gen2, invented by ISi’s chief scientist, Dr Serguei Okhonin, stores significantly
more charge in the memory bitcell. The additional charge provides an order-of-magnitude
improvement in both cell margin—the difference between a “1” and a “0”—and in data
retention time. The higher margin also provides much faster data read and write times,
yet reduces power consumption significantly. As a result, Z-RAM Gen2 significantly
broadens the range of applications that can take advantage of Z-RAM’s density to both
high-performance applications requiring greater than 1GHz operation (when pipelined),
and low-power applications that require long-battery life.
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MASTERS OF MEMORY’S:
“Our Z-RAM Gen2 technology is a real breakthrough,” stated Mark-Eric Jones, president
and CEO of ISi. “We have seen no other technology that is remotely similar to it. Z-RAM
was already the densest memory technology in the world, and with Z-RAM Gen2, it is
now more than twice as fast and cuts memory read power by 75 percent and memory
writes power by a massive 90 percent.”
“Z-RAM Gen2 also exhibits enormous flexibility,” added Jeff Lewis, vice president of
marketing. “The technology can be ‘tuned’ for a very wide range of speed/power
operating points, from ultra-low power to very high performance.” Z-RAM Gen2
achieves compelling specifications in a 65nm fabrication process:

Ultra-high density: greater than 5Mbits per mm2 at 65nm, and greater than
10Mbits per mm2 at 45nm (1.4x – 2x denser than eDRAM and 5x-6x denser than
SRAM)

High performance random array access: greater than 400MHz (when optimized
for performance)

Very low active power consumption: under 10µW/MHz (when optimized for lowpower)
Z-RAM Gen2 technology has been fabricated and validated as a complete memory at
90nm, and the bitcell has been validated on an additional five fabrication processes. Test
chips are currently in fabrication at both the 65nm and 45nm process nodes. The
company has demonstrated bitcell operation on smaller geometries and on the emerging
multi-gate/FinFET devices and anticipates no difficulty in scaling to sub45nm process
technologies.
Z-RAM Gen2 technology is available today from ISi. The technology can be procured as
either a technology license, where ISi trains its customers so that they can build their own
Z-RAM memory macros, or as an instance license, where ISi provides a memory instance
in a specific process and designed for a specific application.
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MASTERS OF MEMORY’S:
9. APPLICATIONS
In theory, memory manufacturers could license Z-RAM to make DRAM chips twice as
dense as conventional DRAM. However, conventional DRAM processes don’t’ use SOI,
so adopting Z-RAM would require memory manufacturers to expensively retool their
fabs. Z-RAM isn’t fats enough to replace SRAM in L1 caches of microprocessors, but L2
and L3 caches could use it. Thanks to the transistor’s gain effect, Z-RAM retains its state
for about the same amount of time as eDRAM, even though a Z-RAM cell has much less
capacitance. As a result, the refresh rate of Z-RAM is about the same as for eDRAM, but
dynamic power is 30% lower.
After three years of development building on a dozen years of theoretical work, Z-RAM
is finally moving out of the lab. Innovative silicon has produced multimegabit test chips
using 90nm SOI processes at Freescale Semiconductor and TSMC. Additional test chips
are now being fabricated at 65nm.
Fig.19: a one-transistor Z-RAM FinFET bit-cell fabricated for test purpose
Some of the early killer applications include:

Networking

PC peripherals

Computer graphics
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MASTERS OF MEMORY’S:

Cell phones consumer electronics

Merging of consumer & computer worlds

Living-room battle

Nomadic applications

Performance oriented

Processor architecture

Clock frequency increase

Power dissipation issue

Fig. 20: Applications of Z-RAM.
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MASTERS OF MEMORY’S:
10. CONCLUSION
10.1 FUTURE-PROOFING
One of the biggest problems facing complex IC and SOI designers is the suitability or
otherwise of a technology’s scalability as process technologies move to smaller nodes.
Embedded DRAM technologies that require a capacitor element are particularly difficult
to scale, as capacitor requires either highly complex stacked or trench designs with major
on the manufacturing process to minimize chip area.
As no capacitor is required, the ZRAM cell readily is scaled as far as the transistor. ISi
has taped out several 90nm megabit designs and demonstrated the technology’s bit-cell
scalability at the 45nm node. It is easily envisaged that ZRAM technology will scale well
to at least 22nm process node and ISi has already measured suitable characteristics in the
FinFET transistors that may well be used at that time.
10.2 MARKETS AND SUMMARY
The market for SoCs and microprocessors with embedded memory in 2005 is estimated
to be worth US$60bn. Applications include networking, PC peripherals, computer
graphics, cell phones and consumer electronics; in reality, any application that is cost,performance –or power-limited with a significant processing embedded memory
requirement will benefit from moving to ZRAM technology on SOI processing. ISi’s new
embedded memory addresses the market need for highly dense memory that will scale to
the process nodes that will be in use for at least 10 years – with no cost penalty, no extra
processing steps and using no exotic materials or physics.
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MASTERS OF MEMORY’S:
11. BIBLIOGRAPHY

“Soft Error Performance of Z-RAM Floating Body Memory” by Fisch, D.;
Beffa, R.; Bassin, C. at International SOI Conference, 2006 IEEE Oct. 2006
Page(s):111 – 112.

“Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on
FinFET
and
tri-gate
devices”
by
Bassin, C.; Fazan, P.; Xiong, W.; Cleavelin, C.R.; Schulz, T.; Schruefer, K.;
Gostkowski, M.; Patruno, P.; Maleville, C.; Nagoga, M.; Okhonin, S. at SOI
Conference, 2005. Proceedings. 2005 IEEE International 3-6 Oct. 2005
Page(s):203 - 204

“RealView Hardware Platforms Product Selector” by Javier Orensanz ,July 2006

“Innovative Silicon’s Tiny DRAM Cells Alter the Memory Equation” By Tom R.
Halfhill , 10/25/05-03

Z-RAM Zero capacitor Embedded Memory Technology addresses dual
requirements of die size and scalability by Dr. Pierre Fazan,CTO ISi.

Electronics design magazine.

www.spectrum.ieee.org

www.innovativesilicon.com

www.zram.com

www.wikipedia.com
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