Download Topic: High Performance Data Acquisition Systems Analog

Topic: High Performance Data Acquisition Systems
Analog Components: Analog to Digital Convertors
Figure 1 Generic High Performance Analog to Digital Convertor
When designing a high performance data acquisition system, often times design engineers will
actually encounter less than desired performance when the designed system is actually
undergoing test and characterization. The first place to begin in troubleshooting the
undesirable errors created within the system is at the analog to digital convertor. The subtleties
in the analog to digital convertor specifications often lead to sources of errors within the
system that are not intuitively obvious. For instance, when using a high resolution 14 bit analog
to digital convertor, the system level performance may actually measure significantly lower
performance than expected. A 14 Bit convertor should yield 214 bit resolution which is 1 part
out of 16,384 which is .0061% accuracy. But, just because an analog to digital convertor may
have a designated resolution of X number of bits, it does not necessarily translate into
accuracy! In fact, resolution and accuracy are actually only partially related functions in many
ways. Resolution is just that, the convertors ability to resolve the smallest level and is highly
related to the signal to noise ratio. However, resolution is not necessarily related to the full
scale of the convertor, which is connected more to the TOTAL integration of each and every
resolved step of the convertor. This leads to the overall integral linearity INL (and final accuracy)
of the analog to digital convertor. Keep in mind though, the design engineer needs to ensure
that the RSS’d (root-summed-squared) combined system values of noise and distortion leading
up to the input of the analog to digital convertor must be significantly below the performance
specifications of the ADC in order to let the ADC be the limiting error source. But remember,
although a 14 bit ADC may have a theoretical SNR (Signal to Noise ratio) of 86db, it can be quite
possible to have only 10-12 Bit accuracy in regards to SFDR (Spurious Free Dynamic Range)
which is connected to the overall integral linearity of the convertor which may not relate at all
to the stated resolution. Let’s take a look at why this can be the case:
As we have previously discussed, there are many errors introduced by the ADC that negatively
affect overall system level performance. But if the design assumes acceptable ADC
specifications in regards to conversion rate, power supply/dissipation, input range, offset and
gain errors (all over temperature variations), the place to scrutinize the ADC performance is in
the area of integral linearity of the device (INL). It is almost always a good idea to begin the
analysis and troubleshooting of any ADC device by reviewing its DC performance. A good rule of
thumb is all problems are inherently DC problems! Which means almost all AC problems can be
traced back to some kind of DC root issue. The AC performance of the ADC can never be better
than the DC performance. In this case, the INL of the ADC (which is a DC specification) can
never outperform the SFDR of the ADC over frequency. INL and SFDR are inherently
interconnected. The first place to start in understanding the INL of a particular ADC is at the
DNL (Differential Non-Linearity). The DNL of the device reveals the minimum verified resolution
of the device and tells how far any particular code is from its adjacent codes. The distance is
measured as a change in input voltage magnitude and then converted to LSB’s (see Figure 2a).
The device is then measured through every code transition (2n-1) and the input voltage
magnitude is then converted to LSB’s and worst case DNL is recorded for the device.
Figure 2a DNL: No Missing Codes
Figure 2b DNL: Missing One Code
Figure 2c DNL: Missing Multiple Codes
The key for good performance for an ADC is the desired specification to have “no missing
codes.” This means that, as the input voltage is swept over its full-scale range, all output code
combinations will appear at the ADC outputs. A DNL error of <+/-1 LSB guarantees no missing
codes. In Figures 2b, and 2c, there are two different DNL error values shown. With a DNL error
of -0.8 LSB (Figure 2a) the device is guaranteed to have no missing codes (fulfilling the
requirement that is necessary at <+/-1.0 LSB). With a value equal to -1 LSB (Figure 2b), the
device is not necessarily guaranteed to have no missing codes (in this case code “10” is missing.
With a DNL value of greater than -1 (-1.5 LSB in Figure 2c) the device inherently has missing
codes. Again, the DNL is of critical importance in regards to the resolution of the ADC. If the
device has missing codes (DNL>1 LSB) than the device no longer functions at its prescribed
resolution. One missing code would turn a 14 bit ADC convertor into 13 bit resolution
instantaneously. If the device has missing codes of (DNL>2LSB’s) than the subsequent
resolution of the ADC drops another bit (to 12 bit resolution) and so on. Keep in mind, the DNL
of a particular ADC can be degraded significantly due to improper power supply and grounding
configurations. Some code transitions that have all bits changing simultaneously can manifest
into significant ground bounces and the DNL errors at these levels can sometimes be several
LSB’s in magnitude.
Now, the one thing to keep in mind though, is the INL is simply the integral of the DNL errors.
Therefore, good INL will guarantee a good DNL result (but not necessarily the other way
around). INL error tells how far away from the ideal “linear” transfer function the device
deviates. For instance, an INL error of +/-2 LSB in a 14 bit system, means the maximum
nonlinearity error may be off by 2 parts out of 16,384 or .0122%. This is already twice the error
allowed for the accuracy that can be required when specifying a 14 bit ADC! Thus, a 1 LSB (or
better) part is required if the designer needs 14 bit accuracy. Often times designers will need to
specify an ADC which has a high bit resolution (that impacts DNL) simply to allow for a better
INL that will determine the overall system level accuracy. It is important to note also that
neither INL or DNL errors can be calibrated or corrected for easily, unlike gain and offset errors.
Again, when designing a high performance (and high frequency) data acquisition system, the
analog to digital convertor should be the ultimate limiting factor in overall system resolution,
accuracy, and noise. For instance, selecting resolution instantly defines the SNR of the system.
BUT it is also true that the overall linearity of the ADC will fundamentally set the precision and
accuracy of the system. Keep in mind, choosing the proper ADC, and correlating it’s DC
specifications to the key results that you desire the system to perform, will then set the limit of
most of your system level performance parameters.
Kai ge from CADEKA