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Introduction to Embedded Microcomputer Systems Mark II Aiken Relay Calculator Mark W. Welker ( From Jonathan W. Valvano) Lecture 5.1 Introduction to Embedded Microcomputer Systems Lecture 5.2 9S12C32 In the single chip operating mode, the 9S12C32 is a single chip complete microcomputer (microcontroller), where all its I/O ports are available. Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.3 3.2.2. Terminology w signed 8-bit or unsigned 8-bit n is a signed 8-bit -128 to +127 u is a unsigned 8-bit 0 to 255 W is a signed 16-bit or unsigned 16-bit N is a signed 16-bit -32787 to +32767 U is a unsigned 16-bit 0 to 65535 =[addr] an 8-bit read from addr ={addr} a 16-bit read from addr using "big endian" [addr]= an 8-bit write to addr {addr}= a 16-bit write to addr using "big endian" The label field optional starts in the first column used to identify the position in memory must choose a unique name for each label The opcode field specifies the microcomputer command to execute. could be pseudo op, which are instructions to the assembler The operand field specifies where to find the data to execute the instruction 0, 1, 2, or 3 operands Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.4 The comment field optional ignored by the computer makes it easier to understand explain how it works why design choices were made how to test it how to change it label here opcode ldaa operand 100 comment RegA=[$0064] http://www.ece.utexas.edu/~valvano/EE319K/S12CPUV2.pdf Object code $96 $64 instruction ldaa 100 comment RegA=[$0064] Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.5 3.2.3. Addressing modes Where to find the data? inherent no operand or implied operand immediate in the instruction itself direct or extended absolute address of the data relative where to go for branch instructions object $87 $86 24 $96 24 $B6 08 01 $20 FE op code Clra Ldaa Ldaa Ldaa Bra operand #36 36 $0801 $F000 comment A = 0 (inherent) A = $24 (immediate) A = [$0024] (direct) A = [$0801] (extended) relative addressing Table 3.2. Simple addressing modes. The memory maps 9S12C32 I/O $0000 to $03FF Ports AD, M, S, T 2K RAM $3800 to $3FFF 32K ROM $4000 to $7FFF $8000 to $FFFF I/O Ports 1K RAM MC68HC812A4 $0000 to $01FF A,B,C,D,E,F,H,J,S,T,AD $0800 to $0BFF 4K ROM $F000 to $FFFF Three good data sheets to have available 32 page CPU12 quick reference http://www.ece.utexas.edu/~valvano/EE319K/cpu12rg.pdf 458 page CPU12 programming reference http://www.ece.utexas.edu/~valvano/EE319K/S12CPUV2.pdf 548 page 9S12C32 data sheet http://www.ece.utexas.edu/~valvano/EE319K/MC9S12C128_V1.pdf Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.6 Review: simplified execution has five phases: Phase 1 2 3 4 5 Function Op code fetch Operand fetch Data read Free cycle Data store R/W Address read PC++ read PC++ read SP,EAR read PC/SP/$FFFF write SP,EAR Comment Put data in IR Calculate EA Data (ALU) ALU (sets CCR) Results stored 1. Inherent addressing mode has no operand field sometimes there is no data stop sometimes the data for the instruction is implied. clra sometimes the data must be fetched, but the address is implied pula 2. Immediate addressing mode uses a fixed data constant. Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.7 EEPROM A $24 $F800 $F801 $86 $F802 $24 $F803 }ldaa #36 Figure 3.10. Example of the immediate addressing mode. The TExaS simulation of this instruction shows the following two cycles. Opcode fetch R 0xF801 0x86 from EEPROM Operand fetch R 0xF802 0x24 from EEPROM Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.8 3. Direct Page addressing mode uses an 8-bit address access from addresses 0 to $00FF called zero-page. on the 6812 they reference the I/O ports the < operator forces direct addressing A $57 I/O $0035 $0036 $57 $0037 EEPROM $F800 $F801 $96 $F802 $24 $F803 }ldaa 36 Figure 3.11. Example of the direct-page addressing mode. The TExaS 6812 simulation this instruction shows the following three cycles. Opcode fetch R 0xF801 0x96 from EEPROM Operand fetch R 0xF802 0x24 from EEPROM Fetch using EARR 0x0024 0x57 from I/O 4. Extended addressing uses a 16-bit address size of data depends on the op code (which register is uses) access all memory and I/O devices outside Motorola family this addressing mode is called direct the > operator forces extended addressing Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems A $62 RAM $0800 $0801 $62 $0802 Lecture 5.9 EEPROM $F800 $F801 $B6 $F802 $08 $F803 $01 }ldaa $0801 Figure 3.12. Example of the extended addressing mode. The TExaS 6812 simulation of this instruction shows the following four cycles. Opcode fetch R Operand fetch R Operand fetch R Fetch using EARR 0xF801 0xF802 0xF803 0x0801 0xB6 0x08 0x01 0x62 from from from from EEPROM EEPROM EEPROM RAM Common Error: It is wrong to assume the < and > operators affect the amount of data that is transferred. The < and > operators will affect the addressing mode, that is how the address is represented. Observation: Accesses to Registers A, B and CC transfer 8 bits, while accesses to Registers D, X, Y, SP, and PC transfer 16 bits regardless of the addressing mode. 5. PC Relative addressing mode used for the branch instructions stored in the machine code is not the absolute address but the 8-bit signed offset relative distance from the current PC value the PC already points to the next instruction the assembler calculates it for us Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems 1) address of current instruction $F880 bra $F840 2) op code of branch instruction, and size of instruction $F880 $20rr bra $F840 3) address of next instruction $F880 $20rr bra $F840 $F882 4) calculate PC relative addressing rr = destination – address of next instruction = $F840 - $F882 = -$42 = $BE The object code for this instruction will be $20BE. Mark W. Welker ( From Jonathan W. Valvano) Lecture 5.10 Introduction to Embedded Microcomputer Systems 1) address of current instruction $F000 bra $F044 2) op code of branch instruction, and size of instruction $F000 $20rr bra $F044 3) address of next instruction $F000 $20rr bra $F044 $F002 4) calculate PC relative addressing rr = destination – address of next instruction = $F044 - $F002 = $42 The object code for this instruction will be $2042. 1) address of current instruction $F000 bra $F144 2) op code of branch instruction, and size of instruction $F000 $20rr bra $F144 3) address of next instruction $F000 $20rr bra $F144 $F002 4) calculate PC relative addressing rr = destination – address of next instruction = $F144 - $F002 = $142 “Branch out of range” assembly error. Mark W. Welker ( From Jonathan W. Valvano) Lecture 5.11 Introduction to Embedded Microcomputer Systems Lecture 5.12 How to do Lab 2 1) look at TExaS assembly listing machine code execution time (cycles) source code $F02F FE0800 $F032 7E0802 $F035 720800 address [3](45){ROP [3](48){WOP [4](51){rOPw } } } ldx $0800 stx $0802 inc $0800 total execution time (cycles) description 2) Work through the phases 3) Verify by running the TExaS simulation Assume this initial state PC = $F02F $0800 = $0D $0801 = $0A 1) look at TExaS assembly listing $F02F FE0800 [3](45){ROP} ldx $0800 2) Work through the phases R/W R R R R R Addr $F02F $F030 $F031 $0800 $0801 Data $FE $08 $00 $0D $0A changes PC=$F030, IR=$FE PC=$F031 PC=$F032, EAR=$0800 X=$0D0A Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.13 3) TExaS simulation shows the following cycles. Opcode fetch R 0xF02F 0xFE from EEPROM Operand fetch R 0xF030 0x08 from EEPROM Operand fetch R 0xF031 0x00 from EEPROM Fetch msb @ EARR 0x0800 0x0D from RAM Fetch lsb @ EARR 0x0801 0x0A from RAM 0xF02F ldx $0800 A=$0F B=$0A CC=sXhInzvc PC=$F032 X=$0D0A Lab 2: Start a fresh copy of TExaS, and create a new Microcomputer file. Step 1. Execute the Mode->Processor… command and select the MC9S12C32. Save this document as Lab2.uc. Step 2. Download the file Lab2.rtf from the class website, shown below. Click on the Program window and execute the Assemble->Options… command. Make sure the check boxes select the configuration shown in Figure 3.36 in the book. Assemble this program by executing the Assemble->Assemble command. org $3800 ;Calculates RegY = sum(Yi-Xi)**2 I rmb 1 ;loop index 3,2,1 SIZE equ 3 org $4000 main ldx #Xi ldy #0 ;sum=0 ldab #SIZE ;loop counter stab I loop ldaa 0,x ;get data from first array suba SIZE,x ;subtract data from second array bpl ok nega ;make it positive ok tab ;RegA=RegB=abs(Yi-Xi) mul ;RegD=(Yi-Xi)**2 leay d,y ;sum=sum+(Yi-Xi)**2 inx dec I bne loop stop Xi fcb -10,-20,-30 ;first array of data Yi fcb -12,20,-40 ;second array of data org $FFFE ;reset vector fdb main Assembly program used in Lab 2. Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Lecture 5.14 Step 3. Execute this program by hand (using paper and pencil) up to but not including the stop instruction. For each instruction show the memory cycles generated and the values of any registers that change. Show the simplified cycles as described in section 3.2.5. Make eight (8) copies of the following page and fill out one table for each instruction executed. This program will execute 32 instructions, resulting in RegY being the 16-bit result 1704. For each instruction you may or may not need all 5 entries. You do not need to show free cycles or changes to the CCR, but do include changes to the other registers including the IR and EAR. E.g., the first instruction is Instruction: ldx R/W Addr R $4000 R $4001 R $4002 #$401F Data $CE $40 $1F Changes PC=$4001, IR=$CE PC=$4002 PC=$4003, X=$401F Step 4. Activate the FollowPC CycleView InstructionView and LogRecord modes using the commands in the Mode menu. Single step the program using TExaS up to an including the stop instruction. Verify the answers you gave for Step 3. Mark W. Welker ( From Jonathan W. Valvano) Introduction to Embedded Microcomputer Systems Instruction: R/W Addr Data Changes Instruction: R/W Addr Data Changes Instruction: R/W Addr Data Changes Instruction: R/W Addr Data Changes Mark W. Welker ( From Jonathan W. Valvano) Lecture 5.15