Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download 0.35 µm CMOS Design Rules - Engenharia Eletrica
Document related concepts
no text concepts found
Transcript
® Austria Mikro Systeme International AG Schloß Premstätten A-8141Unterpremstätten Austria Tel (++43) 3136-500 Fax (++43) 3136-52501 Fax (++43) 3136-53650 Email [email protected] 0.35 µm CMOS Design Rules 7 Digit Document #: 9931032 Revision #: 2.0 Document control Controlled Copy # Strictly Controlled 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG Version History Version Description 1.0 = Rev. N/C 2.0 1. Change version control (A -> 2.0) 2. Guideline: Ratio of POLY1 area to die area 3. Changed Minimum pad pitch Process Family This document is valid for the following twin-tub 0.35 µm processes: process name no. of mask layers CMOS core module CSA 13 x CSD 14 x CSF 14 x CSI 15 x ) poly capacitor module 5 Volt option x x x x p-substrate, triple metal, single poly, 3.3 Volt Related Documents 0.35 µm CMOS Process Parameters: Doc. 9933016 ESD Design Rules: Doc. 9931020 Standard Family Cells: Doc. 9931021 Assembly Related Design Rules: Doc. 9981005 Note All data represent drawn dimensions. Graphical illustrations are not to scale. Support Technical questions on design rules should be directed to the following department: Process Characterization: Doc. 9931032 e-mail: [email protected] fax: (*43) 3136 500 491 phone: (*43) 3136 500 618 Rev. 2.0 2 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG Table of Contents 1. Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. General Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Process Layer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Structure Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1. NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2. PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3. MIDOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4. POLY1, GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5. POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.6. CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7. MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.8. VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.9. MET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.10. VIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.11. MET3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. 6. Element Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1. NMOS, PMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2. NMOSM, PMOSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3. CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4. RPOLY2, RNWELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5. NMOSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6. VERT10, LAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7. SUBDIODE, WELLDIODE, NWD . . . . . . . . . . . . . . . . . . . . . . . . 23 Periphery Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1. PAD Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2. CORNER Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3. SCRIBE Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Recommended Layout Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc. 9931032 Rev. 2.0 3 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 1. Definitions Mask Layers NTUB DIFF FIMP MIDOX POLY1 POLY2 NPLUS PPLUS CONT MET1 M1HOLE VIA MET2 M2HOLE VIA2 MET3 M3HOLE PAD Note: WN DF IF XM P1 P2 IN IP CT M1 M1 VI M2 M2 V2 M3 M3 PA := := := := := := := := := := := := := := := := := := n-tub layer diffusion layer n-field implant layer mid gate oxide layer (VGATE > 3:3V olt) poly1 layer poly2 layer n+implant layer p+implant layer contact layer (connects MET1 to DIFF, POLY1, POLY2) metal1 layer metal1 slot (metal1 = MET1 and not M1HOLE) via1 layer (connects MET2 to MET1) metal2 layer metal2 slot (metal2 = MET2 and not M2HOLE) via2 layer (connects MET3 to MET2) metal3 layer metal3 slot (metal3 = MET3 and not M3HOLE) pad layer The 2-character symbols are used for short rule names. Definition Layers These layers are not used in chip production. They are necessary for design tools, e.g. design rule check. CAPDEF := DIFCUT := DIODE := PO1CUT := PO2CUT := RESDEF := RESTRM := SFCDEF := ZENER := defines sandwich capacitors excludes DIFF from device extraction marks protection diodes for device extraction excludes dummy POLY1 from device extraction excludes dummy POLY2 from device extraction resistor definition layer resistor terminal layer excludes SFC from checks and automatic layer generation excludes Zener diodes from checks and automatic layer generation Doc. 9931032 Rev. 2.0 4 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG Structures DIFFCON DIFFM NDIFF (DN) NDIFFCON PADVIA1 PADVIA2 PDIFF (DP) PDIFFCON POLY1CON POLY2CON PSUB SCRIBE SCRIBECUT SFC WIDE_MET1 WIDE_MET2 WIDE_MET3 := := := := := := := := := := := := := := := := := diffusion contact (CONT & DIFF) diffusion for 5 volt operation (DIFF & MIDOX) n+diffusion (DIFF & NPLUS) n+diffusion contact (CONT & NDIFF) VIA underneath PAD (VIA & PAD) VIA2 underneath PAD (VIA2 & PAD) p+diffusion (DIFF & PPLUS) p+diffusion contact (CONT & PDIFF) poly1 contact (CONT & POLY1) poly2 contact (CONT & POLY2) p-substrate scribe line border (Peripheral bus + scribe edge, example in SFC) scribe line border cut (example in SFC) standard family cells MET1 width and length > 10 µm MET2 width and length > 10 µm MET3 width and length > 10 µm Elements CORNER := CPOLY := LAT2 := SUBDIODE := NMOS := NMOSM := NMOSH := NWD := WELLDIODE := PMOS := PMOSM := RDIFFP3 := RNWELL := RPOLY2 := VERT10 := corner cell with slotted metal busses poly1-poly2 capacitor (POLY1 & POLY2) lateral PNP transistor (2 µm x 2 µm emitter) parasitic n+p- diode (NDIFF & PSUB & DIODE) n-channel MOSFET n-channel MOSFET with mid gate oxide high voltage n-channel MOSFET parasitic n-p- diode (NTUB & PSUB & DIODE) parasitic p+n- diode (PDIFF & NTUB & DIODE) p-channel MOSFET p-channel MOSFET with mid gate oxide p+diffusion resistor in periphery cells (PDIFF & RESDEF) n-tub resistor (NTUB & RESDEF) poly2 resistor (POLY2 & RESDEF) vertical PNP transistor (10 µm x 10 µm emitter) Doc. 9931032 Rev. 2.0 5 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG Geometric Relations A width A spacing to B A notch A enclosure of B A extension of B A overlap of B Note: WnA SnAB SnAA EnAB EnAB OnAB := := := := := := distance inside_A - inside_A distance outside_A - outside_B (different polygons) distance outside_A - outside_A (same polygon) distance inside_A - outside_B (A contains B) distance inside_A - outside_B (A may intersect B) distance inside_A - inside_B The abbreviations are intended for short design rule names. width spacing notch A A overlap B A B overlap A A extension of B B A enclosure of B A A extension of B not violated B enclosure of A violated 2. General Requirements RUL001 Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05 µm RUL002 Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 °, 135 ° RUL003 Data extrema including SCRIBE. . . . . . . . . . . . . . . . . . . . . . . . . . integral multiple of 5 µm Doc. 9931032 Rev. 2.0 6 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 3. Process Layer Overview Note: Width and spacing are minimum values in µm. layer rule# yWN yIF yDF yXM yP1 yIN yIP yP2 yCT yM1 yVI yM2 yV2 yM3 yPA GDS# width spacing / notch N1y W1y S1yy Mask Layers NTUB 5 2.0 3.0 FIMP 8 DIFF 10 0.5 0.6 MIDOX 14 0.6 0.6 POLY1 20 0.3 0.6 NPLUS 23 0.6 0.6 PPLUS 24 0.6 0.6 POLY2 30 0.7 0.5 CONT 34 0.4 0.5 MET1 35 0.4 0.6 VIA 36 0.5 0.5 MET2 37 0.5 0.6 VIA2 38 0.5 0.5 MET3 39 0.5 0.7 PAD 40 15.0 15.0 M1HOLE 57 M2HOLE 58 M3HOLE 61 Definition Layers SFCDEF 42 ZENER 43 DIFCUT 44 PO1CUT 45 PO2CUT 46 DIODE 47 RESDEF 49 RESTRM 50 CAPDEF 55 generation drawn =NTUB (except SFC) drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn MET1 slots MET2 slots MET3 slots SFC Zener diodes non-standard DIFF non-standard POLY1 non-standard POLY2 parasitic diodes resistors resistor terminals sandwich capacitors e.g.: MET1 width = W1M1, MET1 spacing = S1M1M1. Doc. 9931032 Rev. 2.0 7 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4. Structure Rules 4.1. NDIFF S1INIP Overlap of NPLUS and PPLUS is not allowed (except ZENER) BAD1DF DIFF without NPLUS or PPLUS is not allowed (except ZENER) E1INDF Minimum NPLUS extension of DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1DFIP Minimum DIFF spacing to PPLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1DNWN Minimum NDIFF spacing to NTUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 µm E1WNDN Minimum NTUB enclosure of NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 µm E1WNDN E1INDF NTUB NPLUS NPLUS NDIFF NDIFF S1DNWN PPLUS S1DFIP 4.2. PDIFF E1IPDF Minimum PPLUS extension of DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1DFIN Minimum DIFF spacing to NPLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1DPWN Minimum PDIFF spacing to NTUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm E1WNDP Minimum NTUB enclosure of PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 µm BAD2DF NDIFF and butting PDIFF must be connected with MET1 E1IPDF NTUB PPLUS NPLUS S2DFDF PPLUS PDIFF NPLUS S1DFIN E1WNDP PDIFF NDIFF S1DPWN MET1 Doc. 9931032 Rev. 2.0 8 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.3. MIDOX E1XMDF Minimum MIDOX enclosure of DIFFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm S1DFXM Minimum MIDOX spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm S2DFDF Minimum DIFFM spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µm S2DFDF MIDOX DIFFM DIFFM mid oxide mid oxide 111 000 1111 0000 111 000 1111 0000 E1XMDF Doc. 9931032 Rev. 2.0 DIFF POLY1 S1DFXM 9 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.4. POLY1, GATE S2P1P1 Minimum GATE spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 µm S1DFP1 Minimum POLY1 spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm E1P1DF Minimum POLY1 extension of GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm E1DFP1 Minimum DIFF extension of GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 µm E1DNP1 Minimum NDIFF extension of GATE when butted to PDIFF . . . . . . . . . . . . . . . . 0.6 µm E1DPP1 Minimum PDIFF extension of GATE when butted to NDIFF . . . . . . . . . . . . . . . . 0.6 µm R1P1 Maximum ratio of POLY1 area to touched GATE area . . . . . . . . . . . . . . . . . . . . . . . . 100 Note: POLY1 structures collect electric charge during ion-etching which can be a hazard for associated GATE oxide. A(POLY1) A(GATE) R1P1 POLY1 POLY1 S1DFP1 POLY1 GATE POLY1 GATE GATE DIFF NDIFF E1P1DF E1DNP1 PDIFF S2P1P1 PDIFF E1DPP1 NDIFF E1DFP1 4.5. POLY2 BAD1P2 POLY2 is not allowed over DIFF S1DFP2 Minimum POLY2 spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1P1P2 Minimum POLY1 spacing to POLY2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7 µm 111 000 111 000 DIFF POLY2 S1DFP2 Doc. 9931032 Rev. 2.0 POLY1 S1P1P2 10 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.6. CONT BAD1CT CONT without MET1 is not allowed BAD2CT CONT without DIFF or POLY1 or POLY2 is not allowed BAD3CT POLY1CON is not allowed over DIFF W2CT Fixed CONT size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm x 0.4 µm E1M1CT Minimum MET1 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 µm E1DFCT Minimum DIFF enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm E1P1CT Minimum POLY1 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 µm E1P2CT Minimum POLY2 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm S1CTP1 Minimum DIFFCON spacing to GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.4 µm S1CTDP Minimum NDIFFCON spacing to PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm S1CTDN Minimum PDIFFCON spacing to NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm Note: Butting CONTs are not allowed. S1CTDF Minimum POLY1CON spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 µm S1CTP2 Minimum POLY1CON spacing to POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 µm S1CTDF E1DFCT E1P2CT CONT W2CT S1CTP1 E1M1CT MET1 POLY1 E1P1CT POLY2 NDIFF S1CTP2 S1CTDP POLY1 S1CTDN PDIFF Doc. 9931032 Rev. 2.0 11 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.7. MET1 S2M1M1 Minimum MET1 spacing to WIDE_MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µm MET1 WIDE_MET1 >10 µm >10 µm S2M1M1 R1M1 Minimum ratio of MET1 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 % R2M1 Maximum ratio of MET1 area to connected GATE and CPOLY area . . . . . . . . . . 100 Note: MET1 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET1 without DIFFCONs must be considered. MET1 connected to GATE or CPOLY via MET2 and shorted CPOLY does not contribute. 00000 11111 11111 00000 00000 11111 B DIFF A MET1 POLY1 POLY1 C CONT VIA1 MET1 DIFFCON CPOLY E MET1 MET2 11 00 00 11 00 11 CPOLY D POLY1 G DIFF 11 00 00 11 Doc. 9931032 POLY1 MET1 F DIFF Rev. 2.0 R2M1:area(B+D) / area(A+C+E) F and G do not contribute 12 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG BAD1M1 Insert slots in MET1 > 20 µm 300 µm Note: Insert M1HOLEs in direction of current flow. Standard cells do not contain M1HOLEs. W2M1 Minimum M1HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µm W3M1 Minimum M1HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S3M1M1 Minimum M1HOLE spacing on MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm E1M1M1 Minimum MET1 enclosure of M1HOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0 µm MET1 M1HOLE M1HOLE M1HOLE M1HOLE W2M1 E1M1M1 W3M1 Doc. 9931032 Rev. 2.0 S3M1M1 13 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.8. VIA BAD1VI VIA without MET1 is not allowed BAD2VI VIA without MET2 is not allowed BAD3VI VIA over GATE is not allowed W2VI Fixed VIA size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 µm x 0.5 µm E1M1VI Minimum MET1 enclosure of VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 µm E1M2VI Minimum MET2 enclosure of VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 µm E2M1VI Minimum WIDE_MET1 enclosure of VIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm MET1 MET1 WIDE_MET1 VIA E2M1VI E1M2VI MET2 MET2 VIA W2VI E1M1VI Doc. 9931032 Rev. 2.0 14 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.9. MET2 S2M2M2 Minimum MET2 spacing to WIDE_MET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 µm >10 µm MET2 WIDE_MET2 >10 µm S2M2M2 BAD1M2 Stacking MET2, MET1, POLY2, POLY1 is not allowed S1M2M1 Minimum MET2 spacing to MET1 over CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 µm S1M1M2 Minimum MET1 spacing to MET2 over CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 µm MET2 MET1 MET2 MET1 CPOLY POLY1 S1M2M1 S1M1M2 R1M2 Minimum ratio of MET2 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 % R2M2 Maximum ratio of MET2 area to connected GATE and CPOLY area . . . . . . . . . . 100 Note: MET2 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET2 without DIFFCONs must be considered. MET2 connected to GATE or CPOLY via MET3 and shorted CPOLY does not contribute. Doc. 9931032 Rev. 2.0 15 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG BAD2M2 Insert slots in MET2 > 20 µm 300 µm Note: Insert M2HOLEs in direction of current flow. Standard cells do not contain M2HOLEs. W2M2 Minimum M2HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 µm W3M2 Minimum M2HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S3M2M2 Minimum M2HOLE spacing on MET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm E1M2M2 Minimum MET2 enclosure of M2HOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0 µm MET2 M2HOLE M2HOLE M2HOLE M2HOLE W2M2 E1M2M2 W3M2 S3M2M2 4.10. VIA2 BAD1V2 VIA2 without MET2 is not allowed BAD2V2 VIA2 without MET3 is not allowed W2V2 Fixed VIA2 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 µm x 0.5 µm E1M2V2 Minimum MET2 enclosure of VIA2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2 µm E1M3V2 Minimum MET3 enclosure of VIA2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 µm E2M2V2 Minimum WIDE_MET2 enclosure of VIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm MET2 MET2 WIDE_MET2 VIA2 E2M2V2 E1M3V2 MET3 MET3 VIA2 W2V2 E1M2V2 Doc. 9931032 Rev. 2.0 16 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 4.11. MET3 S2M3M3 Minimum MET3 spacing to WIDE_MET3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 µm >10 µm MET3 WIDE_MET3 >10 µm S2M3M3 R1M3 Minimum ratio of MET3 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 % R2M3 Maximum ratio of MET3 area to connected GATE and CPOLY area . . . . . . . . . . 100 Note: MET3 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET3 without DIFFCONs must be considered. MET3 connected to shorted GATE or CPOLY does not contribute. BAD1M3 Insert slots in MET3 > 20 µm 300 µm Note: Insert M3HOLEs in direction of current flow. Standard cells do not contain M3HOLEs. W2M3 Minimum M3HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 µm W3M3 Minimum M3HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S3M3M3 Minimum M3HOLE spacing on MET3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm E1M3M3 Minimum MET3 enclosure of M3HOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0 µm MET3 M3HOLE M3HOLE M3HOLE M3HOLE W2M3 E1M3M3 W3M3 Doc. 9931032 Rev. 2.0 S3M3M3 17 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5. Element Rules 5.1. NMOS, PMOS W2P1 Minimum GATE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm W2DF Minimum GATE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm POLY1 GATE W2DF DIFF W2P1 5.2. NMOSM, PMOSM W3P1 Minimum GATE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 µm W3DF Minimum GATE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 µm POLY1 MIDOX GATE W3DF DIFF W3P1 Doc. 9931032 Rev. 2.0 18 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5.3. CPOLY BAD1IN CPOLY is not allowed over NPLUS BAD1IP CPOLY is not allowed over PPLUS W2P2 Minimum CPOLY width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 µm S2P2P2 Minimum CPOLY spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 µm E1P1P2 Minimum POLY1 enclosure of POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µm S1INP2 Minimum NPLUS spacing to CPOLY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0 µm S1IPP2 Minimum PPLUS spacing to CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µm S1INP2, S1IPP2 POLY1 NPLUS POLY2 POLY2 CPOLY CPOLY W2P2 Note: S2P2P2 PPLUS E1P1P2 See chapter 8. for recommended layout structure of CPOLY. Precision capacitor matching is improved with non-minimum POLY2 width and spacing. Doc. 9931032 Rev. 2.0 19 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5.4. RPOLY2, RNWELL BAD2IN RPOLY2 is not allowed over NPLUS BAD2IP RPOLY2 is not allowed over PPLUS S2INP2 Minimum NPLUS spacing to RPOLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 µm S2IPP2 Minimum PPLUS spacing to RPOLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 µm RUL004 Fixed RESTRM enclosure of RESDEF edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 µm Note: RESDEF and RESTRM are necessary for all resistors. Note: Recommended minimum number of squares. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .L/W 5 RESTRM PPLUS NPLUS RESDEF S2INP2, S2IPP2 POLY2 W 1 2 3 4 5 RUL004 L RUL004 Note: Use the following effective number of squares for resistance calculation of corners: 1/2 1 Note: 1 90° 1 135° 1/3 1 See chapter 8. for recommended layout structure of poly resistors. Doc. 9931032 Rev. 2.0 20 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5.5. NMOSH BULK FOX SOURCE GATE DRAIN-EDGE-FOX FOX PDIFF DRAIN FOX NDIFF CHANNEL FOX NDIFF DRAIN-WELL PSUB PDIFF NDIFF NDIFF WIDTH MIDOX POLY1 NTUB LENGTH Note: The layout of NMOSH is predefined and available on request. Only WIDTH may be changed. Doc. 9931032 Rev. 2.0 21 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5.6. VERT10, LAT2 VERT10 COLLECTOR FOX FOX FOX NDIFF PDIFF BASE EMITTER BASE FOX FOX PDIFF COLLECTOR NDIFF FOX PDIFF NTUB - BASE PSUB - COLLECTOR LAT2 COLLECTOR BASE FOX BASE EMITTER GATE GATE FOX FOX PDIFF COLLECTOR NDIFF FOX PDIFF PDIFF PDIFF FOX NDIFF FOX PDIFF NTUB - BASE PSUB - PARASITIC COLLECTOR Note: The layouts of VERT10 and LAT2 are predefined and available on request. They must not be changed. Doc. 9931032 Rev. 2.0 22 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 5.7. SUBDIODE, WELLDIODE, NWD SUBDIODE DIODE WELLDIODE NTUB NDIFF NWD DIODE DIODE NTUB PDIFF PSUB Note: SUBDIODE, WELLDIODE, NWD are only intended for the simulation of reverse leakage currents and junction capacitances in periphery cells. It is not recommended to use these diodes as active circuit elements. Doc. 9931032 Rev. 2.0 23 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 6. Periphery Rules ESD Related Rules: See Doc. 9931020. 6.1. PAD Rules BAD1PA PAD is not allowed over DIFF BAD2PA PAD is not allowed over POLY1 BAD3PA PAD is not allowed over POLY2 BAD3V2 PADVIA2 over PADVIA1 is not allowed W2PA Bond PAD size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.0 µm x 85.0 µm Note: Test PAD size 60 µm x 60 µm. Probe PAD size 15 µm x 15 µm. Bond pads and test pads must have a minimum pitch of 100 µm. The following rules are only valid for bond pads. E1M1PA Minimum MET1 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µm E1M2PA Minimum MET2 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µm E1M3PA Minimum MET3 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µm E3M1VI Minimum MET1 enclosure of PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 µm E3M2VI Minimum MET2 enclosure of PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 µm E3M2V2 Minimum MET2 enclosure of PADVIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 µm E3M3V2 Minimum MET3 enclosure of PADVIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 µm S2VIVI Minimum PADVIA1 spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 µm S2V2V2 Minimum PADVIA2 spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 µm S1VIV2 Minimum PADVIA2 spacing to PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 µm S1DFPA Minimum PAD spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S1P1PA Minimum PAD spacing to POLY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S1P2PA Minimum PAD spacing to POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S1M1PA Minimum PAD spacing to MET1 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S1M2PA Minimum PAD spacing to MET2 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm S1M3PA Minimum PAD spacing to MET3 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 µm R1VIPA Minimum ratio of PADVIA1 area to PAD area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 % R1V2PA Minimum ratio of PADVIA2 area to PAD area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 % Doc. 9931032 Rev. 2.0 24 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG W2PA VIA / VIA2 CONT E1M1PA S1DFPA DIFF PAD E1M2PA S1P1PA E1M3PA POLY1 S1P2PA E3M1VI POLY2 E3M2VI S1M1PA E3M2V2 MET1 E3M3V2 MET1 / MET2 / MET3 S1M3PA MET2 S1M2PA VIA VIA2 MET3 R1VIPA R1V2PA VIA VIA VIA2 S2V2V2 VIA2 VIA Doc. 9931032 S2VIVI VIA Rev. 2.0 S1VIV2 25 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 6.2. CORNER Rules RUL005 CORNER must be used for die sizes 4mm 4mm. Note: This prevents cracks in corners of the die during thermal stress. RUL006 Insert a continous 2 µm wide slot in 20 µm wide MET. RUL007 Draw MET and slots at 45°. MET1 MET2 MET3 RUL006 ER N R O C RUL007 die corner Note: The layout of CORNER is predefined and available on request. Doc. 9931032 Rev. 2.0 26 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 6.3. SCRIBE Rules SCRIBE is a Standard Family Cell enclosing the design data. The inner edge of SCRIBE is butted to the data extrema of the design. The SFC SCRIBE must be included in all designs without modification. The SFC SCRIBECUT shows how to cut SCRIBE in mixed signal designs with separated supplies. RUL008 Data extrema excluding SCRIBE . . . . . . . . . . . . . . . . . . . . . . . . integral multiple of 5 µm Note: Follows from rule RUL003 and SCRIBE width of 35.0 µm. DESIGN_DATA (0,0) 35 µm SCRIBE Doc. 9931032 Rev. 2.0 27 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 7. Guidelines 7.1 Connect NTUB with as much DIFFCON area as possible. Maximum DIFFCON spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 µm 7.2 Where area permits non-minimum geometries should be used. Note: This is particularly applicable to structures where the layout allows modifications without degrading circuit performance or increasing the overall size. 7.3 Minimum ratio of POLY1 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 % Doc. 9931032 Rev. 2.0 28 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG 8. Recommended Layout Structures Precision Resistors guardring dummy structures with PO1CUT 4 x Runit 1 x Runit 3 x Runit 1 x Runit 1 x Runit matched bends 1 Runit Doc. 9931032 1 Runit Rev. 2.0 3 Runit 1 Runit 4 Runit 29 of 30 0.35 µm CMOS Design Rules ® Austria Mikro Systeme International AG Precision Capacitors guard ring unit cap 135 degree corners equal area/perimeter ratio for non-unit cap dummy structures with PO2CUT Cunit Doc. 9931032 Rev. 2.0 1.4 Cunit 30 of 30 0.35 µm CMOS Design Rules Austria Mikro Systeme Spec. ENG - 51A Rev. 1.0 R Austria Mikro Systeme International AG Schloß Premstätten A-8141Unterpremstätten Austria Tel (++43) 3136-500 Fax (++43) 3136-52501 Fax (++43) 3136-53650 Email [email protected] 0.35 µm CMOS Design Rules Attachment 7 Digit Document #: 9931032 Revision #: 2.0 Page 1 / 2 Release Date 28.07.00 00:00:00 . 0.35 µm CMOS Design Rules Austria Mikro Systeme Spec. ENG - 51A Rev. 1.0 Attachment to 7. Guidelines 7.4 7.5 Precision analog NMOS, PMOS, NMOSM, PMOSM should not be covered with MET1 or MET2. If this is not possible MET1 and MET2 covering of matching transistors should be identical. Minimum channel length for critical analog NMOS transistors . . . . . . . . . . . . . . 0.6 µm Minimum channel length for critical analog NMOSM transistors . . . . . . . . . . . . 1.0 µm Note: Critical analog NMOS and NMOSM transistors are: 1. Transistors biased at (V th < VGS < VDS /2, VDS = VDSmax ). Low temperature applications are especially critical. 2. Transistors used in circuits sensitive to Vth shift. Page 2 / 2 Release Date 28.07.00 00:00:00 .
