Download L2AB-Fall06

318-595 Lab 2A
Safety Standards
& Block-Block Interface Definitions
• Objectives
– Introduction to Global Safety Standards
– Determine the product main applicable safety standards
– Update-Associate PL to Block Level Standard
Requirements
• Deliverable 1 (Team Deliverable)
1. Find and Document at least 3 Safety Standards applicable to your
product using at least 1 from UL
2. Find and Document at least 2 Specific Safety Devices that you will
incorporate in your design and where they will be used
3. Capture 1 and 2 above on at least 1 Product Safety Slide
summarizing the above Safety Standards and Devices – Add this
slide to your overall presentation
318-595 Lab 2A
Block Interface Signals
•
Deliverable 2 – Individual Assignment for Block Owners
1. For Each Design Block: Define and document all of your Block-Block
Interface Signals in the spreadsheet template included within the 3 main
areas:
•
•
•
Power Signals including Power Consumed, Power Supplied
Digital Interface Signals (including busses)
Analog Interface Signals
2. Review ALL “Inter-block” signals and document Approval and “OK” in
your spreadsheets to record signal agreements.
3. See attached Block Interface Signal Table Excel Tool
•
•
•
Summary Tab is Locked
Data Flows from Power, Digital and Analog Tabs
Some Cells have pull-down selections, Others are Free Form Values
BLOCK OUTPUTS NEED TO AGREE WITH BLOCK INPUTS !!!
4. Deliverables for each block include:
•
•
Block Interface Excel File – Electronic
Powerpoint Summary Slide – Electronic and Paper
318-595 Lab 2A
Block Signal Table: Power
Power Signals
Power1 VCC +5
Power2 VCC -15V
Power3 AC Input
Power4 VCC +12V
Type
DC Power
DC Power
AC Power
DC Power
Direction
Input
Input
Input
Output
Block-Block
Interconnect
PCB Trace
PCB Trace
Connector-Cable
Connector-Cable
Voltage
Nominal
5.0V
15.0V
120V
12.0V
Voltage Range
Min
Max
4.75V
14.25V
102V
11.88V
5.25V
15.75V
132V
12.12V
Freq
Nominal
DC
DC
60Hz
DC
Freq Range
Min
Max
0
0
57Hz
0
N/A
N/A
63Hz
N/A
% V-Reg
Max
5.00%
5.00%
15.00%
1.00%
V-Ripple
Max
0.1V
0.25V
N/A
0.01V
Power Signal Design Guidelines
• Assume ALL Blocks will consume and/or provide power
• Consumers must provide worst case demand to Providers (owners)
• Blocks that supply power may also consume it and must allow for their inefficiencies
• If you have bipolar (+/-) analog signals you will need split supplies
• Power Supply Margin = ~50%
• Try to keep DC voltage supplies at standard values including 3.3, 5, 9 and 12 VDC
• Must specify both nominal and range of voltages
• Must specify maximum total current for each voltage
• Frequency range for AC voltages
• Specify % regulation and max voltage ripple for DC voltages
• Must specify Block-Block Interconnect Means for each signal
• If a digital signal is also a power signal, treat it as a power signal
318-595 Lab 2A
Block Signal Table: Digital
Digital Signals
Type
Digital1 Data15-Data0
Digital2 Bit3-Bit0
Digital3 D7-D0
Blue LED Drive
Digital
Digital
Digital
Digital
Dir
Input
Input
Bidir
Output
Block-Block
Interconnect
PCB Trace
PCB Trace
PCB Trace
PCB Trace
Output
Structure
N/A
N/A
Tristate
Other
Input
Structure
Standard
Schmitt
Standard
N/A
Tech
TTL
CMOS
TTL
Other
Freq
Nominal
2.0Mhz
0.5Mhz
5.0Mhz
DC
Logic
Voltage
5V
5V
5V
12V
Vih Min
2.0V
N/A
2.0V
Iih Max
400uA
10uA
400uA
Input Characteristics
ViL Max
IiL Max
0.8V
N/A
0.8V
-1.2mA
-10uA
-1.2mA
O
Vth Min
N/A
1.5V
N/A
Vth Max
N/A
2.6V
N/A
Voh Min
N/A
N/A
2.4V
11.5V
Digital Signal Design Guidelines
• A digital signal is one that conveys two levels of information (ie; 1/0, On/Off,
etc)
• Must classify direction from your block: Input, Output or Bidirectional
• Must specify Block-Block Interconnect Means for each signal
• For Inputs classify as Standard or Schmitt Trigger
• Inputs must have Vih, ViL, (or Vth), Iih and IiL limits
• For Outputs classify as Totem Pole, Open Collector, or Tristate
• Outputs must have Voh, VoL, Ioh and IoL limits
• If unsure, start by assuming Std TTL levels, Std Input, Totem Pole Output
Std TTL: Vih => 2.0V, ViL <= 0.8V, Iih <= 40uA, IiL <= -1.6mA;
16mA
•
•
Voh => 2.4V, VoL <= 0.4V, Ioh <= -400uA, IoL <=
For noisy or slow transition digital signals, use a Schmitt trigger input
Consider optical isolation when digital signals are needed to control or sense
power electronics or high voltage electronics
318-595 Lab 2A
Block Signal Table: Analog
Analog Signals
Analog1 RF Amp Output
Analog2 Audio Output
Analog3 Carrier Input
Type
Analog
Analog
Analog
Direction
Output
Output
Input
Block-Block
Interconnect
Coupling
PCB Trace
Direct
Connector-Cable Capacitive
Wire
Xfmr
Voltage Max
Amplitude
5.0V
1.0V
1.0V
Impedance
Min
Max
800 ohm
6.8ohms
9Kohms
1.2Kohm
9.2ohms
11Kohms
Freq Range
Min
Max
450Khz
20
87.749M
460Khz
20Khz
87.751M
Leakage
Max
10uA
N/A
10uA
Analog Signal Design Guidelines
• By default if a signal is not a Power signal, nor a Digital signal it becomes an
analog signal
• Classify direction of the signal with respect to the block, Input, Output or
BiDir
• Must specify Block-Block Interconnect Means for each signal
• Classify the coupling of the signal as Direct, Capacitive, Xfmr or Other
• Classify the maximum voltage (amplitude), use peak values not RMS
• For input signals, classify the min-max input impedance the signal will be
loaded with
• For output signals, classify the min-max output impedance the signal will be
driven from
• Classify the min-max frequency range for the signal
• Finally list any appreciable leakage current allowed for the signal if
applicable
318-595 Lab 2A
Block Signal Table: Summary
Power Signals
Power1 VCC +5
Power2 VCC -15V
Power3 AC Input
Power4 VCC +12V
Digital Signals
Digital1 Data15-Data0
Digital2 Bit3-Bit0
Digital3 D7-D0
Blue LED Drive
Analog Signals
Analog1 RF Amp Output
Analog2 Audio Output
Analog3 Carrier Input
Type
DC Power
DC Power
AC Power
DC Power
Type
Digital
Digital
Digital
Digital
Type
Analog
Analog
Analog
Direction
Block-Block
Interconnect
Input
Input
Input
Output
PCB Trace
PCB Trace
Connector-Cable
Connector-Cable
Dir
Block-Block
Interconnect
Input
Input
Bidir
Output
Direction
Output
Output
Input
PCB Trace
PCB Trace
PCB Trace
PCB Trace
Block-Block
Interconnect
PCB Trace
Connector-Cable
Wire
Voltage
Nominal
5.0V
15.0V
120V
12.0V
Voltage Range
Min
Max
4.75V
14.25V
102V
11.88V
5.25V
15.75V
132V
12.12V
Output
Input
Structure Structure
N/A
N/A
Tristate
Other
Standard
Schmitt
Standard
N/A
Tech
TTL
CMOS
TTL
Other
CouplingVoltage Max
Amplitude
Direct
5.0V
Capacitive 1.0V
Xfmr
1.0V
Freq
Nominal
DC
DC
60Hz
DC
Freq
Nominal
2.0Mhz
0.5Mhz
5.0Mhz
DC
Impedance
Min
Max
800 ohm
6.8ohms
9Kohms
Freq Range
Min
Max
57Hz
Logic
Voltage
5V
5V
5V
12V
N/A
N/A
63Hz
N/A
Vih Min
2.0V
N/A
2.0V
Freq Range
Min
Max
1.2Kohm 450Khz
9.2ohms 20
11Kohms 87.749M
460Khz
20Khz
87.751M
% V-Reg
Max
0.05
0.05
0.15
0.01
Iih Max
V-Ripple Current
Max
Max
0.1V
0.25V
N/A
0.01V
1.2A
0.5A
1.0A
0.3A
Input Characteristics
ViL Max IiL Max
400uA
10uA
400uA
0.8V
N/A
0.8V
-1.2mA
-10uA
-1.2mA
Leakage
Max
10uA
N/A
10uA
• This tab is locked and all information flows from
individual Power, Digital and Analog Tabs
318-595 Lab 2B
EMC and Block Interface Signals
• Objectives
–
–
–
–
Introduction to Electromagnetic Compatibility Stds
Introduction to Global AC Power and Stds
Document Applicable EMC Stds
Update your requirements at product and block level inputs to account
for proper power and EMC specifications
• Deliverable – Team & Individual Assignment
– Update your Product Level Requirements to include all applicable EMC Stds
your product should be tested to and the accompanying association to each of
your Blocks – See List
– Develop 1-2 slides describing overall product level EMC requirements as
well as standard requirements for power inputs
– Update the Excel Requirement Spreadsheet with the above and submit
318-595 Lab 2B
EMC Standards Summary
US/FCC:
47 CFR 15 - Radio Frequency Devices
47 CFR 18 - Industrial Scientific and Medical Equipment
IEC: 60601-1-2 Electromagnetic compatibility - Requirements and tests
61000-3-2 EMC Part 3: Limits - Section 2: Limitation of harmonics in low-voltage supplies <16A
61000-3-3 EMC Part 3: Limits - Section 3: Limitation of voltage fluctuations and flicker in low-voltage supplies <16A
61000-3-5 EMC Part 3: Limits - Section 5: Limitation of voltage fluctuations and flicker in low-voltage supplies >16A
61000-4-1 EMC Part 4: Test/measurement techniques - Section 1: Overview of immunity tests
61000-4-2 EMC Part 4: Test/measurement techniques - Section 2: ESD immunity tests
61000-4-3 EMC Part 4: Test/measurement techniques - Section 3: Radiated radiofrequency immunity tests
61000-4-4 EMC Part 4: Test/measurement techniques - Section 4: Electrical fast transient/burst immunity tests
61000-4-5 EMC Part 4: Test/measurement techniques - Section 5: Surge immunity tests
61000-4-6 EMC Part 4: Test/measurement techniques - Section 6: Conducted radiofrequency immunity tests
61000-4-7 EMC Part 4: Test/measurement techniques - Section 7: General guide on harmonics measurement and instrum.
61000-4-8 EMC Part 4: Test/measurement techniques - Section 8: Power frequency magnetic field immunity tests
61000-4-9 EMC Part 4: Test/ measurement techniques - Section 9: Pulsed magnetic field immunity tests
61000-4-10 EMC Part 4: Test/measurement techniques - Section 10: Damped oscillatory magnetic field immunity tests
61000-4-11 EMC Part 4: Test/measurement techniques - Section 11: Voltage dips, short interruptions and variations
CISPR:
11 Limits and methods of measurement for Industrial, Scientific and Medical Equipment
16 Specifications for Radio Interference Measuring Apparatus and Measurement Methods
22 Limits and Methods of Measurements of Radio Interference of Information Technology Equipment
For all applicable Stds, your Product Level Requirements should include Engineering Test
Limits in addition to Certification Test Limits