Download Design and Implementation of fast multiplier in FPGA

GATE DIFFUSION
INPUT: A low power
digital circuit design
By
Khoirom Johnson Singh
Under the guidance of
Huirem Tarunkumar
www.khoirom.wix.com/johnson
DEPARTMENT OF ELECTRONICS AND COMMUNICATION, NIT MANIPUR
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Content
1.
2.
3.
4.
5.
6.
Introduction
Literature Review
Literature Review Conclusion
Project Plan
Project Progress
Reference
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1. Introduction
What is power dissipation?
• The rate at which energy is taken from sources and converted into
heat.
Do we want heat in digital circuit/chips?
• No
Then why??
• Because it may cause circuit failure may be permanent or
temporary.
• For every 10 degree Celsius rise in temperature roughly doubles
the failure rate.
• So, it must be dissipated from the circuit to avoid increase in
circuit temperature.
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Why Low-power?
• High chip density (number of
transistor increase) /Power
density.
• High performance computing
system characterized by large
power dissipation.
• Increased market demand for
portable consumer electronics
powered by batteries.
• E.g. smartphones,tabs,laptops etc.
• Another major demand for low
power chips comes from
environmental concerns.
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Early technology
Complementary Metal Oxide Semiconductor
Device(CMOS).
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Complementary CMOS:
VDD
• A CMOS gate consists of two networks- the pull-up
(PUN) and pull-down (PDN) network.
• n-inputs are distributed to both PUN & PDN.
• PUN: make a connection from VDD to F when
F(a1,a2,….an)=1.
• PDN: make a connection from VDD to ground when
F(a1,a2,…..an)=0.
• The PUN and PDN networks are constructed in a
mutually exclusive fashion such that one and only one
of the network is conducting in steady state.
a1
a2
an
PUN
F(a1,a2,….an)
a1
a2
an
PDN
GND
Fig1: CMOS logic gate
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Rules for CMOS design
A
B
A
B
• A set of rules for CMOS
implementation is:
In case of AND function all
Fig 2: NMOS series(A.B) & parallel(A+B).
PMOS are connected in parallel
and NMOS are connected in
A
B
A
B
series.
In case of OR function all PMOS
Fig 3: PMOS parallel(A.B) & series(A+B).
are connected in series and
NMOS are connected in parallel.
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Gate Diffusion Input(GDI)
P
PMOS
• The GDI cell is almost similar to a CMOS inverter structure.
• In a CMOS inverter the source of PMOS is connected
to VDD and the source of NMOS is grounded.
A GDI cell consists of three inputs:
1. G-common inputs to the gate of PMOS and NMOS
2. N-input to the source/drain of NMOS
3. P-input to the source/drain of PMOS
 One major difference between CMOS and GDI is that in
GDI (N,P&G) terminals could be given a supply VDD or
can be grounded or can be supplied with input signal depending
upon the circuit to design and hence effectively minimizing the
number of transistors used.
G
OUT
NMOS
N
Fig.4: GDI Cell
VDD
Vin
Vout
GND
Fig.5:CMOS inverter
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Logic function (GDI)
N
P
G
OUT GATE
0
1
A
𝐴
NOT
B
0
A
AB
AND
1
B
A
A+B
OR
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2.Literature Review
Title: Gate-Diffusion Input (GDI) : A Power- Efficient Method for Digital
Combinatorial Circuits
Authors: Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner
IEEE Transactions on very large scale integration (VLSI) system, VOL.10,No.5
October 2002
 Numerous logic gates and high-level digital circuits are implemented in various
methods and process technologies and their simulation results are discussed.
 The power consumption is reduced by 45% as compared to CMOS.
 Lesser number of transistors are used in GDI technology.
 Lesser area as compared to CMOS.
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Title: Gate Diffusion Input: A technique for fast digital circuits(implemented on
180nm technology)
Author: Sudeshna Sarkar, Monika Jain, Arpita Saha, Amit Rathi
IOSR Journal of VLSI and Signal Processing(IOSR-JVSP) Volume 4, Issue 2,
Ver. IV(Mar-Apr. 2014), PP 49-53 e-ISSN: 2319
 The GDI technique has been presented.
 Lesser number of gates to design a circuit which is desirable for fast and low
power applications.
 Comparison between GDI and CMOS techniques has also depicted.
 The GDI technique can be successfully applied to larger digital circuits like
adder.
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Title: GDI Technique: A Power- Efficient Method for Digital Circuits.
Authors: Kunal & Nidhi Kedia
IJAEEE ISSN(print) : 2278-8948, Volume -1, Issue-3,2012
 A novel GDI technique for low-power design was presented.
 The power consumption reduced by 45% as compared to CMOS
technology.
 GDI will allow high density of fabrication.
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Title: A Review on Gate Diffusion Input(GDI)
Author: Jashanpreet Kaur, Navdeep Kaur and Amit Grover.
International Journal of Advance Research in Electronics, Electrical &
Computer Application of Engineering & Technology Vol.2, Issue 4, PP 385-391
July 2014
 GDI is the advanced digital circuit designing technique in the market place
today.
 It offers reduced area, less power consumption, high speed when compared
to CMOS.
 GDI provides circuit design with reduced number of transistors.
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3. Literature Review
Conclusion
 GDI provides less area of logic design as
compared to CMOS logic design.
 The power consumption of GDI is reduced by
45% as compared to CMOS technology.
 Faster in speed up to 30% as compared to
CMOS logic design.
 GDI provides circuit design with reduced
number of transistors.
 Layout area is very small as compared to other
logic design technologies.
GATES
Bottom Line: Lesser number of transistors are
the main factor for low power consumption.
CMOS
GDI
INVERTER
2
2
OR
6
2
AND
6
2
NOR
4
4
NAND
4
4
XOR
12
4
XNOR
16
4
Fig 6: Transistor count comparison
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4. Project Plan
Performance and power dissipation
Comparison
Comparison of complex circuits
in terms of power dissipation&
delay using Cadence virtuoso.
Implementation of complex circuit
Implementation of complex
digital circuits like FullAdder in Cadence virtuoso.
Power dissipation comparison
(CMOS & GDI)
NOT, OR, AND, NAND,
NOR&XOR logic gates in
Cadence virtuoso.
Implementation of various
logic gates(CMOS & GDI)
NOT, OR, AND, XOR, NAND &
NOR logic gates in Cadence
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virtuoso.
5. Project Progress
 CMOS INVERTER, AND & OR Logic designs are
implemented
Fig 7: SCHEMATIC DIAGRAM FOR CMOS INVERTER.
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 TRANSIENT ANALYSIS FOR CMOS INVERTER AND DYNAMIC POWER
DISSIPATION
IN
OUT
1
0
0
1
Fig 8: Transient analysis of CMOS inverter.
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 SCHEMATIC DIAGRAM FOR CMOS AND LOGIC DESIGN
Fig 9: Schematic diagram for CMOS AND logic design
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 TRANSIENT ANALYSIS FOR CMOS AND Logic design & its DYNAMIC
POWER DISSIPATION
IN
OUT
0
0
0
0
1
0
1
0
0
1
1
1
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Fig 10: Transient analysis of CMOS AND logic design.
 SCHEMATIC DIAGRAM FOR CMOS OR LOGIC DESIGN
Fig 11: Schematic diagram for CMOS OR logic design.
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 TRANSIENT ANALYSIS FOR CMOS OR Logic design & its DYNAMIC
POWER DISSIPATION
IN
OUT
0
0
0
0
1
1
1
0
1
1
1
1
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Fig 12: Transient analysis of CMOS OR logic design
Paper Acceptance
Title: “A Review on Gate Diffusion Input (GDI): A New
Method for Rapid Digital Circuits”
International Conference on “EMERGING TRENDS IN SCIENCE
AND ENGINEERING RESEARCH (ETSER-2015)”
2-4 December 2015
NATIONAL INSTITUTE OF TECHNOLOGY MANIPUR
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Copyright © 2015 by khoirom Johnson singh
6. References
[1] A. Morgenshtein, A. Fish and I.A. Wagner, “Gate diffusion input (GDI) a powerefficient method for Digital Combinatorial Circuit,” Journal of IEEE Trans. On VLSI
System, Vol.10, pp. 566-581, Oct. 2002.
[2] Kunal and Nidhi Kedia “ GDI Technique: A power-efficient method for digital
circuits” Journal of IJAEEE Vol-1, Issue-3, 2012, ISSN (print): 2278-8948.
[3] Sudeshna Sarkar, Monika Jain, Arpita Saha and Amit Rathi “ Gate diffusion
input: A new technique for fast digital circuit”
Journal of IOSR-JVSP, Vol 2, Issue 2, Ver. IV (Mar-Apr, 2014), pp 49-53.
[4] Jashanpreet Kaur, Navdeep Kaur and Amit Grover “ A Review on Gate Diffusion
input (GDI)”Vol, 2 issue 4, July 2014, PP 385-391.
[5] Digital Integrated Circuits by Jan M. Rabaey, Anantha Chandrakasan and
Borivoje Nikolic, 2nd edition, ISBN-978-81-203-2257-8.
[6] R. Uma and P. Dhavachelvan “ Modified Gate Diffusion input technique: A new
technique for enhancing performance in full adder circuits”. 2nd International
conference on communication, computing and security [ICCCS-2012].
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End of Slide
(KHURUMJARI)
Thank You For Your Time
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Copyright © 2015 by khoirom Johnson singh